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Towards Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays

Chen Zhao, Casey Duckering, Andi Gu, Nishad Maskara, Hengyun Zhou

arXiv:2604.16209v2quant-phcs.IT

TL;DR

Quantum error correction needs lower qubit overhead, while practical finite-size qLDPC codes often have rates around or below 1/10. This paper co-designs ultra-high-rate affine-permutation CSS codes with reconfigurable neutral-atom arrays and a hierarchical decoder, achieving circuit-level logical error rates near the teraquop regime and placing the codes near a heuristic finite-blocklength Pareto frontier.

  • Problem

    Finite-size qLDPC codes with distances suitable for large-scale operations often achieve encoding rates around or below 1/10, limiting reduction of quantum-error-correction overhead.

  • Method

    The paper co-designs Kasai-style affine-permutation CSS codes with neutral-atom transport constraints and evaluates them using a hierarchical decoder combining belief propagation with integer-programming fallback.

  • Results

    The codes achieve circuit-level logical error rates near the teraquop regime at p = 0.1% and lie close to a heuristic finite-blocklength Pareto frontier.

  • Takeaways & Limitations

    Ultra-high-rate quantum error correction can achieve competitive performance in regimes relevant to proposed utility-scale quantum algorithms.

  • Takeaways & Limitations

    The work focuses on memory performance; extending the approach to full fault-tolerant computation requires low-weight logical bases and optimized surgery gadgets.

Abstract

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Quantum error correction is widely believed to be essential for large-scale quantum computation, but the required qubit overhead remains a central challenge. Quantum low-density parity-check codes can substantially reduce this overhead through high-rate encodings, yet finite-size instances with practical logical error rates often achieve encoding rates only around or below $1/10$. Here, building on a recent ultra-high-rate construction by Kasai, we identify new structural conditions on the underlying affine permutation matrices that make encoding rates exceeding $1/2$ compatible with efficient implementation on reconfigurable neutral atom arrays. These conditions define a co-designed family of ultra-high-rate quantum codes that supports efficient syndrome extraction and atom rearrangement under realistic parallel control constraints. Using a hierarchical decoder with high accuracy and good throughput, we study the performance under a circuit-level noise model with $p=0.1\%$, achieving per-logical-per-round error rates of $1.3_{-0.9}^{+3.0} \times 10^{-13}$ with a $[[2304,1156,\leq 14]]$ code and $2.9_{-1.5}^{+3.1} \times 10^{-11}$ with a $[[1152,580,\leq 12]]$ code. We compare these codes against a heuristic Pareto frontier for finite-blocklength codes relating block length, encoding rate, and logical error rates, and find that our codes lie near the frontier. These results approach the teraquop regime, highlighting the promise of this code family for practical ultra-high-rate quantum error correction.

1. INTRODUCTION

The paper addresses the qubit overhead of quantum error correction by adapting Kasai’s ultra-high-rate construction for experimentally relevant neutral-atom systems. It develops codes exceeding rate 1/2 and reports circuit-level logical error rates near the teraquop regime.

  • Existing finite-size qLDPC constructions with distances for large-scale operations often achieve encoding rates around or below 1/10.
  • Kasai’s affine-permutation construction achieved rates near 1/2 and distances above 30 at block lengths around 9000.
  • The paper identifies structural conditions that preserve performance while enabling efficient implementation on reconfigurable neutral-atom arrays.
  • The resulting codes exceed rate 1/2 at block sizes around 1000 qubits and use shallow syndrome-extraction schedules based on orbit-wise shifts and small inter-orbit permutations.

2. HARDWARE CO-DESIGNED CODE CONSTRUCTION

The construction co-designs affine-permutation CSS codes with neutral-atom transport constraints. Commuting transition permutations become orbit-wise shifts and inter-orbit permutations, enabling parallel syndrome extraction while retaining high rate and finite-size distance.

  • Reconfigurable neutral-atom arrays offer programmable non-local connectivity, but crossed-AOD transport supports only restricted parallel movement primitives.
  • Kasai’s CSS construction uses affine-permutation blocks in block-circulant X- and Z-check matrices to obtain rates near 1/2.
  • Syndrome extraction applies transversal gates between ancilla and data blocks, with shared transition permutations allowing three stabilizer rows to be measured in parallel.
  • Arbitrary affine permutations can require O(log P) transport steps, increasing syndrome-extraction time.
  • Choosing a reference affine permutation with large orbits and requiring transition permutations to commute with it reduces movements to cyclic shifts within orbits plus permutations between orbits.
  • The constructed examples include J1152,580,≤12K with P = 96 and J2304,1156,≤14K, alongside larger compatible instances.

3. NOISE SIMULATIONS AND HIERARCHICAL DECODING

The paper evaluates the codes under phenomenological and circuit-level noise using a hierarchical decoder designed for accurate, efficient simulation of extremely low logical error rates. The reported results approach the teraquop regime at 0.1% physical error.

  • The simulations target physical error rates around 0.1% and use direct simulation because the large logical-qubit count steepens logical-error scaling near threshold.
  • The decoder escalates from belief propagation to relay belief propagation and then integer programming only when earlier stages fail to converge.
  • Most shots are handled by the first two stages, yielding highly accurate decoding with runtime only modestly above belief propagation alone.
  • Phenomenological simulations compare J1152,580,≤12K and J2304,1156,≤14K over physical error rates using 32 syndrome rounds.
  • Circuit-level simulations at p = 0.1% neglect idling errors and sequentially extract X- and Z-type syndromes.

4. PARETO FRONTIER OF ULTRA-HIGH-RATE CODES

The paper uses heuristic finite-blocklength estimates to compare encoding rate, block length, and logical error rate. Its APM-based codes lie near the estimated frontier, while a gap remains for codes at a few hundred physical qubits.

  • Finite-blocklength estimates: Finite-blocklength estimates provide practical reference curves for achievable encoding rates at fixed block length, physical error rate, and target logical error probability.The quantum estimates heuristically adapt the hashing-bound procedure because exact depolarizing-channel capacity is unknown.
  • Finite-blocklength estimates: At p = 3%, the finite-blocklength estimate gives encoding rates of about 0.55 at n ∼1000 and 0.1 at n ∼100, below the asymptotic hashing-bound rate of approximately 0.758.These values illustrate the importance of finite-size corrections.
  • Comparison with the frontier: The APM-based construction and Gross code family lie closest to the estimated frontier in their respective block-length regimes.Figure 4 compares codes targeting per-logical-per-round error rates of 10^-9 and 10^-12 under circuit-level noise with p_circ = 0.1%.
  • Comparison with the frontier: A gap appears at a few hundred physical qubits, where rates approaching 1/3 appear achievable but no current construction combines those block lengths with comparable logical performance.The paper identifies this intermediate regime as a promising target for future code design.
  • Comparison with the frontier: Numerical code-capacity results follow the finite-blocklength trend but require depolarizing error rates roughly twice as large to reach a given target logical error rate.The comparison uses belief propagation with an integer-programming fallback under a matched error model.

5. DISCUSSION

The discussion presents hardware-co-designed ultra-high-rate CSS codes with competitive circuit-level performance and identifies open challenges in code construction, decoding, and extending memory results to computation.

  • Main results: The hardware-co-designed CSS codes support efficient implementation on reconfigurable atom arrays and achieve circuit-level logical error rates close to the teraquop regime at p = 0.1%.A heuristic finite-blocklength comparison places the constructions near a practical Pareto frontier.
  • Future code and decoder improvements: Broader affine-permutation searches and combinations with lifted or balanced products may improve the tradeoff among rate, distance, decoding performance, and implementation cost.The intermediate regime of a few hundred physical qubits is highlighted as a promising search target.
  • Future code and decoder improvements: The hierarchical decoder is designed primarily for faster Monte Carlo simulation, although its modest fallback overhead may also support real-time decoding on slower platforms.The discussion emphasizes improving early-stage decoder accuracy and reliable fallback heralding.
  • Architectural scope: The present work focuses on memory performance rather than a full architecture for fault-tolerant quantum computation.Future work includes low-weight logical bases, optimized surgery gadgets, and more parallelized surgery schemes.
  • Architectural scope: The paper suggests that the ultra-high-rate philosophy may extend from quantum memory to logical computation, alongside further progress in code design, logical operations, decoding, and hardware co-design.This is presented as a direction toward practical high-rate fault-tolerant quantum computation.

Appendix A: Details of Code Construction and Finite-Size Search Principle

The appendix describes the Kasai CSS construction and a finite-size search that imposes affine-permutation and implementation constraints while screening candidate codes for distance and logical performance.

  • Construction: The Kasai code is a CSS code defined by X- and Z-stabilizer check matrices built from affine permutation matrices.The displayed checks retain active block rows from larger parent matrices.
  • Construction: Removing stabilizer rows can create low-weight logical operators, but Kasai’s omitted rows avoid this failure through non-commuting affine-permutation blocks.The construction arranges the deleted rows so they do not commute in the required way with retained checks of the opposite basis.
  • Finite-size search: The finite-size search chooses a reference affine permutation with large orbits and constrains neighboring transition permutations to commute with it.For P = 96, the reference permutation has three orbits of size 32.
  • Finite-size search: Commuting transition permutations reduce, in the reference cycle basis, to orbit-wise shifts and small inter-orbit permutations.This structure is intended to match the available implementation patterns.
  • Finite-size search: The search additionally imposes girth ≥6, then filters candidates using distance bounds and code-capacity logical-error simulations.The resulting instances are reported with best-found upper bounds rather than exact distance determinations.

Appendix B: Details of Simulations

The appendix introduces the simulation details used in the main text.

  • The appendix provides the simulation details underlying the main-text results.

B.1. Circuits and noise models

The simulations model repeated quantum-memory syndrome extraction using phenomenological and circuit-level assumptions, including a depth-24 measurement circuit and no idling errors.

  • Simulation protocol: The memory simulation initializes physical qubits in |+⟩ or |0⟩ states, performs 32 rounds of X- and Z-stabilizer measurements, and then measures all qubits.Logical errors are inferred from the final X- or Z-basis measurements.
  • Circuit-level model: Circuit-level simulations independently measure X and Z stabilizers with coloration syndrome extraction, producing CNOT depth 12 per basis and total depth 24.The depth can be reduced by a factor of 2 to 4 using additional methods.
  • Circuit-level model: The circuit-level model assumes no idling errors because of long coherence times in neutral-atom and trapped-ion systems.More realistic modeling of idling and atom-loss effects is left for future work.
  • Phenomenological model: The phenomenological model applies measurement errors to stabilizer outcomes and single-qubit depolarizing errors to data qubits after each measurement round.The simulation uses p_phenom = p_data as a single error-strength parameter.

B.2. Decoders

The appendix specifies a three-tier decoding pipeline and the parameterization of representative APM CSS code instances and relay belief-propagation decoding.

  • Decoder hierarchy: The hierarchical decoder comprises belief propagation, relay belief propagation, and integer-programming maximum-likelihood decoding tiers.The final tier solves an exact most-likely-error problem using Gurobi and single-basis syndromes.
  • T1 (belief propagation): The belief-propagation tier uses quaternary decoding for phenomenological simulations and binary detector-model decoding for circuit-level simulations.Both implementations support memory belief propagation with serial and alternating scheduling.
  • T2 (relay BP): The relay tier builds on the first-tier output, skipping its initial belief-propagation phase in circuit-level decoding.The circuit-level implementation uses the open-sourced relay decoder with parameters listed in Table B1.
  • Code instances: The APM CSS parameter table covers P = 96, 192, and 384 with J = 3 active block rows, L = 12 block columns, and girth ≥6.It also specifies non-commutativity pairs (0, 3) and (1, 2), along with affine map parameters for the F_i and G_i blocks.

Appendix C: Hierarchical Decoder and Real-Time Quantum Error Correction

The hierarchical decoder is designed to sustain real-time syndrome processing by concentrating average work in fast early tiers while reserving expensive decoding for a small tail of difficult cases. Extrapolated accelerator runtimes remain below the neutral-atom syndrome-extraction cycles for both studied codes.

  • Real-time operation requires sustaining the incoming syndrome rate without unbounded backlog, with average decoder reaction time not bottlenecking execution.
  • For a k-tier hierarchy, the fraction of syndrome rounds reaching tier i is determined by the escalation probabilities of preceding tiers.Each tier takes average time t_i and passes unresolved instances onward with probability r_i.
  • The average decoding work per syndrome round is ¯t = Σ_i q_i t_i, which must satisfy ¯t ≲ TQEC to keep up with syndrome extraction.Here q_i is the fraction of rounds reaching tier i, and TQEC is the syndrome-extraction cycle time.
  • The hierarchy is efficient when BP resolves most rounds, relay-BP handles most remaining cases, and only a small tail reaches integer programming.Under this regime, average runtime is dominated by the early stages when late-stage runtime ratios are sufficiently favorable.
  • Extrapolated FPGA timing scales with Tanner-graph size through F, yielding approximately 192 ns and 448 ns per sliding-window iteration for the two codes.For the Kasai instances, F is 8.0 and approximately 18.7; larger graph diameter or memory bandwidth may add overhead.
  • CPU runtimes for T1 and T2 are converted to per-round FPGA estimates using measured iteration counts and a conservative scaling assumption for relay-BP.The T2 estimate assumes relay-BP has a similar per-iteration FPGA cost to BP; T1 BP is estimated at roughly 100–260 ns per syndrome round.
  • The decoder’s integer-programming tier is accurate but slow, motivating approximate-optimal or neural decoders as bounded-latency fallbacks.The T3 CPU runtime is several seconds per round, whereas approximate-optimal alternatives retain near-optimal logical-error performance at lower, more predictable latency.
  • 120 ns and 1.0 µs of total decoding work per round remain below the respective 8.3 ms and 9.9 ms syndrome-extraction cycles.These estimates assume FPGA acceleration for T1 and T2 and GPU acceleration for T3.

E.2. Designing APMs to Simplify Atom Movement

The codes simplify atom movement by choosing affine-permutation structures that commute with a reference permutation and by exploiting large abelian column subgroups. For the two target instances, this reduces column operations to one or two global rigid shifts.

  • Reference-orbit design: A reference affine permutation with large orbits is chosen so commuting transition permutations become orbit-wise shifts plus inter-orbit permutations.This makes hardware-supported movement patterns a code-design input rather than a post hoc compilation constraint.
  • Reference-orbit design: Commutation with the reference permutation maps each orbit onto another while applying a uniform within-orbit shift.The orbit action is the structural basis for compiling transitions into simple movements.
  • Column-group structure: The maximal abelian subgroup of each considered column group has order P/3, while the new code groups are abelian and Kasai’s original group is non-abelian.The subgroup supplies a basis in which column components act as translations; the original P = 768 construction has only a partial subgroup structure.
  • Code instances: For P = 96, relabeling columns by group powers turns every component into a rigid shift, and the relabeling is implemented only through the initial atom-loading order.Subsequent rounds therefore require a single cyclic column shift rather than repeated arbitrary permutations.
  • Code instances: For the P = 192 and P = 384 variants, the relevant groups are cyclic or products such as Z2 × Z32, Z2 × Z64, and Z128, producing commuting translations.The bivariate P = 192 instance uses a pair of rigid shifts on Z2 and Z32.
  • Code instances: All 12 generators for the J1152, 580, ≤12K and J2304, 1156, ≤14K instances lie in the maximal abelian subgroup.At P = 96 this gives one global cyclic shift; at P = 192 it gives two commuting shifts, with corresponding row swaps in the 6 × 32 layout.
  • Scope: Raw affine-map abelianness is sufficient but not necessary: schedule-specific transitions may commute even when the raw group does not.Whether this weaker condition applies depends on the syndrome-extraction schedule.

E.4. Atom Layout and Time Estimates

The atom-layout analysis estimates syndrome-extraction costs under explicit transport, gate, measurement, and parallel-control assumptions. Four AODs enable concurrent permutations and data-block motion, while a chosen APM ordering yields favorable total time for both codes.

  • Assumptions: The execution model uses 12 µm data-atom spacing, 2 µm ancilla offsets, 5500 m/s2 acceleration, straight-line moves, and negligible parallel CZ and Hadamard durations.Measurement is modeled at as little as 500 µs, while movement is treated as the bottleneck.
  • Assumptions: Fresh ancilla qubits replace measured ones so gates continue during measurement, making measurement time irrelevant in the modeled regime.This assumption removes measurement waits from the syndrome-extraction timing estimate.
  • Parallel control: Two crossed-AODs nearly halve time by parallelizing shifts or swaps, while four additionally overlap data-block moves with ancilla permutations.Any two permutations shown in one frame of Figs. E2 and E3 are therefore performed simultaneously.
  • Schedule: Table E2 reports space requirements excluding measurement zones and estimated syndrome-extraction round times for the J1152, 580, ≤12K and J2304, 1156, ≤14K codes.The detailed layouts and rearrangement sequences are provided in Figs. E2 and E3.
  • Schedule: The ordering F0, F5, F2, F4, F1, F3, G3, G1, G4, G2, G5, G0 yields favorable total time for both codes.Other orderings remain valid when all F APMs precede all G APMs and satisfy the stated endpoint-index constraints.

E.5. Movement Compilation for Lifted Product Codes

For lifted product codes, group-ring shifts compile into uniform cyclic movements across lift blocks. CRT layouts then separate these translations into independent row and column AOD operations when the relevant factor orders are coprime.

  • Lifted product structure: The compilation strategy applies directly to lifted product codes over cyclic group rings, including bivariate bicycle codes.Their ring elements act on the lift index as uniform cyclic shifts independent of the base index.
  • Lifted product structure: A single crossed-AOD move requires the same shift across every block sharing an axis; product structure supplies this uniformity and avoids per-row serialization.The boundary-map structure enables parallel implementation across lifted blocks.
  • Movement compilation: Successive CNOT-layer transitions remain single monomials because products of ring monomials lie in the abelian group Zℓ.Each layer and inter-layer transition is therefore one rigid shift applied uniformly to an entire block.
  • Movement compilation: CRT folding onto an m × l grid separates a translation into independent row and column AOD shifts when gcd(m, l) = 1.This separation occurs without a carry correction.
  • Code layouts: Figures E2 and E3 show the atom positions and rearrangement sequences for the J1152, 580, ≤12K and J2304, 1156, ≤14K layouts.The layouts use data-qubit spacing and ancilla placement conventions described for the two code instances.
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