Source-linked AI summary
FPGA-Accelerated Real-Time Diagnostics at DIII-D Using the SLAC Neural Network Library for ML Inference
Abhilasha Dave, Semin Joung, SangKyeun Kim, Ramon Reed, Keith Erickson, Jalal Butt, Azarakhsh Jalalvand, Mudit Mishra, James Russell, Larry Ruckman, Ryan Herbst, Egemen Kolemen, David Smith, Ryan Coffee
TL;DR
Real-time plasma control needs fast interpretation of high-bandwidth diagnostic data, while conventional CPU/GPU inference may exceed sub-millisecond timing constraints. The paper deploys a reconfigurable SNL neural network on an FPGA integrated with DIII-D’s PCS. The system reports just over 5 microseconds of inference latency and supports confinement classification and early ELM detection.
Problem
Hundreds of diagnostic channels create computation and latency demands, while CPU/GPU inference can exceed the sub-millisecond timing constraints of real-time control.
Source: §4 · p. 3Method
The authors integrate an SNL-deployed neural network on an FPGA with DIII-D’s real-time diagnostic and PCS pipeline, using BES data for plasma classification and ELM forecasting.
Source: §2 · p. 2Results
Just over 5 microseconds of inference latency was achieved while classifying confinement regimes and detecting breakthrough ELM events through the SHIELD framework and PCS.
Source: §6 · p. 7Takeaways & Limitations
The authors present hardware-accelerated, reconfigurable ML as a foundation for adaptive, data-driven control strategies in next-generation fusion devices.
Source: §6 · p. 7The current CPU-mediated ingestion path fixes inference to 18-frame batches, limiting finer-grained continuous updates; the authors propose direct digitizer-to-FPGA integration.
Source: §5 · p. 7
Abstract
from arXiv · showhide
In this work, we demonstrate the deployment of a hardware-accelerated machine learning (ML) inference system integrated into a real-time processing at the DIII-D tokamak fusion reactor. The team has successfully deployed an AMD/Xilinx KCU1500 field-programmable gate array (FPGA) into the realtime Plasma Control System (PCS) nodes that receives the live Beam Emission Spectroscopy (BES) signal used for Edge Localized Mode (ELM) forecasting. The FPGA hosts a dense neural network using the SLAC Neural Network Library (SNL) that has been trained to infer the likelihood of disruptive ELM conditions. This likelihood then feeds a separate plasma controller that uses Resonant Magnetic Perturbation coils to suppress the predicted disruptive condition. The SNL allows for on-the-fly updates of the neural network weights and biases without requiring full hardware resynthesis for the FPGA. Judicious design of the neural-network architecture can further allow for the hot-swapping of multiple classification tasks to be executed on the single FPGA, significantly enhancing the real-time adaptability of the system for context-aware control strategies that respond in real-time to evolving reactor conditions. These adaptive weights naturally support continuous model refinement and seamless task switching during live experimental operation. This use case is chosen as a high rate signal processing example that can serve as a template for general ML-based reactor diagnostic processing for active reactor control systems. We see this as an essential development for achieving reactor relevant operation in future continuous operation fusion devices.
2 Introduction
The paper presents an FPGA-accelerated neural network for real-time plasma classification and ELM prediction on DIII-D. It motivates this application by the need for adaptable, low-latency control and highlights runtime parameter updates as a route to switching inference tasks.
2 Introduction
- The authors present the system as a template for ML-based control frameworks in future reactor-relevant fusion environments where latency and adaptability are critical.The demonstration uses magnetic-confinement fusion, with tokamaks described as technologically mature and potentially near-term commercializable.Source: §2 · p. 1
- Real-time ELM prediction and mitigation matter because ELMs threaten plasma stability and reactor-component integrity in high-confinement regimes.The authors identify real-time feedback control as essential for regulating plasma stability, sustaining confinement, and mitigating disruptions.Source: §2 · p. 2
- The system targets BES signals for classifying plasma states and forecasting breakthrough ELMs, using a pre-trained neural network deployed on an FPGA at the RTSTAB acquisition node.BES provides high-resolution, two-dimensional electron-density fluctuation measurements at 1 MSps.Source: §2 · p. 2
- A multi-layer perceptron deployed through SNL runs on the Xilinx FPGA in a DIII-D PCS node and produces time-sequenced BES features for regime classification and early ELM detection.The PCS integration is intended to meet real-time plasma-control latency constraints.Source: §2 · p. 2
- SNL can reload task-specific weights and biases at runtime without FPGA resynthesis, allowing multiple inference tasks on one firmware-based model.The paper names ELM forecasting and confinement-regime recognition as example tasks.Source: §2 · p. 2
3 System Overview
The DIII-D monitoring system routes high-bandwidth diagnostic streams through a modular real-time infrastructure to local acceleration hardware. In this implementation, an FPGA processes the SNL inference and sends outputs toward the PCS and actuator-control systems.
3 System Overview
- A modular C++ infrastructure supports low-latency diagnostic acquisition, buffering, and inter-process communication, routing streams to local acceleration hardware.The paper defers detailed architecture and plasma-control implementation to a forthcoming publication.Source: §3 · p. 2
- ECE, CO2, and BES signals are digitized at 1 MSps across 160 channels, with PCIe acquisition and synchronized ring buffers; remote digitizers can appear local with sub-microsecond latency over distances up to 100 meters.The digitizers use 18-bit differential signals.Source: §3 · p. 3
- The AMD/Xilinx KCU1500 FPGA hosts SNL inference, and its outputs travel to the PCS host over InfiniBand for low-latency integration with actuator controls.The authors describe deterministic timing, computational flexibility, and scalable bandwidth as system requirements.Source: §3 · p. 3
4 Application of the SLAC Neural Network Library for RealTime Plasma Monitoring in the DIII-D Tokamak
The application adapts SNL for low-latency inference in DIII-D’s real-time diagnostic and control pipeline. Its FPGA design combines diagnostic preprocessing, a configurable neural network, and batched postprocessing, while runtime parameter reloading supports task changes without resynthesis.
4 Application of the SLAC Neural Network Library for RealTime Plasma Monitoring in the DIII-D Tokamak
- SNL addresses the latency and bandwidth demands of real-time diagnostic processing, where hundreds of channels and CPU/GPU inference can challenge sub-millisecond control timing.The framework compiles remotely trained models through an AMD Vitis toolchain using HLS and C++ templates for FPGA inference.Source: §4 · pp. 3–4
- Runtime weight and bias reloading, together with input and output masking, can reconfigure a fixed network without resynthesis or place-and-route cycles.The paper describes masking unused ECE and CO2 inputs while allowing future accommodation of additional diagnostics or aging sensors.Source: §4 · p. 4
- The DIII-D implementation processes time-series BES signals for confinement classification and breakthrough-ELM forecasting, then routes inferred ELM likelihood to a separate PCS controller for RMP-coil adjustment.SNL is positioned between the diagnostic front end and the PCS.Source: §4 · p. 4
4.1 Integration of Pre- and Post-Processing Units with SNL-Based Inference
- The FPGA preprocessing selects 16 BES channels from the digitizer stream, and each inference call uses 18 events with 48 time slices per event before postprocessing sends results to the PCS.The model produces one four-class result per event in this described pipeline.Source: §4.1 · pp. 4–5
4.2 Neural Network Structure
- The shared fully connected feedforward network uses a lightweight architecture, while runtime output-layer reconfiguration switches between binary ELM detection and four-class confinement classification.The input comprises 768 features from 48 consecutive time slices across 16 BES channels; the hidden layers each contain 50 ReLU neurons.Source: §4.2 · pp. 5–6
4.3 FPGA Implementation and Resource Utilization
- The KCU1500 implementation was synthesized with Vitis HLS 2023.1, and reported utilization leaves headroom for more complex models or multiple inference tasks on one FPGA.The design operated within timing and routing constraints at a 6 ns target clock, and weight/bias reloads were exercised during a closed-loop ELM-suppression experiment.Source: §4.3 · p. 6
5 Future Work and System Integration Considerations
The current CPU-mediated ingestion pipeline delivers diagnostic data in fixed windows, constraining inference to a segmented format and limiting finer-grained updates. Future integration would send digitizer signals directly to the FPGA and controller, supporting continuous streaming and potentially adaptive or event-triggered control.
5 Future Work and System Integration Considerations
- The CPU middleware delivers fixed-window data, so the current pipeline operates in a segmented format rather than the FPGA architecture’s continuous-streaming paradigm.The proposed alternative is to route signals directly to the FPGA for inference and then to the controller.Source: §5 · p. 7
- The current software-mediated design processes 18 discrete input frames per inference cycle, limiting finer-grained, continuous, or faster-than-real-time updates.The FPGA is fully pipelined and optimized for frame-based input.Source: §5 · p. 7
- Future integration would bypass the CPU layer with direct digitizer-to-FPGA interfaces, potentially enabling continuous streaming, lower control-loop latency, and event-triggered strategies.The authors cite LCLSII as an example of direct digitizer-to-FPGA interfaces.Source: §5 · p. 7
6 Conclusion
The work integrates a low-latency FPGA neural network into DIII-D’s real-time monitoring and control infrastructure for confinement-regime classification and early ELM detection. The system meets its latency budget despite CPU middleware constraints, and the authors present it as a foundation for adaptive control in future fusion devices.
6 Conclusion
- Just over 5 microseconds of inference latency—10% of the ingestion time window—was achieved by the FPGA-deployed model in DIII-D’s real-time infrastructure.The model ingested BES data for confinement-regime classification and early detection of breakthrough ELM events, interfacing with SHIELD and PCS.Source: §6 · p. 7
- Custom FPGA pre- and post-processing modules interface digitized signals with SHIELD-compliant operation, while CPU middleware constrains the current data-acquisition pipeline.The architecture maintains strict latency budgets despite those constraints.Source: §6 · p. 7
- The authors identify hardware-accelerated, reconfigurable ML as a potential foundation for adaptive, data-driven control in next-generation fusion devices.They frame real-time diagnostic interpretation and rapid response as essential to sustained, disruption-free operation.Source: §6 · p. 7
8 Disclaimer
The disclaimer limits government responsibility for the report and disclaims endorsement of commercial products or authors’ views.
8 Disclaimer
- The report disclaims express and implied warranties and government responsibility for the accuracy, completeness, or usefulness of its contents.It also disclaims liability for disclosed information, apparatus, products, or processes.Source: §8 · p. 8
- The report does not represent that use of its disclosed information, apparatus, products, or processes would avoid infringement of privately owned rights.Source: §8 · p. 8
- References to commercial products do not imply government endorsement, and the authors’ views need not reflect government views.Source: §8 · p. 8
9 Data Availability
The paper’s supporting DIII-D data are available through the DIII-D National Fusion Facility, subject to its user protocols.
9 Data Availability
- Relevant data supporting the study’s findings are available from the DIII-D National Fusion Facility.Source: §9 · p. 8
- Access to DIII-D data requires following the user protocols described on the DIII-D website.Source: §9 · p. 8
- Questions about data availability can be directed to the paper’s corresponding author.Source: §9 · p. 8