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Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid

Boren Gu, Tamas Noszko, Vincent Steffan, Jens Niklas Eberhardt, Joschka Roffe, Jens Eisert, Stergios Koutsioumpas

arXiv:2606.19482v1quant-ph

TL;DR

High-performance qLDPC codes offer lower overhead but commonly require connectivity difficult to realize on superconducting hardware. This work introduces planar directional tile codes whose iSWAP walks dynamically implement stabiliser measurement using nearest-neighbour interactions, retaining finite-size advantages over rotated surface-code memories. At around 30 circuit qubits per logical qubit, the best layouts reduce the per-logical per-round logical error rate by up to three orders of magnitude.

  • Problem

    Finite-size qLDPC overhead advantages must be reconciled with strictly planar nearest-neighbour implementation, because high-performance constructions typically require non-local check-data interactions.

  • Method

    Directional tile codes use directional words and nearest-neighbour iSWAP-based walks to define stabiliser supports and dynamically implement their measurements on square-grid layouts.

  • Results

    At p=0.001 and around 30 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by up to three orders of magnitude relative to rotated surface-code memories.

  • Takeaways & Limitations

    Finite-size qLDPC advantages can survive compilation into strictly planar nearest-neighbour circuits without long-range couplers, qubit shuttling, or non-planar connectivity.

Abstract

from arXiv · show

High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a square grid of qubits. The key idea is to generate check-data connectivity dynamically: nearest-neighbour iSWAP walks both define the stabiliser supports and implement their measurement, avoiding the need for a long-range hardware graph. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the role of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 30 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by up to a factor of 1000 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.

I. INTRODUCTION

The paper addresses whether qLDPC memories can retain finite-size overhead advantages while using strictly planar nearest-neighbour hardware. Directional tile codes answer affirmatively through dynamically generated check-data connectivity and show strong finite-size and circuit-level results.

  • Motivation: Two-dimensional locality imposes asymptotic restrictions on simultaneously achieving high rate and large distance, leaving finite-size hardware-compatible advantages as the key open question.The bound is expressed as k d^2 = O(n).
  • Approach: Directional tile codes implement planar qLDPC memories on square grids using only nearest-neighbour iSWAP gates.iSWAP exchange dynamics route quantum information while generating check-data interactions.
  • Approach: Each stabiliser is measured by a nearest-neighbour walk rather than through a static long-range coupling graph.The walk dynamically generates the required check-data connectivity during syndrome extraction.
  • Leakage handling: Exchanging data and check qubits after each syndrome-extraction round naturally resets both roles every other round, helping remove leakage from higher excited states.The passage describes this as especially relevant to leakage noise in superconducting hardware.
  • Results: The [[323, 14, 15]] instance has a code-efficiency ratio nearly an order of magnitude larger than that of a rotated surface-code patch at the same distance.Code efficiency is evaluated using k d^2/n.
  • Results: At p=0.001 and around 30 circuit qubits per logical qubit, the best directional tile-code layouts reduce per-logical per-round logical error rate by up to three orders of magnitude versus rotated surface-code memories.The comparison uses circuit-level simulations with the same encoded memory size.

II. PLANAR QLDPC MEMORIES FROM DIRECTIONAL WORDS

Directional words jointly specify stabiliser supports and nearest-neighbour measurement schedules, enabling open-boundary planar qLDPC memories. The resulting bounded-weight circuits retain constant-depth extraction and can outperform rotated surface-code layouts after routing overhead is included.

  • Directional-word construction: A directional word is an ordered lattice-step string that defines stabiliser support and the local schedule for measuring it.The same word places paired X- and Z-type checks on primal and dual lattices.
  • Planar construction: The construction applies directional prescriptions directly to finite planar patches, producing open-boundary layouts rather than periodic codes.Routing qubits are inserted only where needed to preserve nearest-neighbour ordered walks.
  • Efficiency metric: The circuit-efficiency ratio benchmarks implemented layouts using all physical qubits required by syndrome extraction, including routing qubits.It compares against k rotated surface-code patches.
  • Circuit depth: A syndrome-extraction round has depth w+2 for a directional word of weight w, independent of overall code size.The depth includes check-qubit initialisation and measurement.
  • Implemented performance: After routing overhead is included, implemented directional tile-code memories can outperform rotated surface-code footprint curves under a uniform circuit-level noise model.The construction generates check-data interactions dynamically in spacetime through iSWAP-based walks.

III. NEAREST-NEIGHBOUR SYNDROME EXTRACTION

Directional words drive nearest-neighbour syndrome extraction by moving check qubits across a square grid while CXSWAP operations accumulate stabiliser parities. The same iSWAP-based gate family supports interactions and routing, with alternating rounds restoring the layout.

  • Performance accounting: Each listed code supports extraction depth w, or w+2 including check-qubit preparation and measurement.The circuit-level comparison includes data, check, and routing qubits; simulations in Table II cover only codes with n≤300.
  • Circuit construction: CXSWAP gates simultaneously accumulate stabiliser eigenvalues and advance check, data, and routing-qubit positions.The control orientation differs for X- and Z-type checks after basis changes.
  • Circuit construction: Directional words specify ordered nearest-neighbour walks for check qubits across data and routing qubits.Each directional layer applies local operations along one lattice direction.
  • Round structure: Alternating a directional word with its inverse restores the physical layout without long-range operations.This makes consecutive extraction rounds compatible with the same planar hardware arrangement.
  • Hardware implementation: Nearest-neighbour iSWAP-based operations implement both parity interactions and routing moves on the square-grid layout.Routing qubits bridge gaps so every step remains nearest-neighbour.
  • Leakage considerations: The circuits exchange data and check roles between rounds, but leakage performance is not modelled in the reported results.Routing qubits may also be reset or measured for leakage mitigation or flagging strategies.

IV. DIRECTIONAL TILE CODES

Directional tile codes build planar CSS memories from paired connected strings on primal and dual lattices, with additional conditions ensuring commutation and deterministic extraction. Their layouts use boundary routing qubits and exhibit distinct finite-distance circuit-scaling regimes.

  • Directional tiles: A directional tile pair uses one ordered connected string and the same string on the dual lattice to define X- and Z-type checks.The directional word labels the ordered lattice steps and the resulting stabiliser supports.
  • Tile conditions: The mutual condition ensures static X- and Z-stabiliser commutation, while an even-multiplicity displacement condition ensures deterministic extraction.The latter applies to every displacement vector with odd vertical displacement.
  • Planar construction: Tessellating directional tiles on a finite rectangular grid and pruning unnecessary boundaries produces the data and check-qubit layout.The construction uses open boundaries rather than periodic boundary conditions.
  • Circuit scaling: For weights w=7 and w=9, circuit-qubit counts follow exact quadratic fits over the shown distances.Higher-weight words w=11 and w=13 are approximately linear over the finite-distance regime relevant to overhead comparisons.
  • Hardware embedding: Boundary gaps are filled with routing qubits so the ordered syndrome-extraction walk remains nearest-neighbour.Terminal routing sites can be removed when they are not load-bearing during a round.

V. ROUTING OVERHEAD AND OPTIMISATION

The routing overhead is boundary dominated, scaling linearly with code dimensions and reducing to O(d) for balanced distances, while optimisation removes non-load-bearing routing sites and routing measurements can improve decoding.

  • Scaling: Routing overhead is boundary dominated and scales linearly with the relevant code distances.Routing qubits are introduced near the planar boundary, whose size grows with the code’s linear dimensions.
  • Scaling: In balanced families, routing overhead reduces to n_r = O(d).For comparable d_X and d_Z, both standard and optimised overheads grow approximately linearly with the common distance.
  • Optimisation: Removing non-load-bearing terminal relay sites reduces routing overhead by shifting corresponding data or check positions.The optimisation targets routing qubits that are not needed between two data-check interactions.
  • Architectural integration: Routing overhead may be partly shared with auxiliary padding regions in multi-patch architectures.Suitable lattice-surgery layouts can use boundary routing qubits as inter-patch workspace rather than treating them as entirely separate overhead.
  • Fault diagnosis: Routing-qubit measurements provide flag information about faults along the ordered routing path.In circuit-level simulations, supplying this information to the decoder improves performance at relatively high physical error rates.

VI. SUMMARY AND OUTLOOK

Directional tile codes use the same directional word to define stabilisers and nearest-neighbour syndrome-extraction walks, achieving code-size-independent measurement depth. Their finite-size advantage persists after planar compilation, while simulations and broader hardware models remain open directions.

  • Construction: Directional tile codes use one directional word to specify both CSS stabilisers and ordered nearest-neighbour measurement walks.iSWAP exchange dynamically generates check-data connectivity in spacetime instead of requiring a static long-range coupling graph.
  • Construction: A syndrome-extraction round has depth w + 2, independent of code size.The depth includes check-qubit preparation and measurement for a directional word of weight w.
  • Results: Up to three orders of magnitude lower per-logical per-round logical error rates are achieved than in rotated surface-code memories at about 30 circuit qubits per logical qubit.This comparison is made after compiling syndrome extraction into strictly planar nearest-neighbour circuits.
  • Limitations and outlook: The present evidence is finite-size, restricted to particular directional-word families, and based on simplified noise models.The authors identify systematic searches and biased, coherent, and hardware-calibrated noise models as needed next steps.
  • Limitations and outlook: Leakage has not been explicitly modelled, and the full circuit-level costs of logical operations and architecture-level compilation remain unassessed.Proposed routes include leakage removal, lattice surgery, code-automorphism operations, and larger-layout integration.

Appendix A: Toric directional codes as bivariate-bicycle codes

Toric directional codes form a translationally invariant CSS subfamily of bivariate-bicycle codes, with stabiliser supports encoded by paired bivariate polynomials and reciprocal dual strings. Their Tanner graphs are (w, w)-regular.

  • Algebraic construction: Toric directional codes are translationally invariant CSS codes and a distinguished subfamily of bivariate-bicycle codes.They are obtained by tessellating a generalised torus with directional tiles.
  • Algebraic construction: Bivariate polynomials f(x, y) and g(x, y) encode X-stabiliser support on horizontal and vertical edges of a periodic grid.The corresponding Z-stabiliser uses reciprocal polynomials on the dual string.
  • Algebraic construction: The CSS parity-check matrices are represented through cyclic-shift matrices for the quotient-ring variables.The binary representation maps x and y to tensor products involving cyclic-shift permutation matrices and identities.
  • Regularity: Every stabiliser generator and every data qubit has total degree w, making the Tanner graph (w, w)-regular.Each check has weight w, and each data qubit participates in exactly w checks.

Appendix B: Directional tile codes for biased noise

Directional tile codes can realise strongly unbalanced X- and Z-distances by changing the rectangular base-grid aspect ratio, supporting biased-noise applications. A brute-force search identifies high-efficiency instances within the stated search space.

  • Biased-noise layouts: Varying the rectangular base-grid aspect ratio changes the balance between X- and Z-type distances for a fixed directional word.The resulting strongly unbalanced codes may suit biased-noise architectures.
  • Search and comparison: The search covers directional words and base grids with M + N ≤ 25, reporting instances with the largest unbalanced code-efficiency ratio k d_X d_Z / n.The table compares these instances with rectangular rotated surface-code patches.

Appendix C: Routing overhead of directional tile codes

Directional tile-code routing overhead is confined to the layout boundary, so it grows with distance rather than patch area. Boundary optimisations substantially reduce this overhead while preserving the measured stabilisers and circuit behaviour.

  • Routing-overhead scaling: Routing qubits are needed only near the planar layout boundary, making their overhead scale with linear patch size rather than area.For fixed directional words and bounded aspect ratio, this corresponds to boundary-to-boundary distance scaling.
  • Routing-overhead scaling: Both standard and optimised routing overheads grow approximately linearly with uniform distance d, while optimisation provides substantial constant-factor savings.This behaviour is shown for d = d_X = d_Z across directional-word families.
  • Boundary optimisation: Route window shortening removes inactive routing prefixes and suffixes by shifting check starts, provided no collision or data-check overlap is introduced.The procedure tests whether the shortened layout still supports the required syndrome-extraction schedule.
  • Boundary optimisation: Trace pruning greedily deletes edge routing qubits and shifts remaining qubits, accepting candidates only when stabiliser supports, detectors, logical observables, and determinism remain unchanged.The method uses two forward-and-backward syndrome-extraction rounds to validate each proposed removal.
  • Representative instance: The [[323, 14, 15]] code’s routing sites decrease from 346 to 165, removing 181 sites and reducing the unoptimised layout by approximately 52%.Route-window shortening reduces 346 to 235 sites before trace pruning removes additional sites.

Appendix D: Logical gates from automorphisms and derived automorphisms

Directional tile codes support logical operations through code automorphisms, including boundary deformations and geometric symmetries. These transformations induce logical Clifford actions while preserving the stabiliser structure.

  • Derived automorphisms: Derived automorphisms temporarily enlarge a tile-code boundary, inducing non-trivial Clifford actions that decompose into products of logical CNOT gates.The construction is described as compatible with a low-overhead fault-tolerant implementation.
  • Geometric symmetries: Palindromic directional words induce reflections of the physical layout that preserve the stabiliser group and define code automorphisms.The reflected directional word gives the same local stabiliser constraints.
  • Geometric symmetries: Reflection automorphisms need not be implemented by nearest-neighbour SWAP circuits because qubits can be re-indexed while updating stabilisers, decoder information, and the Pauli frame.Their induced logical Clifford action is evaluated in the canonical logical Pauli basis.
  • Automorphism search: Automorphism searches identify multiple generators and large symmetry groups, suggesting additional algebraic structure in the studied code families.The framework represents stabiliser codes as binary linear codes and determines induced logical actions under allowed Clifford constraints.
  • Implications: The reported automorphism ingredients may support fault-tolerant Clifford computation or symmetry-assisted decoding.Examples of automorphism-group orders are listed for the N2ESEN2 family with stabiliser weight w = 7.

Appendix E: Circuit-level memory simulations with only nearest-neighbour operations

The circuit-level evaluation uses four-round nearest-neighbour memory simulations under a uniform depolarising noise model. Circuits are compiled with CXSWAP gates and decoded using VibeLSD.

  • Simulation setup: Circuit-level memory simulations use four syndrome-extraction rounds for every code instance and fix the physical noise parameter at p = 0.001.The circuits are compiled using CXSWAP gates under the uniform depolarising model specified in Table VII.
  • Simulation setup: Simulations run in Stim with up to 10 million shots, terminating early after 30 observed logical errors.Decoding uses VibeLSD with an ensemble of 200, LSD order 0, and 15 min-sum iterations per round.
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