PaperlayerView exact revision on arXiv

Source-linked AI summary

Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices

Shyamal Y. Dharia, Stephen D. Smith, Camilo E. Valderrama

arXiv:2607.18149v1cs.LGcs.AI

TL;DR

Edge EEG classification is constrained by conventional neural networks’ computational demands, so this paper evaluates Differentiable Logic Gate Networks against matched MLP and BNN baselines across four EEG benchmarks. Diff-Logic outperformed MLPs on dementia detection, matched emotion-recognition accuracy at scale, and delivered 2.91× faster, 14× smaller inference models.

  • Problem

    Real-world EEG processing with Diff-Logic remains insufficiently evaluated under edge-device constraints, despite the deployment barriers posed by conventional neural networks.

  • Method

    The study performs iso-parameter comparisons of Diff-Logic, MLP, and BNN models across four EEG benchmarks spanning dementia detection and emotion recognition.

  • Results

    Diff-Logic achieved up to 80.2% Macro F1 on dementia detection, while compiled circuits were 2.91× faster and 14× smaller than equivalent floating-point models.

  • Takeaways & Limitations

    Diff-Logic offers competitive EEG classification with favorable latency, memory, and scaling characteristics for resource-constrained edge deployment.

  • Takeaways & Limitations

    The evaluation relies on pre-extracted tabular EEG features, while standard Diff-Logic does not inherently support temporal or spatial convolutions for raw signals.

Abstract

from arXiv · show

Real-time EEG classification on edge devices is bottlenecked by the floating-point arithmetic of conventional neural networks. We investigated Differentiable Logic Gate Networks (Diff-Logic) as a hardware-native alternative that compiles models into pure Boolean circuits executable via bitwise CPU operations. Through rigorous iso-parameter experiments across four EEG datasets spanning two classification tasks, binary dementia detection and 3-class emotion recognition, we compared Diff-Logic against matched-capacity Multi-Layer Perceptron (MLP) and Binarized Neural Network (BNN) baselines at four complexity tiers (50k-500k parameters). On dementia screening, Diff-Logic achieved 80.2% Macro F1, outperforming the MLP baseline by 6.8%. On emotion recognition, the MLP retained a moderate performance advantage but incurred a 2.3$\times$ higher latency and 14$\times$ larger model size when deployed on a power-constrained (7W) Nvidia Jetson Orin Nano CPU (Single-core). Critically, Diff-Logic inference time remained nearly constant across a 10$\times$ increase in model scale, achieving a peak speedup of 2.9$\times$ over MLPs at the largest complexity tier. Our results establish logic-based neural architectures as a practical paradigm for resource-constrained brain-computer interfaces, achieving competitive or superior performance while natively satisfying the latency and memory constraints of portable edge deployment. Code is available on GitHub: https://github.com/Shyamal-Dharia/eeg-difflogic

1. Introduction

The introduction frames conventional deep-learning inference as a deployment barrier for real-time EEG and BCI systems, then motivates Diff-Logic as a hardware-native alternative. It presents a rigorous EEG evaluation targeting accuracy, latency, and iso-parameter comparisons across Diff-Logic, MLP, and BNN models.

  • Deployment challenge: High-parameter neural architectures impose computational, power, and thermal barriers for portable BCI and real-time EEG deployment.The introduction attributes these barriers to the computational overhead of standard deep-learning models.
  • Hardware-native motivation: Microsecond-scale inference requires replacing traditional multiply-accumulate operations with hardware-native formulations such as Differentiable Logic Gate Networks.Diff-Logic relaxes discrete Boolean operations and targets efficient execution on edge-processor arithmetic logic units.
  • Research gap: Diff-Logic’s translation from theoretical efficiency to complex, non-stationary EEG processing remains an open practical question.The paper specifically identifies real-world EEG processing under edge constraints as unexplored.
  • Study scope: The paper presents a rigorous application of Diff-Logic to real-time EEG decoding and examines bitwise learning on high-dimensional, non-stationary brain signals.The evaluation compares Diff-Logic with traditionally floating-point-intensive models for EEG classification.
  • Contributions: The study evaluates Diff-Logic against MLPs and BNNs across four EEG benchmarks and 50k–500k parameters, reporting up to a 2.91× speedup over Float32 MLPs.Its stated contributions include soft probabilistic training followed by compiled Boolean inference and accuracy comparisons for emotion recognition and dementia detection.

2. Related Works

EEG decoding has progressed from deep feature-learning architectures toward compact models for real-time deployment, while hardware-efficient approaches have explored binarization and differentiable logic circuits. Diff-Logic differs from BNNs by learning sparse Boolean topologies that harden into executable logic gates.

  • EEG decoding architectures: EEG decoding shifted from traditional feature engineering to deep representation learning, but high-parameter architectures challenged real-time deployment.Deep4Net used deep convolutional networks to capture spatiotemporal hierarchies, motivating compact architectures such as EEGNet.
  • Hardware-efficient neural networks: BNNs constrain weights and activations to {−1, +1} and replace multiplications with XNOR-popcount operations.Despite this hardware-oriented arithmetic, BNNs retain dense connectivity and require accumulation steps that limit embedded BCI throughput.
  • Differentiable logic networks: Diff-Logic learns network topology rather than merely quantizing a fixed topology, using differentiable AND, OR, and XOR gates during training.After convergence, each gate hardens to a single Boolean function, producing sparse logic circuits that require no accumulation.

3. Methods

The study evaluated Diff-Logic against MLP and BNN baselines across four EEG datasets covering dementia detection and 3-class emotion recognition. Diff-Logic quantized normalized EEG features into thermometer-coded binary inputs and learned sparse Boolean circuits through differentiable soft logic gates.

  • Datasets: Four EEG datasets covered two applications: dementia detection and 3-class emotion recognition, involving 119 unique subjects.The cohort included 88 clinical-dataset subjects and 31 SEED subjects.
  • Datasets: Dementia data used 19-channel resting-state EEG, 500 Hz sampling, and 95-dimensional PSD features from 10-second windows.The 95 dimensions came from five frequency bands across 19 channels.
  • Datasets: Emotion data used 62 channels at 200 Hz, 4-second windows, and 310-dimensional differential-entropy features across three classes.Evaluation used trial-level 10-fold cross-validation.
  • Model comparison: Three architectures were compared: Diff-Logic, an MLP with continuous normalized inputs, and a BNN with binarized linear layers, batch normalization, and sign activations.MLPs used 2–3 ReLU hidden layers with dropout p = 0.3, while BNNs retained latent full-precision weights for updates.
  • Diff-Logic architecture: 16 possible Boolean functions were represented by each soft logic gate through a learnable probability distribution, enabling gradient-based training before hardening.After convergence, each neuron selected its highest-probability function, producing a sparse Boolean circuit executed with bitwise operators and no floating-point arithmetic.

4. Experimental Setup

The experiments used iso-parameter comparisons across Diff-Logic, MLP, and BNN architectures, with task-specific input representations and standardized training procedures. Edge feasibility was evaluated on a 7W Jetson Orin Nano under single-threaded CPU execution, with Diff-Logic compiled on-device.

  • Model and input design: Iso-parameter comparisons constrained Diff-Logic, MLP, and BNN to approximately equal trainable parameter counts at each complexity tier.This design attributes performance differences to representational efficiency rather than model capacity.
  • Model and input design: MLP and BNN used min–max normalized continuous features, whereas Diff-Logic used thermometer-encoded binary inputs.Feature counts were n=95 and n=310 for MLP/BNN, versus n=1,425 and n=4,650 for Diff-Logic, respectively.
  • Training procedure: All models were trained in PyTorch for 100 epochs with batch size 128 using Adam and inverse-frequency class weights in cross-entropy loss.Diff-Logic used η = 0.01 to update gate probability distributions effectively.
  • Edge deployment benchmark: 7W Jetson Orin Nano benchmarking used single-threaded CPU execution to simulate worst-case low-power deployment conditions.The platform had 8 GB RAM, an ARM Cortex-A78AE CPU, and an Ampere-architecture GPU.
  • Edge deployment benchmark: Diff-Logic models were compiled directly on the Jetson, and latency measurements used untrained instances because latency depends only on gate count and connectivity.This avoided compiling all 5×10 = 50 trained checkpoints per tier and isolated raw computational cost from Boolean-function assignments.

5. Experimental Results

Diff-Logic outperformed matched MLP and BNN baselines on dementia classification, while matching near full-precision MLP performance on SEED at sufficient capacity. Its inference latency remained effectively constant as model size increased, yielding a favorable performance–efficiency trade-off.

  • Dementia classification: 80.2% F1-score was achieved by Diff-Logic on dementia classification, outperforming MLP (Float32) and BNN (Binary) baselines across model scales.On CN vs. AD, Diff-Logic achieved 78.9–80.2% F1-score across scales and improved nearly 10 percentage points over MLP at 200k parameters.
  • Optimization behaviour: Gradient approximation methods struggled to converge on high-dimensional EEG data, whereas Diff-Logic learned connectivity and logic directly for quantized inference.The passage characterizes direct logic learning as a more robust alternative to standard binary neural-network optimization.
  • Emotion recognition: 61.0 vs. 61.3 at 500k parameters showed Diff-Logic nearly matched the SEED Float32 MLP, despite the MLP’s moderate lead at lower capacities.The reported SEED performance range was approximately 62 for MLP versus 55–61 for Diff-Logic before the gap vanished at 500k parameters.
  • Scaling behaviour: ∼0.19–0.22ms latency remained effectively constant for Diff-Logic as model size grew by an order of magnitude, unlike the linearly scaling MLP and BNN baselines.The flat scaling curve was attributed to architectural properties including structural condensation and direct logic connectivity.
  • Performance–efficiency trade-off: Diff-Logic dominated the dementia performance–efficiency Pareto frontier by combining the highest F1-score with the lowest latency at scale.Neither baseline matched this simultaneous performance and latency combination.

6. Discussion

Diff-Logic matched or exceeded deep-learning performance on EEG tasks while using fewer resources, with particular advantages in dementia classification and inference scaling. Its current evaluation is limited by tabular features and expanded thermometer encoding, motivating convolutional, recurrent, FPGA, and ASIC extensions.

  • 9.4 percentage points: Diff-Logic outperformed the MLP on dementia tasks at Tier 3 with identical parameter budgets.The discussion attributes this advantage to Diff-Logic’s alignment with threshold-based rules in clinical EEG.
  • 74.8% to 72.0%: MLP accuracy on CN vs. AD dropped when scaling from 50k to 500k parameters.The discussion interprets this decline as overfitting and emphasizes logic-based models’ practical value for smaller clinical cohorts.
  • 0.22 ms and 140 KB: Diff-Logic achieved this latency and storage footprint at the 500k tier.The discussion states that this footprint fits within the L1/L2 cache hierarchy of most modern microcontrollers.
  • The evaluation relied on pre-extracted tabular EEG features, while thermometer encoding expanded input dimensionality by 15×.The standard architecture does not inherently support temporal or spatial convolutions, limiting immediate applicability to raw time-series or image-based modalities.
  • Convolutional and recurrent gate extensions, along with direct FPGA or ASIC implementations, are proposed to address feature-extraction and ultra-low-power deployment gaps.These implementations could map compiled Boolean circuits directly to silicon primitives without software emulation.

7. Conclusion

The conclusion reports an iso-parameter comparison showing that Diff-Logic outperformed MLPs on clinical dementia detection and matched emotion-recognition accuracy at scale. Its Boolean-circuit implementation also delivered substantial speed and size advantages.

  • Conclusion: 80.2% Macro F1 was achieved by Diff-Logic on clinical dementia detection, outperforming the MLP by 9.4 percentage points.The comparison used iso-parameter Diff-Logic, MLP, and BNN baselines.
  • Conclusion: Comparable accuracy was achieved by Diff-Logic on the SEED emotion recognition task at scale.This result was reported within the iso-parameter comparison against standard continuous MLP and binary BNN baselines.

Appendix A. Dataset Summary

Appendix A summarizes the EEG datasets used in the study, specifying their feature representations and window counts. Features are represented by Power Spectral Density or Differential Entropy, while windows count total non-overlapping segments across subjects.

  • Dataset features: The dataset summary identifies Power Spectral Density (PSD) and Differential Entropy (DE) as the EEG feature representations.The table defines the feature notation used across the summarized datasets.
  • Window definition: Windows denote the total number of non-overlapping segments aggregated across all subjects.This definition specifies how dataset window counts should be interpreted.

Appendix B. Thermometer Encoding

Appendix B presents the mapping between continuous input ranges, Thermometer Encoding with T = 15, and equivalent 4-bit unsigned integer precision.

  • Thermometer Encoding: The appendix maps continuous input ranges to Thermometer Encoding.The encoding uses T = 15.
  • Thermometer Encoding: T = 15 specifies the Thermometer Encoding configuration.This mapping is presented alongside continuous input ranges and equivalent integer precision.
  • Thermometer Encoding: 4-bit unsigned integer precision is given as equivalent to the encoding representation.The table relates this precision to the continuous input ranges and Thermometer Encoding.

Appendix C. Boolean operators for Differential Logic Gate Network

Appendix C defines the 16 Boolean logic gates used in Diff-Logic together with differentiable real-valued relaxations. Their inputs a and b represent probabilities that the input bits are true.

  • Boolean operators: 16 Boolean logic gates are specified for Diff-Logic.The gate set is accompanied by differentiable real-valued relaxations.
  • Boolean operators: Each Boolean gate has a differentiable real-valued relaxation used in Diff-Logic.
  • Boolean operators: The inputs a and b lie in [0, 1] and represent probabilities that the input bits are true.

Appendix D. Model Architectures Structure for Comparison · Appendix E. Exact Model Configurations

Appendix D defines matched model architectures across iso-parameter tiers, while Appendix E specifies exact parameter and gate counts. The comparison distinguishes input encoding and inference-cost scaling between Diff-Logic, MLP, and BNN.

  • Appendix D. Model Architectures Structure for Comparison: Diff-Logic uses H gates per layer, whereas MLP and BNN use H neurons per layer.
  • Appendix D. Model Architectures Structure for Comparison: All three architectures are compared at each iso-parameter tier.
  • Appendix D. Model Architectures Structure for Comparison: Diff-Logic receives thermometer-encoded binary inputs, while MLP and BNN receive continuous inputs.
  • Appendix E. Exact Model Configurations: Appendix E reports exact parameter and gate counts for the compared models.
  • Appendix E. Exact Model Configurations: For MLP and BNN, inference cost scales with the full parameter count.
  • Appendix E. Exact Model Configurations: For Diff-Logic, inference cost scales only with the compiled gate count.
Loading 2607.18149v1…