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Characterizing Warp Divergence from Pascal to Blackwell

Alpin Dale

arXiv:2607.23402v1cs.ARcs.PF

TL;DR

Cross-generational evidence was missing for the assumption that warp-divergence behavior remained fixed after Volta. This study combines microbenchmarks, hardware counters, and compiler-generated instruction analysis across Pascal, Ampere, Hopper, and Blackwell. Divergence retains a stable linear cost model even as reconvergence machinery evolves.

  • Problem

    Whether warp-divergence behavior changes across post-Volta GPU generations remained untested despite assumptions that Ampere findings transfer unchanged to Hopper and Blackwell.

    Source: §I · p. 1

  • Method

    The study combines microbenchmarks, hardware counters, and compiler-generated SASS analysis across Ampere, Hopper, two Blackwell variants, and a pre-ITS Pascal baseline.

    Source: §I · p. 1

  • Results

    From Pascal through Blackwell, divergence follows a stable linear serialization model, while compiler- and ISA-exposed reconvergence machinery changes substantially.

    Source: §VIII · p. 6

  • Takeaways & Limitations

    Performance models can reuse the divergence-cost model across Ampere–Blackwell, but increasing occupancy does not hide divergence's instruction-issue cost.

    Source: §VI · p. 5

    Evidence that Blackwell's .RELIABLE barrier field is not a runtime control is restricted to the tested executions.

    Source: §VI · p. 5

Abstract

from arXiv · show

Since Volta introduced Independent Thread Scheduling (ITS), NVIDIA GPUs have been widely assumed to handle warp divergence in a fixed manner. We test this assumption across Ampere, Hopper, and datacenter and consumer Blackwell GPUs, using pre-ITS Pascal as a baseline. Combining cycle-accurate microbenchmarks, hardware counters, and static analysis of compiler-generated SASS, we separate stable behavior from architectural change. Across all tested generations, divergent paths serialize linearly with the number of paths $k$, following $T(k) \approx sk$ with no super-linear reconvergence penalty. Warp execution efficiency falls as $32/k$, the penalty is independent of occupancy, and predication removes the serialization cost. The same behavior appears on Pascal, showing that this programmer-visible cost model predates ITS. The compiler-emitted reconvergence machinery, however, has changed substantially. Pascal uses a per-warp SSY/SYNC instruction stack, whereas later generations use barrier-register instructions. Deferred reconvergence beyond the immediate post-dominator falls from 29 cases on Ampere to 2 on Blackwell. Blackwell also introduces a two-tier convergence-barrier classification, uniform-branch instructions, and explicit partial-mask warp synchronization, none of which appear on Ampere or Hopper. Controlled bit-flip experiments indicate that the new barrier class is a static compiler classification with no observable runtime effect in our tests. Thus, divergence retains a stable and predictable performance cost even as NVIDIA's control-flow ISA and reconvergence mechanisms continue to evolve.

I. INTRODUCTION

Warp divergence has a generation-invariant linear cost across the tested Pascal, Ampere, Hopper, and Blackwell GPUs, while compiler-visible reconvergence machinery changes substantially.

I. INTRODUCTION

  • Prior microarchitecture studies largely omit control-flow divergence, while SASS-level analysis covers only Turing; no prior work compares ITS divergence across generations or measures it on Blackwell.The reconvergence model can block a lock-holding thread while peers spin, producing deadlocks; Volta’s ITS gave each thread an independent program counter and call stack to address this limitation. Ampere divergence results are often presumed to transfer unchanged to Hopper or Blackwell.Source: §I · p. 1
  • Four post-ITS GPUs spanning three generations and two Blackwell variants are characterized alongside Pascal using microbenchmarks, hardware counters, and compiler-emitted SASS analysis.The study separates invariant programmer-visible behavior from changes in compiler- and ISA-exposed control-flow machinery.Source: §I · p. 1
  • Up to 32-way splits, divergence follows T(k) ≈ s·k across Ampere, Hopper, both Blackwell variants, and Pascal, without super-linear reconvergence penalties.The small constant cost per path and Pascal result establish that linear serialization predates ITS.Source: §I · p. 1
  • 32/k is the generation-invariant warp execution efficiency; divergence penalties are occupancy-independent instruction-issue costs that additional resident warps cannot hide.Hardware performance counters independently confirm the efficiency relationship.Source: §I · p. 1
  • Deferred reconvergence beyond the immediate post-dominator nearly disappears on Blackwell; the pre-ITS baseline retains the SSY/SYNC stack replaced by barrier registers.Static analysis compares compiler-emitted reconvergence placement across generations.Source: §I · pp. 1–2
  • Blackwell adds two-tier convergence barriers, BRA.U, and partial-mask WARPSYNC absent on Ampere and Hopper; controlled bitflips reveal no observable runtime effect from barrier classes.The 2-bit barrier class distinguishes .RECONVERGENT from .RELIABLE and behaves as a static compiler classification in these tests.Source: §I · p. 2

II. BACKGROUND … C. SASS control flow and the scheduling control word

Warp divergence splits active lanes across paths that must eventually reconverge. Volta introduced independent scheduling through per-thread state, while post-Volta SASS manages reconvergence with explicit barrier instructions.

A. SIMT, reconvergence, and the IPDom stack

  • Up to 32 active lanes execute one warp instruction at a time; divergent branches partition lanes into paths executed with reduced active masks before eventual reconvergence.Source: A. SIMT, reconvergence, and the IPDom… · p. 2
  • Classical reconvergence uses a per-warp stack to reunite threads at the branch’s immediate post-dominator, the earliest instruction all paths must reach.Alternatives include dynamic warp formation, thread-block compaction, warp subdivision, thread frontiers, stack-less designs, and divergence-aware scheduling –.Source: A. SIMT, reconvergence, and the IPDom… · p. 2

B. Independent Thread Scheduling

  • Volta replaced the single per-warp program counter with per-thread state, enabling independent scheduling of divergent threads and guaranteeing forward progress.This removed the classic spin-lock deadlock permitted by the stack model,.Source: B. Independent Thread Scheduling · p. 2
  • Independent Thread Scheduling no longer guarantees implicit reconvergence, motivating explicit __syncwarp() convergence barriers.How ITS schedules divergent paths in practice, and whether that scheduling has changed since Volta, is not publicly documented.Source: B. Independent Thread Scheduling · p. 2

C. SASS control flow and the scheduling control word

  • Post-Volta SASS uses BSSY to establish a reconvergence barrier at a target program counter and BSYNC to wait, rather than an implicit hardware stack.Source: C. SASS control flow and the… · p. 2
  • 128-bit SASS instructions since Volta carry compiler-assigned scheduling control words encoding a stall count, yield hint, scoreboard dependencies, and reuse cache.SASS is NVIDIA’s proprietary binary instruction-set architecture.Source: C. SASS control flow and the… · p. 2

III. EXPERIMENTAL SETUP · IV. THE COST OF DIVERGENCE · A. Divergence is linear path serialization

Divergence latency scales linearly with the number of paths across all tested GPUs, including pre-ITS Pascal, without a measurable super-linear reconvergence penalty. The experiments combine cycle measurements, validated efficiency counters, and SASS inspection to distinguish genuine divergence from compiler predication.

III. EXPERIMENTAL SETUP

  • The study pairs dynamic GPU microbenchmarks with static analysis of compiler-generated SASS across architectures.Static compilation covers sm_80 through sm_120; Pascal sm_61 SASS is generated on its own host because current toolchains no longer target it. Post-ITS GPUs run CUDA 13, while Pascal runs CUDA 12.4.Source: §III · p. 2, Table I · p. 2
  • Long, non-mergeable per-path loops bracketed by per-class __syncwarp() force genuine divergent branches rather than compiler predication.Disassembly confirms BSSY/BSYNC reconvergence barriers, or SSY/SYNC on Pascal. Predication can preserve instruction counts without reducing SIMD utilization, potentially misleading timing-only experiments.Source: §III · p. 2
  • 201 launches per datum yield median cycle measurements with a coefficient of variation below 10^-4 on every GPU.The clock64() SM counter brackets the measured region; frequency-independent cycle counts make per-path slopes comparable despite different GPU clocks. Measurements are effectively deterministic, so error bars are omitted.Source: §III · p. 2
  • 32.0, 16.3, and 1.6 active threads per instruction validate the efficiency counter for convergent, 2-way, and 32-way kernels, respectively.Nsight Compute’s smsp__thread_inst_executed_per_ inst_executed.ratio measures average active threads per issued warp-instruction, with 32 representing full convergence.Source: §III · p. 2

A. Divergence is linear path serialization

  • 54.1 k, 58.1 k, 46.1 k, and 70.1 k cycles are the per-path slopes for Ampere, Hopper, both Blackwell parts, and Pascal, respectively.Blackwell executes a path about 15–20% faster than Hopper without changing the serialization model. Identical server and consumer Blackwell slopes indicate an architecture-family rather than chip-specific cost.Source: A. Divergence is linear path… · pp. 2–3
  • 31.7–31.9× single-path latency for a 32-way split across all tested GPUs demonstrates linear path serialization without a measurable super-linear reconvergence penalty.Balanced paths perform identical work, and latency fits T(k) ≈ s·k + c. Constant overhead is roughly 2 k cycles on post-ITS GPUs and negligible on Pascal.Source: A. Divergence is linear path… · pp. 2–3, Figure 1 · p. 3
  • Within 0.6% across k, Pascal’s per-path cost remains flat, demonstrating that linear serialization predates ITS.Pascal’s larger per-path constant reflects its lower single-thread throughput.Source: A. Divergence is linear path… · p. 3

B. Efficiency falls as 32/k

Hardware counters show that active threads per warp-instruction fall almost exactly as 32/k on all four post-ITS GPUs. This confirms that linear divergence costs reflect lost SIMD utilization rather than predicated or redundant execution.

B. Efficiency falls as 32/k

  • Hardware counters confirm that linear divergence costs reflect lost SIMD utilization rather than predicated or redundant execution.A k-way divergent region issues the same instructions k times, each with 32/k active lanes.Source: B. Efficiency falls as 32/k · p. 3
  • Pascal lacks counter measurements because driver permissions restrict access, but its linear timing cost and occupancy-invariant penalty establish the same lost-utilization effect.Performance-counter access on the available driver is restricted to administrators.Source: B. Efficiency falls as 32/k · p. 3
  • 32/k closely matches active threads per warp-instruction on all four post-ITS GPUs, whose measured curves are indistinguishable.Measured values are 31.9, 16.2, 8.3, 4.25, 2.23, and 1.21 for k = 1, 2, 4, 8, 16, and 32, respectively.Source: Figure 2 · p. 3, B. Efficiency falls as 32/k · p. 3

C. Predication removes the serialization · D. The penalty is occupancy-invariant · E. Forward progress holds, but paths run in order

Predication eliminates the measured serialization cost, whereas increasing occupancy does not reduce divergence penalties. Forward-progress tests succeed, but divergent paths run in structural order without fine-grained interleaving in the absence of contended synchronization.

C. Predication removes the serialization

  • 2.00× falls to 1× when predication replaces two-way divergence on all four post-ITS GPUs.The branch-free formulation computes both arms; post-ITS measured ratios are within 0.5% of 2.00. Pascal’s cost falls from 1.94× to 1×.Source: C. Predication removes the serialization · p. 3

D. The penalty is occupancy-invariant

  • A divergent warp issues k× more instructions; occupancy hides latency rather than instruction count, explaining why additional warps cannot amortize divergence.The passage identifies eliminating divergence through predication or data reorganization as the effective remedy regardless of occupancy.Source: D. The penalty is occupancy-invariant · p. 3

E. Forward progress holds, but paths run in order

  • 32 lanes contending for one lock all complete successfully on every tested generation, including pre-ITS Pascal.Each lane acquires the lock, enters a critical section, and releases it.Source: E. Forward progress holds, but paths… · p. 3
  • The lock experiment does not exercise classical stack deadlock because release occurs within the acquiring branch.Classical stack deadlock requires an unbounded intra-warp peer-wait, which the authors do not run on shared hardware.Source: E. Forward progress holds, but paths… · p. 3

D. The penalty is occupancy-invariant

E. Forward progress holds, but paths run in order

  • Two spin iterations suffice for consumers to observe the producer’s result, revealing that divergent paths execute in structural order and run to completion.This holds even when the producer performs 107 iterations of work. Without contended synchronization, ITS provides forward progress without fine-grained interleaving of divergent paths.Source: E. Forward progress holds, but paths… · pp. 3–4

V. RECONVERGENCE ACROSS GENERATIONS · A. From an instruction stack to barrier registers

Reconvergence machinery evolves from Pascal’s per-warp instruction stack to barrier registers and Blackwell’s reliability-tagged scheme, while measured divergence cost remains fixed. A 38-kernel SASS analysis examines these mechanisms and reconvergence placement.

V. RECONVERGENCE ACROSS GENERATIONS

  • 38 kernels are compiled for every architecture from sm_80 to sm_120, and their generated SASS is analyzed.Pre-ITS Pascal is treated separately because it lacks the barrier-register mechanism.Source: §V · p. 4
  • For each divergent branch, analysis reconstructs the control-flow graph, computes the immediate post-dominator, and classifies the matching BSYNC placement.This procedure applies to the barrier-register generations.Source: §V · p. 4
  • The corpus spans simple and nested branches, switch statements, loops with early exits, short-circuit evaluation, and deliberately irreducible control flow.These patterns broaden the analysis beyond simple divergent branches.Source: §V · p. 4

A. From an instruction stack to barrier registers

  • Pascal manages divergent regions with SSY pushing a reconvergence PC and SYNC popping it; nested divergence produces nested instruction pairs.This is a per-warp reconvergence stack.Source: A. From an instruction stack to… · p. 4
  • Post-Volta generations use BSSY/BSYNC barrier registers, with Blackwell adding a reliability-tagged two-tier scheme.No BSSY, BSYNC, or BREAK instructions appear anywhere in the Pascal corpus.Source: A. From an instruction stack to… · p. 4
  • 29 deferred reconvergence cases on Ampere fall to 2 on Blackwell, despite measured divergence cost remaining fixed across generations.Deferred reconvergence occurs later than the immediate post-dominator.Source: Figure 4 · p. 4, A. From an instruction stack to… · p. 4

B. Deferred reconvergence disappears · C. A two-tier convergence barrier on Blackwell

Deferred reconvergence falls from 29 branches on Ampere to 2 on Blackwell. Blackwell introduces two barrier classes distinguishing partial from final reconvergence, but changing their encoding produces no observable runtime effects in the tested kernels.

B. Deferred reconvergence disappears

  • 29 divergent branches reconverge after the immediate post-dominator (IPDom) on Ampere, falling to 7 on Hopper and 2 on Blackwell.Deferred reconvergence postpones merging through unrolled or nested loops.Source: B. Deferred reconvergence disappears · p. 4
  • 72.7% of Ampere branches, 90.8% of Hopper branches, and 83.2% of Blackwell branches reconverge exactly at the IPDom.Blackwell trades the diminished deferred tail for a new class of earlier-than-IPDom reconvergence.Source: B. Deferred reconvergence disappears · p. 4

C. A two-tier convergence barrier on Blackwell

  • 2-bit reliability fields encode Blackwell’s .RECONVERGENT and .RELIABLE BSSY/BSYNC modifiers, which are absent on Hopper and earlier GPUs.The two modifiers occupy distinct non-zero field values on sm_100 and later.Source: C. A two-tier convergence barrier on… · p. 4
  • .RECONVERGENT marks the true post-dominator merge that all lanes ultimately reach and was never observed to be broken out of.Earlier generations’ single bare barrier cannot express the nested partial-and-final reconvergence scheme.Source: C. A two-tier convergence barrier on… · pp. 4–5
  • .RELIABLE marks early partial reconvergence at unrolled-iteration and short-circuit-clause boundaries, nested inside an enclosing .RECONVERGENT region.BREAK is encoding-restricted to .RELIABLE, allowing a subset of lanes to exit early. This nested scheme accounts for Blackwell’s before-IPDom reconvergences.Source: C. A two-tier convergence barrier on… · pp. 4–5
  • Direct cubin edits, disassembly verification, and a store-disabling positive control establish that the driver executes patched instruction bytes rather than re-deriving them.The mutated kernels were executed through the driver API; disabling a store changed the output.Source: C. A two-tier convergence barrier on… · p. 5
  • Flipping Blackwell’s barrier-class field left output, completion, warp-level forward progress, convergence-sensitive partner exchange, and cycle counts unchanged in every tested kernel.The results support a static compiler/assembler classification rather than runtime control; barrier registers and BSSY/BSYNC/BREAK opcodes govern reconvergence and forward progress. Tests included mismatched pairs, an assembler-unemitted BREAK.RECONVERGENT encoding, and the identically executing pre-Blackwell bare encoding.Source: C. A two-tier convergence barrier on… · p. 5

D. Uniform branches and partial-mask synchronization

Within the studied corpus, Blackwell alone exposes uniform branches and explicit partial-mask warp synchronization in its ISA. It also limits live reconvergence-barrier nesting by predicating rather than spilling.

Uniform branches and partial-mask synchronization

  • 23 BRA.U occurrences on Blackwell, versus 0 on Ampere/Hopper, mark branches the compiler proves non-divergent.BRA.U is predicated on a uniform datapath register and preceded by a uniform ISETP, replacing divergent BRA instructions where uniformity is provable.Source: D. Uniform branches and partial-mask… · p. 5
  • Blackwell emits explicit WARPSYNC for partial-mask warp intrinsics, whereas Ampere and Hopper emit bare shuffles without a barrier.These intrinsics use __shfl or __syncwarp under a data-dependent mask, making partial-mask reconvergence explicit on Blackwell.Source: D. Uniform branches and partial-mask… · p. 5
  • 3 live reconvergence-barrier levels on Blackwell, versus 4 on older parts, are enforced by predicating an additional level rather than spilling.No BMOV barrier-spill instruction was observed on any tested generation.Source: D. Uniform branches and partial-mask… · p. 5

VI. DISCUSSION

Divergence costs remain stable across Ampere–Blackwell even as reconvergence machinery evolves. The experiments leave limitations concerning forward progress, .RELIABLE behavior, and interactions with memory divergence.

Performance implications

  • k× cost and 32/k efficiency characterize k-way divergence across Ampere–Blackwell; predication recovers performance, but greater occupancy cannot hide the penalty.Divergence increases issue count rather than exposing latency. Analytical models and simulators, can therefore treat this divergence-cost kernel as fixed.Source: §VI · p. 5

Control-flow evolution

  • Blackwell’s disappearance of deferred reconvergence and introduction of two-tier barriers make reconvergence distinctions more explicit than on earlier generations.Single-generation binary-analysis tools, and SASS-level models, will mis-model Blackwell control flow unless they incorporate its new instructions.Source: §VI · p. 5

Limitations

  • Single-warp bitflip experiments on sm_110 show no runtime effect from .RELIABLE, but do not exclude effects in untested regimes.Possible untested uses include particular multi-warp scheduling conditions and consumption of the field by profilers or debuggers.Source: §VI · p. 5
  • Pascal also completes the bounded forward-progress probes; classical stack deadlock remains supported by prior analysis, not reproduced by these experiments.Forcing that deadlock requires an unbounded intra-warp peer-wait, which the authors do not run on shared hardware.Source: §VI · p. 5
  • The kernels isolate path serialization, while real applications interleave divergence with memory divergence that this study does not separate.Source: §VI · p. 5

VII. RELATED WORK · VIII. CONCLUSION

Divergence costs remain stable across the tested GPUs, but compiler-visible reconvergence mechanisms and control-flow instructions have changed substantially.

VII. RELATED WORK

  • Prior NVIDIA microbenchmarks,,,,, emphasize memory, tensor cores, and instruction throughput; this work adds cross-generational control-flow analysis.Control-flow divergence is essentially absent from those earlier studies.Source: §VII · p. 5
  • Eight compute capabilities, sm_61 through sm_120, extend Turing control-flow reverse engineering across four architecture families.The analysis contrasts the pre-ITS stack with barrier registers and identifies Blackwell-specific instructions and barrier classes unavailable to the earlier study.Source: §VII · p. 6
  • Beyond compiler divergence analysis, and scalarization/melding,, this study measures reconvergence placement and forward-progress behavior introduced by ITS,.The earlier reconvergence and mitigation literature largely predates or assumes the IPDom-stack model.Source: §VII · p. 6
  • Revisiting pre-ITS divergence benchmarks [29], this study adds Pascal/post-ITS comparisons, hardware-counter cross-checks, predication controls, and occupancy-invariance and cross-generational-invariance results.These controls distinguish measured divergence costs from compiler predication effects.Source: §VII · p. 6

VIII. CONCLUSION

  • 32/k efficiency accompanies linear divergence serialization across Ampere, Hopper, both Blackwell variants, and pre-ITS Pascal.Predication recovers lost utilization, while additional occupancy does not hide the issue cost.Source: §VIII · p. 6
  • ITS generations replace Pascal’s SSY/SYNC reconvergence stack with barrier registers, while deferred reconvergence has all but vanished.The stable measured performance therefore coexists with substantial changes in compiler-visible reconvergence machinery.Source: §VIII · p. 6
  • Blackwell introduces a two-tier .RECONVERGENT/.RELIABLE barrier scheme, uniform branches, and explicit partial-mask synchronization absent from earlier generations’ emitted instructions.Architecture and tooling work must account for this evolving control-flow ISA.Source: §VIII · p. 6
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