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Simulation-Aware In-Context Policy Improvement for LLM-Aided Analog Layout Refinement

Bingyang Liu, Ziming Wei, Xiaohan Gao, David Z. Pan

arXiv:2608.13767v1cs.AIcs.RO

TL;DR

Analog layout refinement still depends on costly, expert-driven simulation loops, while BO requires many evaluations and prior LLM methods lack faithful geometric context. This paper introduces a simulation-aware multi-agent ICPI framework that updates generator parameters through structured layout states and act–observe–reflect feedback. On real-world circuits, it improves post-layout performance over built-in heuristics, BO, and a non-ICPI baseline using tens of simulations.

  • Problem

    Analog layout optimization lacks an automatic, sample-efficient way to tune generator parameters from sparse post-layout simulation feedback while representing geometric layout changes faithfully.

  • Method

    A simulation-aware LLM multi-agent framework performs in-context policy improvement by iteratively updating exposed placement and routing parameters through structured layout states and an act–observe–reflect loop.

  • Results

    With tens of post-layout simulations, the framework outperforms built-in heuristics, BO-based tuning, and a non-ICPI baseline on two OTA benchmarks.

  • Takeaways & Limitations

    Simulation-aware ICPI can improve analog layout refinement over established heuristic and BO tuning under a small post-layout simulation budget on the studied circuits.

  • Takeaways & Limitations

    Scaling the framework to more complex systems remains challenging because state representation complexity and simulation-driven search costs grow.

Abstract

from arXiv · show

Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement. Although end-to-end layout generators accelerate initial placement and routing, they still require experts to manually tune layout optimization parameters with repeated post-layout simulations for stringent design specifications. While Bayesian Optimization (BO) is widely adopted for parameter tuning in analog IC design, at the layout level it typically requires hundreds to thousands of evaluations, each involving costly parasitic extraction and post-layout simulation, which makes it impractical. Recently, Large Language Models (LLMs) have demonstrated potential in improving the sample efficiency of such simulation-driven tuning. However, their restricted access to geometric layout context and design-specific heuristics limits their ability to manipulate the layout optimization process. In this paper, we propose a simulation-aware LLM multi-agent framework that performs in-context policy improvement (ICPI) by iteratively updating layout optimization parameters exposed by an analog layout generator through an act-observe-reflect loop on compact structured layout representations. Experiments on real-world analog circuits show that, with only tens of post-layout simulations, our approach improves post-layout performance over the generator's built-in heuristics and BO-based tuning method.

I. INTRODUCTION

Analog IC layout refinement remains an expert-driven, simulation-intensive loop, while automated generators accelerate initial layout generation but do not eliminate costly parameter tuning. This paper introduces a simulation-aware multi-agent ICPI framework that uses structured layout states and sparse post-layout feedback to improve generator parameters under tight simulation budgets.

  • Motivation: Analog layout refinement remains human-driven because designers repeatedly modify layouts and run costly post-layout simulations from sparse feedback.The process requires reasoning over design-specific simulation feedback rather than following a fixed procedure.
  • Motivation: Automated placement-and-routing algorithms and end-to-end layout generators have accelerated initial analog layout generation.Prior approaches span classical, domain-knowledge-driven, and machine-learning techniques, including ALIGN and MAGICAL.
  • Challenge: Hundreds to thousands of samples are typically required by BO per design, whereas layout simulation budgets often allow only tens of runs.Each sample requires costly parasitic extraction and post-layout simulation, making BO impractical for layout-level tuning.
  • Method: The proposed ICPI framework iteratively updates generator-exposed placement and routing parameters to evolve a design-specific refinement policy.Parameters include net weights, placement bias, symmetry constraints, routing priorities, and wire widths.
  • Method: The framework combines a compact structured layout state with a simulation-aware act–observe–reflect loop and persistent design journal.The state includes connectivity, device locations, optimization parameters, parasitic summaries, and post-layout outcomes; each round updates one parameter family from sparse feedback.
  • Results: Across two OTA benchmarks, the method achieves better post-layout performance than built-in heuristics, BO-based tuning, and a non-ICPI baseline under small simulation budgets.The benchmarks span different technologies and parameter-space scales.

II. PRELIMINARIES · A. In-Context Policy Improvement and Self-Feedback

In-context policy improvement enables LLMs to refine behavior through iterative feedback, reflection, retrieval, and environment interaction. Analog layout optimization is a suitable setting because its exposed controls are interpretable and its simulations provide domain-specific signals.

  • A. In-Context Policy Improvement and Self-Feedback: Self-refinement methods use a propose–feedback–refine pattern to improve LLM behavior at test time under fixed weights.The model produces an answer, generates feedback or confidence signals, then rewrites or abstains based on that feedback.
  • A. In-Context Policy Improvement and Self-Feedback: These methods structure feedback, reflection, and retrieval around the model’s own outputs.The supplied passage identifies these mechanisms as part of recent work on LLM self-feedback and internal consistency.
  • A. In-Context Policy Improvement and Self-Feedback: ReAct-style agents interleave chain-of-thought reasoning with environment actions, while Reflexion adds explicit self-feedback to the loop.Reflexion summarizes failures and proposes strategy updates that are incorporated into later prompts.
  • A. In-Context Policy Improvement and Self-Feedback: Propose–execute–revise patterns also support code optimization and configuration frameworks through repeated edits to programs or settings.The passage presents these frameworks as domain-specific appearances of ICPI ideas.
  • A. In-Context Policy Improvement and Self-Feedback: ICPI is particularly suited to tasks with semantically meaningful controls and rich, domain-specific feedback from the environment.The passage identifies these two properties as the conditions suggested by prior studies.
  • A. In-Context Policy Improvement and Self-Feedback: Analog layout back-end optimization has interpretable controls such as symmetry constraints, wirelength weights, routing priorities, and wire widths and spacings.Its environment also returns signals through parasitic extraction and post-layout simulation.

B. End-to-end Analog Layout Generator · III. FRAMEWORK

End-to-end analog layout generators convert circuit specifications into layouts through automated placement and routing pipelines, but practical flows still depend on manually tuned constraints and tool parameters. The framework addresses this dependence by synchronizing structured layout states with iterative LLM-based parameter refinement under a limited post-layout simulation budget.

  • B. End-to-end Analog Layout Generator: Modern generators produce layouts directly from netlists, technology information, and user constraints using placement followed by design-rule-aware legalization and routing.The cited passage identifies MAGICAL, ALIGN, and other analog placement-and-routing frameworks as examples sharing this broad pipeline.
  • B. End-to-end Analog Layout Generator: ICPI organizes layout optimization parameters into parameter families for LLM-guided refinement.Table I is titled “Layout Optimization Parameter Families Used in ICPI.”
  • B. End-to-end Analog Layout Generator: Practical layout flows still require designers to provide and tune symmetry groups, optimizer configurations, wire-spacing options, and global objective-balancing weights.These parameters support tradeoffs among different layout objectives.
  • B. End-to-end Analog Layout Generator: Analog layout generators could expose finer-grained controls such as device anchors, well-cluster assignments, per-net wirelength weights, and routing parameters.The passage contrasts these potential net-level controls with the smaller set of parameters commonly tuned in practice.
  • III. FRAMEWORK: The framework targets precise LLM access to evolving layouts beyond ambiguous natural-language descriptions.This is one of the two challenges identified for LLM-aided simulation-aware analog layout refinement.
  • III. FRAMEWORK: The framework also seeks to improve parameter decisions across iterations while operating within a budget of only tens of expensive post-layout simulations.The paper presents this as the second central challenge addressed by the framework.
  • III. FRAMEWORK: Three core components address these challenges, including a structured layout state that synchronizes the evolving layout for iterative refinement.Figure 2 introduces the three-component framework, although the supplied passage names only the structured layout state component.

A. Action Space and Circuit-Level Analysis · B. Layout State

The framework exposes interpretable layout optimization parameters and uses an off-loop circuit Analyzer to guide refinement under a limited simulation budget. It represents layout state with synchronized structural context, active parameters, and post-layout feedback so LLM agents can reason about current behavior and its causes.

  • A. Action Space and Circuit-Level Analysis: The framework builds on MAGICAL with extended PDK support and interfaces exposing placement and routing parameters while leaving underlying optimization algorithms unchanged.These exposed parameters govern layout evolution rather than generic tool hyperparameters.
  • A. Action Space and Circuit-Level Analysis: Five interpretable parameter families organize the action space: net weights, placement bias, symmetry constraints, routing priorities, and wire widths.They affect placement proximity, directional bias, matching tightness, routing-resource allocation, and wire-width tradeoffs.
  • A. Action Space and Circuit-Level Analysis: The structured parameter space remains combinatorially large under coarse discretization across many nets and devices.This makes the action space more tractable than raw layout editing but still difficult to explore exhaustively.
  • A. Action Space and Circuit-Level Analysis: Under only tens of expensive post-layout evaluations, black-box exploration covers a very small fraction of the parameter space.The framework therefore adds an off-loop Analyzer that processes the netlist once before iterative refinement.
  • B. Layout State: The layout state avoids raw polygons and full GDS descriptions because polygon-level representations are verbose and image-based representations obscure circuit topology and routing connectivity.It instead uses a structured, synchronized intermediate representation for conveying layout information to the LLM.
  • B. Layout State: The layout state records connectivity, subcircuit membership, bounding boxes, coordinate-based geometry, and current exposed parameters.This combines circuit structure and geometric context with visibility into the active parameter family and how the layout is being steered.
  • B. Layout State: By combining structure, parameters, and feedback, the layout state lets the LLM assess the layout’s current appearance, behavior, and settings responsible for that behavior.This supports reasoning within a short context window.
  • B. Layout State: After each post-layout simulation, the state appends performance results that approximately indicate layout quality.The representation therefore combines structural information, applied parameters, and observed feedback in one context.

C. Design Journal · D. ICPI Loop

The paper introduces a design journal that gives the ICPI loop persistent, design-specific memory of parameter edits and outcomes. Three role-specific agents use this memory in an act–observe–reflect loop to select, execute, and assess layout-parameter updates.

  • C. Design Journal: The journal enables adaptation within each design instance instead of relying only on static prompts or hand-crafted exemplars.Prior LLM-assisted efforts mainly injected expertise through fixed instructions without persistent memory of design-specific edit outcomes.
  • C. Design Journal: The design journal stores compressed round snapshots, selected parameter families, intended goals, edits, outcomes, reflections, and failure-handling experience.It serves as cross-round memory for the ICPI loop.
  • D. ICPI Loop: The Supervisor begins each round by combining the current layout state, circuit-level hints, journal history, and recent feedback to select exactly one parameter family.It formulates high-level goals while making policy-level decisions at the parameter-family level.
  • D. ICPI Loop: The Executor converts Supervisor goals into concrete updates by consulting prior attempts from the same parameter family before invoking the layout generator.It chooses which parameters to modify and by how much, using design-journal experience.
  • D. ICPI Loop: The Executor uses a traceback loop to roll back when proposed settings produce an illegal layout.The passage gives over-constrained symmetry and overly aggressive widths as examples of generator failure conditions.
  • D. ICPI Loop: After each round, the Reflector compresses the history into a journal entry explaining the selected parameters, outcomes, and why the change appears helpful or harmful.Over time, the journal records what worked, what failed, and how parameter families interact with the circuit.
  • D. ICPI Loop: All agents share one backbone LLM with role-specific prompts and fixed output schemas, while the Analyzer, Supervisor, Executor, and Reflector receive distinct information or output constraints.The Analyzer receives structured netlist serialization; the Supervisor receives layout state, circuit hints, and the journal; the Executor returns concrete updates and short rationales.

IV. EXPERIMENTAL RESULTS · A. Experimental Setup

The framework is evaluated on two realistic OTA layout benchmarks using costly extraction and simulation, against heuristic and Bayesian-optimization baselines. Electrical quality is summarized by a geometric-mean figure of merit that penalizes specification violations and remains sensitive to degradation across metrics.

  • A. Experimental Setup: The evaluation uses two OTAs spanning different technology nodes and topologies: a two-stage Miller-compensated OTA in 65 nm and a fully differential common-mode-feedback OTA in 40 nm.Although limited to two designs, the benchmarks are described as non-toy examples.
  • A. Experimental Setup: Each candidate undergoes full layout generation and parasitic extraction, while selected iterations additionally require post-layout simulation, making the optimization budget unlike conventional low-cost parameter search.This evaluation setup is intended to test the framework under expensive simulation-driven refinement.
  • A. Experimental Setup: The implementation extends the open-source MAGICAL-derived layout generator with broader PDK support and interfaces exposing layout optimization parameters.Parasitic extraction uses Siemens Calibre, and post-layout simulation uses Spectre within Cadence Virtuoso.
  • A. Experimental Setup: The framework is compared with Heuristic fixed settings and BO Bayesian optimization over the same exposed parameter space.Heuristic fixes net weights, bias terms, symmetry constraints, routing priorities, and wire widths; BO treats post-layout performance as its optimization objective.
  • A. Experimental Setup: Electrical quality is summarized by a scalar FoM over Gain, UGB, and CMRR, using each metric’s target L_m and value v_m.The supplied definition specifies target-based scoring for these three metrics.
  • A. Experimental Setup: The scoring applies a quadratic penalty below minimum targets and a bounded reward above them, with phase margin targeted at L_PM = 60°.The metric score equals 1 at its target, increases smoothly above target, and caps phase-margin contribution once stability is sufficient.
  • A. Experimental Setup: The final FoM is the geometric mean of s_Gain, s_UGB, and s_CMRR multiplied by α_PM, making it sensitive to degradation in any metric.The phase-margin factor is capped after sufficient stability, while the geometric mean aggregates the three electrical-quality scores.

B. Post-layout Performance Comparison

Across OTA1 and OTA2, ICPI achieves stronger post-layout electrical performance than the compared tuning methods within the reported simulation budget. The comparison also distinguishes electrical gains from area increases and reveals a qualitative robustness advantage over BO.

  • Evaluation protocol: Area is reported separately because neither BO nor ICPI directly optimizes it; the objective is purely electrical FoM within the exposed parameter space.
  • Robustness: BO can yield geometrically legal, LVS-clean candidates that are electrically non-functional because excessive parasitics prevent loop gain from reaching unity, resulting in zero FoM.Ours instead encounters backend-infeasible intermediate proposals, including over-constrained symmetry or overly aggressive parameter combinations.
  • OTA1: Ours achieves the highest OTA1 FoM, 1.104, exceeding Ours w/o ICPI at 1.003 and BO at 0.979.The ICPI layout has area essentially identical to BO, while being larger than the Heuristic design.
  • OTA2: Under the same 31-candidate horizon, BO improves all four OTA2 electrical metrics over the Heuristic but remains below the CMRR target and increases area by more than 25%.OTA2 has a parameter dimension roughly two orders of magnitude higher than OTA1.
  • OTA2: Ours w/o ICPI improves both OTA2 FoM and area over the Heuristic but does not meet the Gain and CMRR targets, whereas Ours meets all four electrical targets.

C. Runtime and overhead

Agent orchestration is relatively lightweight compared with parasitic extraction and post-layout simulation. Across OTA1 and OTA2, orchestration remains a minority of total wall-clock time under the stated conservative timing bound.

  • Agent orchestration cost: Per round, orchestration takes about 37 s and 12k tokens for OTA1 and about 43 s and 17k tokens for OTA2.Input context accounts for over 90% of the tokens.
  • Relative runtime: Less than 16% of total wall-clock time is attributable to LLM orchestration, versus more than 141 min for parasitic extraction and post-layout simulations per design.Over 30 rounds, orchestration amounts to roughly 18 to 21 minutes; the comparison uses a conservative lower-bound timing and excludes place-and-route.

V. CONCLUSION

The paper presents a simulation-aware LLM multi-agent framework that improves analog layout optimization parameters through an act–observe–reflect loop using sparse post-layout feedback. With only tens of post-layout simulations, it improves performance over built-in heuristics, BO-based tuning, and a non-ICPI baseline.

  • Conclusion: The framework performs in-context policy improvement over layout optimization parameters through an act–observe–reflect loop driven by sparse post-layout feedback.It wraps a mature analog layout generator in a simulation-aware LLM multi-agent framework.
  • Conclusion: With only tens of post-layout simulations, the approach improves post-layout performance over built-in heuristics, BO-based tuning, and a non-ICPI baseline.The result is demonstrated on real-world analog circuits.
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