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PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization

Ruogu Chen, Jie Han

arXiv:2608.13790v1cs.LGcs.AIcs.AR

TL;DR

HPWL and pre-route labels poorly preserve post-route timing rankings, motivating a predictor that uses complete mixed-size placements and post-GRT supervision. PPAPlace propagates predicted timing gradients through co-optimization and refinement, improving average WNS and TNS by 22% and 51% over the hierarchical baseline on five held-out circuits.

  • Problem

    HPWL and pre-route timing labels poorly reflect post-route timing, while existing methods omit standard-cell density and routing congestion from their representations.

  • Method

    PPAPlace is a differentiable dual-stream surrogate trained on post-GRT labels that predicts post-route PPA from macro and standard-cell placements and supplies timing gradients for co-optimization and refinement.

  • Results

    22% and 51% improvements in average WNS and TNS over Hier-RTLMP were achieved on five held-out circuits.

  • Takeaways & Limitations

    Post-GRT supervision and differentiable timing feedback provide a learned post-route objective for placement optimization while preserving power and routability.

  • Takeaways & Limitations

    The study uses RTLMP placements for label fidelity, and broader validation across technology nodes, libraries, and placer settings remains needed.

Abstract

from arXiv · show

Macro placement significantly affects a chip's post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics such as the worst negative slack (WNS) and total negative slack (TNS). As a result, all six evaluated artificial intelligence (AI) placers degraded PPA relative to the hierarchical baseline. Recent efforts have tried to train cross-stage predictors to close this gap. However, existing methods focus on macro-only representations and use pre-route metrics as training labels. A label fidelity study of ten circuits at four design flow stages reveals that HPWL and pre-route timing poorly reflect final post-route timing rankings. In contrast, post-global-routing achieves the best balance between final timing fidelity and label generation cost-effectiveness. Based on this finding, PPAPlace is a timing-driven differentiable surrogate predicting post-route PPA from macro and standard-cell placements. The surrogate is a dual-stream predictor that combines graph attention over the chip netlist with spatial convolution over the placement grid. It is trained on post-global-routing labels. The predicted WNS and TNS gradients flow end-to-end back to cell coordinates. PPAPlace exploits these gradients in two ways: as a co-objective injected into an analytical placer's optimization loop (PPAPlace-CoOpt), and as a post-placement refinement step that adjusts macro positions via projected gradient descent (PPAPlace-Refine). On five ChiPBench test circuits excluded from training, PPAPlace improves average WNS and TNS by 22\% and 51\% over the hierarchical baseline while preserving power and routability, using the same predictor without test-circuit retraining. Code is available at https://github.com/ValleyC/PPAPlace.

1 Introduction

PPAPlace addresses the weak relationship between conventional placement proxies and post-route PPA by selecting higher-fidelity supervision and enabling differentiable timing optimization over mixed-size placements.

  • Motivation: ChiPBench found that all six evaluated AI placers degraded PPA relative to Hier-RTLMP, while macro HPWL correlated only −0.08 with WNS.These results challenge HPWL as a reliable timing objective.
  • Motivation: Existing approaches commonly use pre-route STA labels and macro-only representations, omitting standard-cell density and routing congestion.The paper examines both assumptions as potential sources of cross-stage mismatch.
  • Label selection: A ten-circuit study identifies post-global-routing labels as high-fidelity and cost-effective for preserving final post-route timing rankings.The study provides the supervision-stage basis for PPAPlace.
  • Method: PPAPlace combines graph attention over netlist connectivity with spatial convolution over mixed-size placement features and propagates predicted timing gradients to cell coordinates.The spatial stream encodes cell density, pin density, and RUDY-style congestion.
  • Deployment: PPAPlace-CoOpt adds the surrogate to DREAMPlace’s optimization loop, while PPAPlace-Refine applies post-placement gradient descent to converged placements.Refine does not require access to the source placer’s internals.
  • Results: 22% and 51% improvements in WNS and TNS over the hierarchical baseline were achieved while preserving power and routability.The result uses the combined gradient-guided deployment modes.

2 Related Work

Prior work extends analytical, learning-based, and cross-stage placement methods with learned or engineered objectives, but does not optimize mixed-size placement for post-route PPA.

  • Analytical placement: Analytical placers optimize smooth wirelength and density objectives through continuous gradient-based optimization.DREAMPlace recasts this formulation as neural-network training and reports over 30× GPU speedup.
  • Analytical placement: AutoDMP uses Bayesian optimization to tune DREAMPlace parameters against post-placement proxies such as RSMT wirelength, density, and RUDY congestion.These proxies are computed before routing and can remain mismatched with post-route PPA.
  • Differentiable objectives: Efficient-TDP and RoutePlacer inject differentiable timing or congestion objectives into DREAMPlace, targeting single intermediate metrics.RoutePlacer reports routing-overflow reduction of up to 16%.
  • AI-based placement: AI-based methods including reinforcement learning, black-box optimization, diffusion, and evolutionary search generally optimize HPWL or macro HPWL as the primary objective.The methods differ algorithmically but share this objective emphasis.
  • Cross-stage methods: LaMPlace, MacroRank, PreRoutGNN, and Re2MaP address cross-stage prediction or macro placement but do not integrate predictors into mixed-size placement optimization.LaMPlace’s main timing labels are generated before CTS or routing.

3 Preliminaries

The paper frames placement as coordinate optimization over a netlist hypergraph, evaluates it through downstream PPA flow stages, and motivates differentiable surrogates to avoid repeated full-flow computation.

  • Placement formulation: A placement assigns normalized coordinates to macros and standard cells represented as vertices in a netlist hypergraph.The hypergraph consists of modules V and connecting nets E.
  • Placement formulation: Analytical placers minimize a smooth wirelength approximation plus a density penalty that discourages cell overlap.The density weight controls the relative contribution of the penalty.
  • Evaluation metrics: Post-route PPA is obtained through CTS, GRT, and DRT, which progressively add fidelity to timing and congestion estimates.The full downstream flow is denoted F(x), with F_s(x) ending at stage s.
  • Evaluation metrics: The PPA output contains WNS, TNS, power, and area, while direct computation typically takes tens of minutes to hours.WNS is worst negative slack and TNS is total negative slack.
  • Cross-stage prediction: A cross-stage predictor approximates final PPA from placement-stage features, provided its training labels preserve the final ranking of placements.This motivates comparing supervision stages before predictor training.

4 Label Fidelity Analysis

Across ten diverse circuits evaluated through the complete flow, post-GRT timing rankings best match post-DRT ground truth while costing substantially less than detailed routing.

  • Study design: The study covers ten circuits spanning CPU, neural-processing, and peripheral designs, with 10–132 macros and 33K–427K cells.The range tests multiple design scales and application domains.
  • Study design: Each of 20 RTLMP configurations per circuit was evaluated through synthesis, floorplanning, standard-cell placement, CTS, GRT, and DRT.WNS, TNS, and power were recorded at each stage; area was excluded because it remained constant per circuit.
  • Correlation analysis: Table 1 reports Spearman ρ_WNS against post-route ground truth, with WNS and TNS showing the same pattern.Only WNS is reported in the table.
  • Correlation analysis: Post-GRT reaches ρ≥0.78 on all ten circuits with no sign reversals, averaging ρ=0.86 at 0.20 hours per sample.Full DRT costs 3.7 hours per sample on average.

5 PPAPlace

PPAPlace uses post-GRT supervision and a differentiable dual-stream surrogate to model PPA from complete mixed-size placements. Its gradients guide placement through co-optimization or post-placement refinement.

  • Architecture and deployment: PPAPlace trains a differentiable PPA predictor on post-GRT labels from complete mixed-size placement states.The system includes differentiable feature extraction and two gradient-guided deployment modes.
  • Placement representation: The spatial representation rasterizes placement into a 64 × 64 grid containing density, pin, macro-occupancy, and routing-pressure channels.These normalized channels capture spatial patterns such as congestion hotspots and density imbalances.
  • Placement representation: The graph representation models macro connectivity from the netlist and attaches normalized position, geometry, aspect-ratio, pin-count, net-degree, and net-span features to each node.Clique-expanded edges are weighted by the number of shared nets between macro pairs.
  • Dual-stream predictor: Separate CNN and GAT streams encode spatial and graph representations, then fuse fixed-size embeddings to predict WNS, TNS, power, and area.The architecture produces 512-dimensional combined embeddings across circuits of different sizes.
  • Training objective: The composite training loss combines mean squared error with a pairwise ranking loss that directly optimizes within-circuit placement ordering.The ranking loss uses z-score-normalized metrics and compares placement pairs from the same circuit.
  • Gradient-guided deployment: End-to-end differentiation provides timing gradients with respect to cell positions, enabling co-objective optimization in DREAMPlace and post-placement gradient refinement.CoOpt adds predicted WNS and TNS to wirelength and density, while Refine adjusts a converged placement.

6 Experiments and Results

Experiments evaluate PPAPlace on held-out ChiPBench circuits using the OpenROAD flow and compare configurations against the Hier-RTLMP reference. The study also reports training-data scope, computational cost, and a placement-dependent limitation of the fidelity analysis.

  • Experimental setup: The evaluation uses five held-out ChiPBench circuits, including three in-family and two out-of-family designs, with WNS, TNS, power, and area measured after the full OpenROAD flow.The circuits use the Nangate45 library and the same Hier-RTLMP normalization as LaMPlace.
  • Experimental setup: Each training circuit samples 1,000 DREAMPlace configurations by randomizing ten placement hyperparameters, with approximately 65% converging in DREAMPlace.The sampled parameters include density, learning rate, wirelength model, iteration count, macro halo, noise ratio, and random seed.
  • Limitation: The label-fidelity study uses RTLMP placements whereas predictor training uses DREAMPlace placements, so it does not establish placer-independent predictor accuracy.Repeating the stage study on DREAMPlace placements remains future work.
  • Compared configurations: PPAPlace uses one shared surrogate across configurations, with Refine applying 30 projected-gradient steps and CoOpt adding the surrogate after 200 warmup iterations.CoOpt linearly ramps its surrogate weight to 0.01, and CoOpt+Refine applies refinement after co-optimization.
  • Computational cost: Post-GRT label generation averages 0.2 h per sample, the 5,000-label pipeline takes approximately 63 h elapsed, and model training takes approximately 45 min.The offline cost is amortized because the same dataset and model serve downstream experiments.

6.2 Main Results

PPAPlace improves post-route timing over prior methods and the hierarchical baseline while maintaining routability and near-constant power.

  • DREAMPlace achieves the lowest HPWL but the worst post-route timing, with average WNS of 1.61×.This result confirms the reported disconnection between HPWL and post-route PPA.
  • PPAPlace-CoOpt achieves average WNS of 0.83 and TNS of 0.57, outperforming DREAMPlace 4.0.The post-route-supervised co-objective improves timing relative to pre-route STA weighting.
  • 22% WNS and 51% TNS improvements are achieved overall by CoOpt+Refine over the hierarchical baseline.The overall WNS/TNS ratios are 0.78/0.49, respectively.
  • PPAPlace improves consistently across all test circuits and achieves the best average on both WNS and TNS.It achieves the best per-circuit result on 6 of 10 circuit–metric pairs and is second-best on most remaining pairs.

6.3 Gradient Quality

The surrogate gradients align positively with true post-GRT timing changes and can guide refinement, although extended optimization eventually leaves the training distribution.

  • Average cosine similarity between surrogate and true gradients is 0.53 for WNS and 0.46 for TNS.Similarity is positive on all circuits, based on 100 random perturbation directions per circuit.
  • Gradient descent reduces true post-GRT WNS from 0.82 to 0.76 over 20 refinement steps on swerv_wrapper.The surrogate closely tracks the true WNS during refinement.
  • Beyond step 22, true WNS rises as refinement exits the training distribution.The loop returns the checkpoint with the lowest surrogate loss to mitigate moderate overshoot.
  • The best swerv_wrapper refinement setting uses T=30 steps, while T=50 is slightly worse.The corresponding WNS values for T={10,20,30,50} are {0.79,0.77,0.76,0.77}.

6.4 Generalization

PPAPlace generalizes across held-out placements, circuits, placers, and a different library, with accuracy highest within the training placer distribution.

  • Average held-out-placement ranking reaches Spearman ρ=0.77, Kendall τ=0.58, and 68% top-5 accuracy.These results are measured on 500 held-out DREAMPlace placements per circuit, versus 1% top-5 accuracy for random selection.
  • Ariane circuits absent from training reach WNS ρ values of 0.81 and 0.72.The lower value on ariane136 marks the weaker of the two unseen-family results.
  • LOCO cross-circuit Kendall τ ranges from 0.07 on isa_npu to 0.28 on mor1kx.The reported range is sufficient to identify above-average placements.
  • The combined GAT+CNN predictor reaches Kendall τ=0.31, exceeding macro-only, CNN-only, and GAT-only variants.The component streams provide complementary density-pattern and netlist-connectivity information.
  • Cross-placer transfer to unseen RTLMP placements lowers WNS Spearman ρ to 0.61 from 0.77 on DREAMPlace placements.The drop indicates a placement-distribution gap rather than placer independence.
  • On zero-shot Superblue placements, WNS/TNS Spearman ρ is 0.68/0.62 with 56% top-5 accuracy.Against LaMPlace, PPAPlace ranks second in WNS and first on Superblue16 TNS.

6.5 Ablation Studies

The ablation shows that both supervision stage and placement representation affect ranking fidelity, with post-GRT labels and GAT+CNN jointly achieving the strongest agreement.

  • Label Fidelity and Representation: 0.31 Kendall’s τ is achieved by combining post-GRT supervision with GAT+CNN, exceeding settings that change only one factor.Post-GRT raises macro-only τ from 0.08 to 0.18, while GAT+CNN raises pre-route τ from 0.08 to 0.13.
  • Label Fidelity and Representation: Table 6 reports Kendall’s τ and WNS across label stages and representations, with upper and lower sections separating the two ablations.The upper section crosses two stages with two representations; the lower section fixes GAT+CNN while varying label stage.
  • Label Fidelity and Representation: 0.31 Kendall’s τ with GAT+CNN exceeds 0.13 from pre-route STA and 0.16 from post-CTS.The comparison isolates supervision stage while keeping the representation fixed.
  • Label Fidelity and Representation: 3.7 hours per post-DRT label versus 0.20 hours per post-GRT label favors post-GRT under a fixed offline budget.Post-DRT reaches τ=0.34, but its label cost is substantially higher.
  • Label Fidelity and Representation: 0.31 Kendall’s τ for GAT+CNN exceeds macro-only polynomial and GAT-only at 0.18 and CNN-only at 0.22.The combined model uses complementary density-pattern and netlist-connectivity information.

7 Conclusion

PPAPlace provides differentiable post-GRT timing feedback for placement optimization and refinement. On held-out circuits, CoOpt+Refine improves timing over the hierarchical baseline, while broader robustness and deployment remain open challenges.

  • Conclusion: 22% and 51% improvements in average WNS and TNS over Hier-RTLMP are achieved on five held-out circuits.The result uses CoOpt+Refine on circuits excluded from training.
  • Conclusion: PPAPlace uses a post-GRT-trained differentiable surrogate to provide gradient-based PPA feedback unavailable from analytical proxies.The conclusion links the surrogate’s post-GRT training to its gradient-based placement feedback.
  • Conclusion: Training on Nangate45 and zero-shot testing on the IBM 45 nm library leave broader technology-node and standard-cell-library validation unresolved.The paper identifies broader validation as a future direction.
  • Conclusion: Cross-placer transfer reaches ρ=0.61 versus within-placer accuracy of 0.77, indicating a remaining transfer gap.The paper suggests targeted fine-tuning or domain adaptation as possible ways to narrow it.
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