PaperlayerView exact revision on arXiv

Source-linked AI summary

Hybrid ML for Lightweight Pre-Route Delay Estimation in Open-Source IC Design

Marvin Castro Castro, Erick Carvajal Barboza

arXiv:2608.17914v1cs.LG

TL;DR

Early-stage delay estimation is difficult when physical-design information is limited. This paper combines decision trees with linear regression for lightweight pre-route prediction, reducing error by up to 65% versus OpenLane across evaluated circuits.

  • Problem

    Accurate early delay estimation remains difficult, while STA pessimism and late timing violations can drive inefficient iterative design refinement.

  • Method

    The approach combines a decision tree with localized linear regression to predict path-segment delays from pre-routing logical and physical features.

  • Results

    The hybrid model reduces error by up to 65% compared to OpenLane across all circuits.

  • Takeaways & Limitations

    The model offers a lightweight, computationally efficient, and explainable alternative for earlier delay analysis and optimization support.

  • Takeaways & Limitations

    Linear regression assumes global linearity, making it less suited to complex, highly nonlinear pre-route timing data.

Abstract

from arXiv · show

Static Timing Analysis (STA) is a critical step in the design flow of digital integrated circuits, however, obtaining accurate delay estimations can represent a challenge when limited information regarding physical design is available. In response, this work presents a hybrid and light-weight machine learning (ML) based approach that combines a decision tree with linear regression to improve pre-routing delay estimations generated by the open-source RTL-to-GDSII tool OpenLane. The proposed model achieves an 80\% reduction in error compared to OpenLane's estimates, demonstrates a 71\% improvement even without utilizing OpenLane-specific parameters. Overall, this method offers an alternative to traditional delay propagation techniques and more complex machine learning models that is not only accurate, but is also over 300 times smaller, 2 times faster and offers a higher explainability.

I. INTRODUCTION

Pre-routing delay estimation is difficult because limited physical information and conservative STA assumptions create discrepancies that drive repeated design iterations. The work proposes a hybrid, explainable model combining decision trees and linear regression to improve early path-segment delay prediction.

  • Motivation: Repeated timing violations and discrepancies between early estimates and post-layout results make VLSI design inefficient by requiring multiple re-optimization cycles.These iterations occur even when designers follow best practices during synthesis and placement.
  • Motivation: Pre-routing delay estimation is challenging because limited layout information and unavailable interconnect parasitics cause early estimates to diverge from post-route values.This divergence hinders accurate optimization before routing.
  • Motivation: Timing-graph STA algorithms are scalable and fast, but insufficient physical information before routing or detailed placement impairs prediction accuracy.These algorithms propagate delays along paths between startpoints and endpoints.
  • Proposed approach: The proposed hybrid model predicts path-segment delays, including gate and wire components, by integrating a decision tree with linear regression.The two algorithms are described as simple and explainable, with decision trees accommodating heterogeneous distributions and non-linear behavior.
  • Proposed approach: Combining both models partitions data into homogeneous regions where linear regression can operate under a more reasonable local-linearity assumption.This structure leverages decision-tree partitioning while mitigating linear regression’s weakness on complex, highly non-linear pre-route timing data.

II. RELATED PREVIOUS WORK

Prior work has increasingly used data-driven models for STA delay prediction, including Random Forests and neural networks, but these approaches face tradeoffs in explainability, data requirements, and deployment environments. This motivates lightweight, interpretable hybrid models for timing prediction within open-source frameworks such as OpenLane.

  • Learning-Based STA Prediction: Data-driven techniques have become an attractive alternative for improving STA delay-prediction accuracy as traditional analytical models struggle with increasingly complex circuit interactions.The cited work frames the challenge in terms of logical, electrical, and physical features.
  • Prior Machine Learning Models: Random Forest pre-routing models have produced reliable post-route timing estimates from limited physical information by learning statistical correlations from previous designs.Carvajal et al. compared their predictions against a commercial STA tool and reported reduced pessimism.
  • Neural-Network Approaches: Neural-network models, including MLPs, capture complex non-linear timing dependencies and can improve accuracy, but often reduce explainability and require more training data.These limitations may hinder practical adoption where transparency and runtime efficiency are important.
  • Open-Source EDA: Open-source EDA research has applied Machine Learning to improve delay estimates produced by OpenLane, supporting reproducibility, accessibility, and community-driven innovation.The cited examples include work using Random Forest and Gradient Boosted Decision approaches.
  • Research Gap: No prior work identified by the authors had used a comparable decision-tree and leaf-level linear-regression hybrid for timing prediction or circuit design.Hybrid models of this structure had been explored successfully in other domains, but their application to electronic design automation remained largely unexplored.
  • Motivation: Existing ensemble and neural approaches motivate lightweight, transparent, interpretable alternatives that can operate effectively within open-source frameworks like OpenLane.The intended alternative preserves designers’ expected insight and control while addressing limitations of prior approaches.

III. METHODOLOGY · A. Machine Learning Model Structure

The model estimates individual-net delay from pre-routing features of driver and sink gates, with additional sinks providing context. It combines decision-tree routing with a separate linear-regression model at each leaf for final prediction.

  • A. Machine Learning Model Structure: The model predicts delay for individual nets using pre-routing information by analyzing each net’s driver and sink gates individually.For a path to sink e on Net C, features come from driver gate C0 and sink gate C1.
  • A. Machine Learning Model Structure: Capacitance, slew, and location information are obtained from the driver and sink gates for each analyzed path.The capacitance and location of both gates are considered.
  • A. Machine Learning Model Structure: Additional sinks are incorporated as context when estimating delay to a target sink.For sink e, additional sinks f and g are included in the estimation context.
  • A. Machine Learning Model Structure: The model architecture resembles a traditional decision tree, but each leaf node is linked to its own linear regression model.Unlike a single constant value at each leaf, the architecture assigns a separate regression model.
  • A. Machine Learning Model Structure: The decision tree determines the leaf node corresponding to each new data sample during prediction.Prediction begins by traversing the constructed tree for each sample.
  • A. Machine Learning Model Structure: After tree traversal, the assigned linear regression model estimates the sample’s delay.The regression model associated with the selected leaf produces the final delay estimate.

B. Model Features

The model predicts path-segment delay from logical and physical features, including driver and sink capacitance, slew, and distance. It also incorporates context-related parameters to capture effects from gates and paths outside the target path.

  • Core features: The model uses each path segment’s logical and physical characteristics, including driver and sink capacitance, slew, and distance, as prediction features.Context-related parameters account for gates outside the path that may influence delay.
  • Core features: Higher fanout increases load capacitance, which directly affects signal propagation delay.
  • Core features: Higher slew rate correlates with increased propagation delay because signal transition time is influenced by load capacitance.
  • Core features: Driver-to-sink distance reflects wire length, which is proportional to the target delay variable.
  • Context features: Context-sink locations capture routing effects because additional paths increase routing utilization, load capacitance, and slew, resulting in higher delay.The median context-sink location approximates average driver-to-context-sink distance, while its standard deviation measures spatial spread.

C. Data generation

The dataset combines pre-routing features and reports with signoff timing labels generated through OpenLane on the SkyWater 130 nm PDK. It is partitioned into train, variations, and unseen datasets to distinguish training designs, altered variants, and independent designs.

  • Data sources: Pre-routing stages provide features, while OpenLane signoff timing reports provide labels and pre-routing reports add driver and sink locations.Data collection uses placement and related pre-routing information before signoff timing reports supply the labels.
  • Data sources: The data-generation flow runs RTL-to-GDSII designs from benchmark circuits in OpenLane using the SkyWater 130 nm Technology PDK.Benchmark sources include ISCAS-89 and OpenCores, as stated in the passage.
  • Dataset partitioning: The data is divided into train, variations, and unseen datasets with relationships illustrated in Figure 3.The passage identifies train as the largest dataset, although the supplied text truncates its complete description.
  • Dataset partitioning: The variations dataset uses different variations of circuits s38417 and s15850, while the unseen dataset contains independent designs zipdiv and picorv32.The unseen designs and their variations are independent of the train and variations datasets.

D. Model Training and Selection

The hybrid model was selected by training and evaluating numerous parameter configurations on the training data. The configurations varied data scaling, decision-tree hyperparameters, sink-location features, distance representation, and linear-regression type.

  • Model selection: Numerous hybrid-model instances were trained and evaluated across different permutations of parameter configurations on the training data.The selection process compared multiple parameter combinations rather than a single fixed configuration.
  • Model configuration: Data scaling configurations included standardization, min-max feature scaling, or no scaling.Standardization sets each parameter to mean zero and unit variance, while min-max scaling maps values to [0, 1].
  • Model configuration: Decision-tree settings varied maximum depth and maximum feature utilization from 5 to 15.Both hyperparameters were tested across the stated range.
  • Model configuration: The experiments varied sink-location statistics, distance representation, and linear-regressor type.Configurations optionally used median or standard-deviation sink locations, compared X/Y coordinates with Euclidean distance, and selected Ridge or OLS regression.

E. Machine Learning Algorithms

This section describes three machine learning algorithms and their corresponding cost functions: decision trees, linear regression, and ridge regression. The methods differ in how they partition features, minimize error, or regularize model weights.

  • Decision Trees: Decision trees recursively partition the feature space using feature thresholds that maximize Gini-impurity reduction, with impurity minimized at each split.The Gini cost is expressed as Σ_{k=1} p_k(1 − p_k).
  • Linear Regression: Linear regression fits y = β_0x_0 + β_1x_1 + ... + β_nx_n + ϵ by minimizing the sum of squared errors without regularization.Because all features are fitted equally, the method is sensitive to outliers.
  • Ridge Regression: Ridge regression applies L2 regularization to penalize weight sizes, helping mitigate overfitting or multicollinearity.Its cost function includes the corresponding regularization penalty.

IV. RESULTS · A. Model Selection Results · B. Delay prediction results

The results select a hybrid-model configuration that performs best across both test sets, then show that the hybrid model substantially reduces delay-prediction error relative to OpenLane across circuits. The largest reported reductions are 77% for s38417 and 80% for s15850.

  • A. Model Selection Results: The optimal configurations include the smallest RMSE on the unseen dataset, the smallest variations-dataset RMSE, and the smallest combined error across both datasets.The third row represents the configuration with the smallest combined error for both datasets.
  • B. Delay prediction results: The selected third-row configuration uses no data scaling and no context features because it provided the best outcomes for both test sets.Results in the delay-prediction section use this configuration.
  • B. Delay prediction results: 65%: the hybrid model reduces error by up to 65% compared to OpenLane across all circuits.This average comparison covers the testing pool across all circuits.
  • B. Delay prediction results: 77%: error reduction for s38417 compared to OpenLane.The third circuit is identified as achieving a significantly lower error rate with the hybrid model.
  • B. Delay prediction results: 80%: error reduction for s15850 compared to OpenLane.The fourth circuit is identified as achieving a significantly lower error rate with the hybrid model.
  • B. Delay prediction results: The stronger results for s38417 and s15850 may be attributed to their increased similarity to the training data.This attribution is presented as a possible explanation for the lower error rates on those circuits.

C. Delay prediction and model comparison

The hybrid model is compared with prior Random Forest and delta-prediction approaches across four circuits, performing strongly when OpenLane estimates are included and reducing error overall. Without OpenLane estimates, the delta-based model remains best overall, although the hybrid model outperforms it on zipdiv.

  • Comparison with prior work: Prior studies use Random Forest models or predict the difference between OpenLane pre-route and signoff delay.The latter approach is categorized as delta prediction.
  • Model comparison: With OpenLane pre-route delay as an input, the hybrid model has the highest accuracy on unseen picorv32 and zipdiv, the lowest error on s38417, and near-best error on s15850.The unseen dataset comprises picorv32 and zipdiv.
  • Model comparison: Without OpenLane pre-route delay as an input, the delta-based model remains best overall, while the hybrid model performs better on zipdiv.
  • Overall performance: 28% maximum RMSE reduction and 21.76% average reduction distinguish the hybrid model, which has lower error in 3 of 4 circuits than the delay estimates from.On s15850, the hybrid model has 25.7% higher error than the best-performing model.

V. CONCLUSION

The conclusion presents the hybrid decision-tree/linear-regression model as a lightweight, efficient, interpretable approach that improves delay prediction compared with OpenLane and similar standalone ML methods. It also identifies broader datasets and design conditions as priorities for evaluating and improving generalization.

  • Contribution: The work presents the first unified hybrid model combining decision trees and linear regression for integrated-circuit delay prediction.The authors characterize the model as lightweight, computationally efficient, and improved across several delay-prediction scenarios.
  • Contribution: The hybrid structure partitions feature space and applies localized regressions, improving interpolation while preserving explainability against OpenLane and standalone ML approaches.This structure is intended to help design engineers understand and trust automated predictions.
  • Interpretability: Each prediction is explained by its tree-decision sequence and the linear formula applied at the corresponding leaf.This transparency supports debugging, model validation, and analysis of which design features drive delay variations.
  • Future Work: A broader dataset spanning more circuits, process nodes, and design conditions is identified as a priority for improving generalization and evaluating performance limits.The current dataset is described as sufficient to demonstrate feasibility but limited for comprehensive evaluation.
Loading 2608.17914v1…