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A high-isolation wideband channelizer for MKID readouts: a custom HLS implementation on RFSoC

Alberto Hernandez Fernandez, David Diaz Martin, Jose Javier Diaz Garcia, Roger John Hoyland, Luis Fernando Rodriguez Ramos, Diego Portero Rodriguez, Silvestre Rodriguez Perez

arXiv:2608.24459v1astro-ph.IMeess.SP

TL;DR

Wideband MKID readouts need channelizers that preserve isolation and flatness while processing very high-rate streams. This paper uses parallel overlapping polyphase branches and frame-level reordering on an RFSoC, achieving below 0.1 dB scalloping loss across the full 2 MHz channel with approximately 80 dB out-of-band isolation.

  • Problem

    Implementing 16-tap, 4096-channel overlapping reordering at a 4.096 GSPS throughput is a central challenge for high-isolation MKID readout channelizers.

  • Method

    The channelizer computes delayed and non-delayed 16-tap polyphase branches in parallel and uses frame-level reordering to keep most processing at 256 MHz.

  • Results

    Below 0.1 dB scalloping loss across the full 2 MHz channel and approximately 80 dB out-of-band isolation were measured for the overlapped channelizer.

  • Takeaways & Limitations

    Architectural parallelism enables a deeper, higher-isolation wideband channelizer while avoiding aggressive clocking across most of the design.

  • Takeaways & Limitations

    HLS state toggles can be silently skewed across pipeline stages, requiring explicit handling to preserve correct overlap-state and buffer alignment.

Abstract

from arXiv · show

We present a high-performance channelizer for Microwave Kinetic Inductance Detectors (MKIDs), designed to mitigate spectral leakage and scalloping loss through a 50% overlapping polyphase filter bank (PFB). The design is implemented on a Xilinx Zynq UltraScale+ RFSoC ZCU111 using a custom design - primarily in Vitis High-Level Synthesis (HLS), with the time-critical output serializer and glue logic in VHDL - that processes a 4.096 GSPS input stream with a per-branch super-sample rate (SSR) of 16. Rather than relying on aggressive 512 MHz clocking and vendor IP cores, our split-path architecture computes the delayed and non-delayed polyphase branches concurrently, so that the bulk of the channelizer operates at a robust 256 MHz while a single 512 MHz subdomain is confined to the BRAM-to-FFT section. This architectural parallelism enables a deep 16-tap prototype filter that doubles the filter depth of comparable high-speed systems and substantially improves channel isolation. We report the complete internal architecture of the reordering engine that implements the overlap, including two implementation hazards not documented in prior art: a pipeline-stage skew affecting state toggles in HLS, and the state-preservation requirements of a restartable design. The 2/1 overlapped channel response is validated in simulation - recovering the ~3.9 dB scalloping loss of a critically sampled channelizer to below 0.1 dB across the full 2 MHz channel - and characterized systematically with a 100-tone batch frequency sweep, while the parent readout system has been operated cryogenically with an MKID array in an adiabatic demagnetization refrigerator (ADR), identifying individual resonators in total darkness. The result is a resource-efficient, high-isolation benchmark for wideband frequency-division-multiplexed readouts.

1 Introduction

MKID frequency-division multiplexing depends on a digital backend whose channelizer efficiently separates wideband signals into individual resonator channels. This work presents an oversampled RFSoC channelizer that uses architectural parallelism and a custom HLS implementation to improve isolation while avoiding pervasive aggressive clocking.

  • Application context: MKID arrays have demonstrated 10^3–10^4 pixels on sky, making backend channelization a key determinant of multiplexing performance.Examples include ARCONS, DARKNESS, and the MKID Exoplanet Camera.
  • Motivation: The channelizer is central to MKID readouts, while direct independent filtering scales as O(M^2) and PFB-FFT channelization reduces this to O(M log M).A critically sampled PFB nevertheless motivates oversampling to address channel-response limitations.
  • Motivation: Existing oversampled RFSoC designs use aggressive 512 MHz clocking and phase time-multiplexing, limiting prototype filters to typically 8 taps.These design choices reduce hardware size but constrain filter depth.
  • Contribution: The proposed channelizer processes 4.096 GSPS with per-branch SSR 16, keeps most of the pipeline at 256 MHz, and is built primarily in Vitis HLS with a VHDL output serializer.Its architecture prioritizes parallelism over raw clock speed and avoids reliance on vendor-specific IP cores.
  • Novelty: The paper fully discloses the reordering engine, including HLS pipeline-stage skew that desynchronizes state toggles and selective state preservation for restartable operation.These implementation hazards are identified as not documented in prior literature.

2 MKID Readout and Frequency-Division Multiplexing

MKID arrays use superconducting LC resonators whose photon-induced kinetic-inductance changes shift resonance frequency. Frequency-division multiplexing interrogates distinct resonators simultaneously with a frequency comb and requires digital synthesis, DAC playback, ADC digitization, and channelization.

  • MKID Readout: An MKID is a lithographed superconducting LC resonator capacitively coupled to a common feedline.Below the critical temperature, Cooper-pair inertia produces kinetic inductance.
  • MKID Readout: A photon exceeding twice the superconducting gap breaks Cooper pairs into quasiparticles, increasing kinetic inductance and lowering the resonant frequency.The resulting change in quasiparticle density also modifies the internal quality factor.
  • Frequency-Division Multiplexing: Distinct resonator frequencies allow the whole array to be interrogated simultaneously by driving a common feedline with one tone per resonator.The readout recovers the amplitude and phase imprinted by each resonator; this is frequency-division multiplexing.
  • Frequency-Division Multiplexing: The digital backend must synthesize a programmable comb, play it through a DAC, digitize the return with an ADC, and channelize the wideband stream.These operations support multiplexed interrogation and recovery of per-tone resonator information.

3 Polyphase Channelization and the Overlap Technique

The channelizer uses polyphase decomposition and FFT combination to reduce computation, while 50% overlap addresses scalloping loss through output reordering and interleaved FFT inputs. A 16-tap Blackman prototype improves isolation over shallower designs, with simulated flat coverage across the 2 MHz channel.

  • Polyphase Channelization: Polyphase decomposition partitions a length-K·M prototype into M sub-filters, whose outputs are combined by an M-point FFT instead of independent down-converting FIR filters.This reduces the independent-filter cost of O(M^2) multiplications per input sample to one FFT.
  • Implementation Parameters: The implementation uses M = 4096 channels, K = 16 taps per polyphase path, SSR = 16, and approximately 1 MHz channel spacing.The prototype contains K·M = 65,536 coefficients and has an approximately 2 MHz passband.
  • Overlap Technique: ≈3.9 dB scalloping loss in the critically sampled case is reduced to below 0.1 dB with the 2/1 overlapped PFB across the 2 MHz channel.The overlapped response provides flat coverage at 1 MHz channel spacing.
  • Overlap Technique: 50% overlap requires cyclic reordering of polyphase outputs and two interleaved LOWER and UPPER sub-bands before the FFT.Implementing this reordering at 4.096 GSPS with 4096 channels and a 16-tap prototype is the core implementation challenge.
  • Prototype Filter: 16 taps provide a sharper transition and deeper stop-band than the 8-tap design, reaching roughly 15 dB deeper at the first adjacent channel.The deeper Blackman prototype is intended to suppress crosstalk in a dense MKID array.

4 Architecture and HLS Implementation · 4.1 Throughput, Super-Sample Rate and Clocking · 4.2 Split-Path Polyphase Topology

The channelizer sustains the 4096 MSPS converter stream with SSR = 16 at 256 MHz, using parallel delayed and non-delayed 16-tap polyphase branches. A 512 MHz read domain is confined to BRAM and FFT serialization after frame-level alternation and clock-domain crossing.

  • 4.1 Throughput, Super-Sample Rate and Clocking: 4096 MSPS converter output requires parallel processing in SSR-sized words to avoid dropping samples.The RFSoC fabric sustains roughly 200–500 MHz for complex DSP designs.
  • 4.1 Throughput, Super-Sample Rate and Clocking: SSR = 16 at 256 MHz is the selected operating point for every parameterized DSP block.SSR = 8 would force 512 MHz throughout the receive chain, while SSR = 32 would exceed routing resources.
  • 4.1 Throughput, Super-Sample Rate and Clocking: The operating readout system currently runs its entire processing chain in a single 256 MHz clock domain.
  • 4.2 Split-Path Polyphase Topology: Two physically parallel FIR branches compute the overlapping PFB’s delayed and non-delayed results, each using a 16-tap, SSR = 16 Blackman polyphase bank.Together, the branches deliver 32 aggregated samples per 256 MHz cycle to the reordering stage.
  • 4.2 Split-Path Polyphase Topology: Dedicated HLS switch modules assemble each branch’s polyphase frames by buffering the SSR-16 stream in BRAM and presenting K = 16 time-aligned samples per lane.The delayed switch uses the same structure with an offset read schedule.
  • 4.2 Split-Path Polyphase Topology: In the 256 MHz write domain, the branches feed an HLS order block with II = 1 that performs frame-level alternation.
  • 4.2 Split-Path Polyphase Topology: A clock-domain crossing transfers reordered data to the 512 MHz read domain, where ping-pong BRAMs and the done module serialize frames into the SSR-16, 4096-point FFT.

4.3 Frame-Level Reordering · 4.4 Pipeline-Stage Skew in HLS State Toggles

The channelizer adopts frame-level rather than sample-level reordering to preserve timing closure at SSR = 16, using split HLS/VHDL modules and ping-pong BRAM buffering. This implementation also exposes an HLS hazard in which adjacent state toggles can be scheduled into different pipeline stages, requiring explicit atomic updates and cycle-by-cycle waveform verification.

  • 4.3 Frame-Level Reordering: Frame-level reordering alternates whole-frame destinations for the delayed and non-delayed branches instead of interleaving samples within each FFT word.The adopted granularity is presented as the key pre-FFT reordering decision.
  • 4.3 Frame-Level Reordering: SSR = 16 and two parallel branches make sample-level mux-select-write interleaving exceed one 256 MHz cycle and break the HLS pipeline’s II = 1.The comparison cites Smith’s SSR = 8 design as feasible for sample-level reordering.
  • 4.3 Frame-Level Reordering: The order block writes branch outputs into four BRAMs at 256 MHz, while the done block reads them at 512 MHz and alternates LOWER and UPPER sub-bands.The done block uses 256 read beats per frame to deliver 16 samples per cycle to the FFT core.
  • 4.3 Frame-Level Reordering: Ping-pong buffering writes one BRAM pair while reading the other, swaps at frame boundaries, and crosses only buffer toggle and buffer ready through synchronizers.The design prevents read/write collisions by construction.
  • 4.3 Frame-Level Reordering: The order module truncates each 36-bit filter sample to 32 bits, packs sixteen samples into one 512-bit BRAM word, and synthesizes as II = 1.The truncation discards four least-significant bits below the 16-tap filter’s quantization noise floor; the kernel uses roughly one thousand registers and one thousand LUTs.
  • 4.4 Pipeline-Stage Skew in HLS State Toggles: Vitis HLS can schedule adjacent ping pong and frame state toggles into different pipeline stages, creating a one-cycle control-state skew.The hazard occurs despite the assignments being adjacent in the source-level if block.
  • 4.4 Pipeline-Stage Skew in HLS State Toggles: Grouping all frame-boundary toggles into one unified update expression forces atomic scheduling, while correctness requires cycle-by-cycle control-waveform inspection.Output data alone can mask a one-cycle skew.

4.5 Selective Soft Reset and Restart Alignment · 4.6 Two Clock Domains and the Bounded 512 MHz Subdomain

The design preserves restart alignment through a selective soft reset and confines the demanding reorder-to-FFT path to a bounded 512 MHz subdomain. This partition keeps the main OPFB at 256 MHz while avoiding the timing and fit problems of operating the complete M = 4096, 16-tap design at 512 MHz.

  • 4.5 Selective Soft Reset and Restart Alignment: Selective soft reset clears only first frame done while preserving write ptr, ping pong, and frame state across acquisition stops.This preserves phase lock between the reorder engine and datapath during restart.
  • 4.5 Selective Soft Reset and Restart Alignment: Clearing first frame done ensures the first post-restart output is a complete, well-formed frame rather than an interrupted frame tail.The policy avoids restarting the reorder permutation at an arbitrary phase relative to the switch modules’ circular buffers.
  • 4.6 Two Clock Domains and the Bounded 512 MHz Subdomain: 512 MHz is required for SSR = 16 if the reorder stage delivers the alternating LOWER/UPPER sequence at 16 samples per cycle.The relation given is fclk · SSR = 2fs, implying fclk = 512 MHz for SSR = 16.
  • 4.6 Two Clock Domains and the Bounded 512 MHz Subdomain: The main zone combines two FIR branches and the order block at 256 MHz with 32 aggregated samples per cycle.The split architecture leaves the resource-heavy DSP48, BRAM, and routing portion in the lower-frequency domain.
  • 4.6 Two Clock Domains and the Bounded 512 MHz Subdomain: Ping-pong BRAMs carry the data across clock domains, with ownership exchanged only at frame boundaries through buffer toggle and buffer ready controls.Each control uses double-flop synchronization, while released-buffer selection prevents simultaneous read/write access to the same BRAM address.
  • 4.6 Two Clock Domains and the Bounded 512 MHz Subdomain: M = 4096 with 16 taps cannot close timing on the ZCU111 when the complete chain is raised to 512 MHz.The design instead confines the higher clock rate to the necessary subdomain rather than adding extensive pipelining that would prevent fitting.

4.7 Resource Utilization and Timing · 4.8 Channelized Output

The OPFB front-end meets target timing with its main resource cost concentrated in the two polyphase banks, while the functional system maintains sub-3 µs deterministic digital latency. Its channelized output comprises 4096 channels with 1 MHz spacing and 2 MHz flat-top bandwidth, represented as separate 27-bit real and imaginary components.

  • 4.7 Resource Utilization and Timing: 512 DSP slices comprise the two polyphase banks, using 12% of the 4272 available DSP48E2 slices.Each polyphase bank uses 256 DSP48E2 slices; this resource cost instantiates the second overlap state in space.
  • 4.7 Resource Utilization and Timing: All custom HLS modules are fully pipelined at their target clocks with positive slack.The post-synthesis estimates target the ZCU111 XCZU28DR-2 device.
  • 4.7 Resource Utilization and Timing: The implementation uses Vivado 2022.1, Vitis HLS 2022.1, Vivado Model Composer, and PYNQ-based embedded software.The FFT core is generated in Vivado Model Composer, while the embedded software runs on PYNQ.
  • 4.7 Resource Utilization and Timing: Below ∼3 µs is the deterministic digital latency from ADC to the 10 GbE interface in the functional system.Cables, mixers, and the cryostat add a few microseconds of analog latency, measured with a reference calibration pulse.
  • 4.8 Channelized Output: 4096 channels provide 1 MHz spacing and 2 MHz flat-top bandwidth after the FFT.The channel bank is delivered as separate real and imaginary components.
  • 4.8 Channelized Output: 27-bit fixed-point real and imaginary components form the channelized output word.The serializer extracts the 18 most significant bits of each stored 32-bit sample as the FFT input word, and the FFT grows it to 27 bits.

5 Results

The overlapped channelizer was validated in a cycle-accurate Xsim testbench reproducing the polyphase, reorder, and FFT chain. Tone sweeps and a 100-simulation batch campaign confirmed flat 50%-overlapping passbands, symmetric adjacent-channel response, and ≈80 dB stop-band suppression, while the parent readout system operated with a cryogenic MKID array.

  • 5.1 Channel response: The cycle-accurate Xsim testbench reproduced the complete polyphase, reorder, and FFT chain, including hardware reorder order and done modules.The overlapped channelizer is intended to replace the deployed system’s classic non-overlapped PFB.
  • 5.1 Channel response: ≈80 dB stop-band suppression was measured below channel peaks, with adjacent channels forming flat 50%-overlapping passbands across the band.The response was obtained from hardware reorder data during a tone sweep at fs = 4.096 GSPS with NFFT = 4096.
  • 5.1 Channel response: 100 independent Xsim simulations characterized one tone at a time across the band, isolating each excitation from neighboring intermodulation and leakage.The single-tone campaign kept waveform databases small enough for automated cycle-level inspection.
  • 5.1 Channel response: 90.3 dB response was recovered in channel 20 for a centered tone, while adjacent channels responded at 84.3 dB, exactly 6.0 dB lower.The adjacent-channel response was symmetric on both sides within the measurement precision.
  • 5.2 Cryogenic system operation: The parent eDAS17 readout system operated on an MKID array at ≈100 mK in an ADR, with 80 dB transmit attenuation and about −90 dBm device drive power.The setup included a HEMT amplifier at 4 K and exercised the RF–digital–RF loop under conditions for future overlapped-channelizer deployment.

6 Comparison with the State of the Art

The design occupies a distinct state-of-the-art niche as a 16-tap, M = 4096 channelizer on a single RFSoC at 4.096 GSPS, using frame-level reordering. Compared with the UCSB sample-level design, it trades greater spatial replication and control complexity for lower clocking pressure and deeper filtering.

  • Present design’s niche: 16 taps, M = 4096, and 4.096 GSPS make this, to the authors’ knowledge, the deepest oversampled channelizer implemented on a single RFSoC.The design is also the only cited implementation built around frame-level reordering.
  • Comparison with UCSB: The UCSB comparison implements the same 2/1 OPFB function with a sample-level design that uses one physical filter, half the channels, and half the taps.This minimizes silicon area relative to the present architecture.
  • Methodological commonality: Both designs are written primarily in C++ for Vivado/Vitis HLS and operated through PYNQ, keeping their sources parametric and maintainable by a small team.The same IAC design targets the ZCU208 at higher sample rates by regenerating with different SSR and clock constraints.
  • Architectural tradeoff: 512 MHz timing forces the UCSB design’s time-multiplexed filter to use a shallow prototype, whereas spatial filter replication lets the IAC design operate at 256 MHz.The IAC design retains a single 512 MHz VHDL serialization module and reports HLS-specific control hazards.

7 Conclusions

The paper presents a high-isolation wideband MKID channelizer on RFSoC, using architectural parallelism and custom HLS/VHDL implementation to achieve deeper filtering without aggressive clocking. Simulation and cryogenic operation validate low scalloping loss, strong isolation, and resonator identification in total darkness.

  • Architecture: Architectural parallelism enables a deeper, higher-isolation channelizer than aggressively clocked, IP-based designs of comparable bandwidth.The design computes delayed and non-delayed polyphase branches in parallel on a Xilinx Zynq UltraScale+ RFSoC ZCU111, primarily using Vitis HLS with the time-critical serializer in VHDL.
  • Validation: Below 0.1 dB scalloping loss is achieved across the full 2 MHz channel, recovering the approximately 3.9 dB loss of a critically sampled channelizer.The result is reported for the 2/1 overlapped channelizer in simulation.
  • Validation: Approximately 80 dB out-of-band isolation is confirmed by a 100-tone batch sweep, with symmetric adjacent-channel responses at the designed −6 dB crossover.The sweep validates the channelizer’s frequency response in simulation.
  • System demonstration: Cryogenic operation of the parent readout system on a real MKID array identified individual resonators in total darkness.This exercised the complete RF–digital readout system under cryogenic conditions.

8 Future Work

Future work will deploy the overlapped channelizer in the production bitstream and validate its flat, high-isolation response on the cryogenic array. Further efforts will address multi-channel transport over 10 GbE and real-time phase processing for single-photon event detec.

  • Deployment and validation: The overlapped channelizer will replace the classic non-overlapped PFB in the deployed bitstream.This transition includes adding the auxiliary modules required by the overlapped architecture.
  • Deployment and validation: The flat, high-isolation channel response will be validated directly on the cryogenic array.
  • Further development: Future development includes full multi-channel transport over the 10 GbE link to a network-attached storage backend.
  • Further development: Real-time phase processing will be pursued for single-photon event detec.
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