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An Open-Source Benchmark Suite of 3D-IC Testcases
Rohan Soni, Jooyeon Jeong, Alexander Graening, Anthony Foo, Richard Chen, Puneet Gupta
TL;DR
Existing planar benchmarks do not capture the physical-design challenges of 3D heterogeneous integration, while publicly accessible and scalable 3D benchmark resources remain limited. The paper presents an open-source suite generated from CATCH using reusable chiplet and substrate models, providing 20 standardized 2.5D/3D designs for reproducible evaluation. The suite spans increasing architectural complexity and is intended to support comparison and extension across 3D design methodologies.
Problem
Publicly accessible, scalable benchmarks for reproducibly evaluating diverse 3D heterogeneous-integration physical-design problems remain limited.
Source: §II · p. 1, §I · p. 1Method
The paper constructs a two-phase benchmark suite from reusable CATCH-parameterized chiplet templates and composes them into graded 2.5D/3D system-in-package designs.
Source: A. Benchmark Generation Framework · p. 2, §II · p. 2, 1) (Phase 1) Chiplet Library · p. 2Results
The released suite contains 20 heterogeneous 2.5D/3D benchmark designs organized into four categories of increasing complexity and represented in standardized 3Dblox.
Source: §II · p. 2, 2) (Phase 2) Benchmark Design Suite · p. 2Takeaways & Limitations
The 3Dblox suite provides common heterogeneous structures for reproducible comparison and future benchmark extensions as integration technologies and design problems evolve.
Source: §IV · p. 2, §II · p. 2
Abstract
from arXiv · showhide
The physical design community has benefited from standardized, publicly available benchmark suites, which have enabled reproducible evaluation and driven significant advances in 2D place-and-route algorithms over the past three decades. However, the emergence of 3D heterogeneous integration technologies, including through-silicon vias (TSVs), hybrid bonding, and chiplet-based architectures, has introduced new physical design challenges that are not captured by existing planar benchmarks. Although several 3D-IC design examples have been reported, publicly accessible and scalable benchmark suites that enable reproducible evaluation across different 3D physical design problems remain limited. In this paper, we present an open-source suite of 3D-IC benchmark testcases derived from representative chiplet-based case studies in CATCH, an open-source framework for estimating the cost of heterogeneous integration architectures. The proposed benchmark suite provides reusable virtual chiplet models covering compute, memory, I/O, analog, and substrate components. Each testcase captures essential physical design characteristics of 3D systems, including heterogeneous die integration, inter-die connectivity, and technology-dependent design constraints. By publicly releasing these benchmarks, we aim to establish a common evaluation platform and accelerate community-wide research progress in 3D heterogeneous integration.
I. INTRODUCTION
Open, representative benchmarks have provided common infrastructure for reproducible 2D physical-design evaluation and algorithmic progress. Emerging 3D heterogeneous integration creates substantially different design problems that planar benchmarks do not capture.
- Open benchmark suites established common, reproducible targets that supported advances in 2D placement, routing, and optimization.Source: §I · p. 1
- The 2D physical-design experience shows that open, representative benchmarks enable fairer comparison of emerging methodologies.Source: §I · p. 1
- 3D heterogeneous integration combines stacked dies, high-density interfaces, interposers, and heterogeneous chiplets, creating problems substantially different from planar physical design.Source: §I · p. 1
II. MOTIVATION
Publicly available benchmarks for 3D heterogeneous integration remain limited and fragmented across specific studies or implementation flows. The paper addresses this gap with an open-source, reusable benchmark infrastructure spanning diverse 2.5D/3D architectures.
- Existing 3D benchmark resources are limited, specialized, or confidential, leaving no reproducible infrastructure for fair methodology comparison.Source: §II · p. 1
- Recent open-source efforts validate physical-design methodologies within particular flows but do not systematically span chiplet composition, die count, packaging, and cost-driven configurations.Source: §II · p. 1
- The paper introduces an open-source benchmark suite for heterogeneous 2.5D/3D physical design generated using the CATCH framework.Source: §II · pp. 1–2
- The infrastructure includes a reusable virtual chiplet library, automated CATCH-to-standard conversion, and 20 benchmark designs in four increasing-complexity categories.Source: §II · p. 2
- The benchmarks are released as standardized 3Dblox descriptions to support reproducible evaluation and future extensions.Source: §II · p. 2
A. Benchmark Generation Framework
Benchmark construction uses two phases: defining reusable chiplet-library elements and composing them into a graded suite of system-in-package designs. CATCH XML represents complex stack, connectivity, and substrate constraints.
Benchmark Generation Framework
- Phase 1 defines a reusable chiplet library, while Phase 2 composes its elements into a graded suite of system-in-package designs.Source: A. Benchmark Generation Framework · p. 2
- CATCH XML supports arbitrary stack hierarchies, face/back-side connectivity, TSV pass-through signaling, buried dies, and substrate-level routing constraints.Source: A. Benchmark Generation Framework · p. 2
1) (Phase 1) Chiplet Library:
The Phase 1 library defines virtual active-die and substrate templates covering pass-through interconnect, compute, memory, I/O, analog, organic, and silicon-interposer roles. Their parameters represent varied integration and packaging conditions.
1) (Phase 1) Chiplet Library:
- Five virtual active-die templates are characterized by CATCH parameters for constructing heterogeneous benchmark designs.Source: 1) (Phase 1) Chiplet Library · p. 2
- Compute Small models a CPU-core die of approximately 20 mm2, while Compute Large models a GPU or accelerator die of approximately 250 mm2.Source: 1) (Phase 1) Chiplet Library · p. 2
- Memory DRAM represents a vertically stackable approximately 50 mm2 die, and the IO Controller represents a approximately 10 mm2, high-connection-count chiplet.Source: 1) (Phase 1) Chiplet Library · p. 2
- The Analog Chiplet represents a 15 mm2 analog component for heterogeneous technology nodes in wireless SoC disaggregation.Source: 1) (Phase 1) Chiplet Library · p. 2
- Organic and silicon substrates model contrasting packaging conditions, with approximately 110 µm and 45 µm bonding pitches, respectively.Source: 1) (Phase 1) Chiplet Library · p. 2
- The TSV Interconnect Die supports face- and back-side connections for HBM-style stacks and double-sided stacking tests.Source: 1) (Phase 1) Chiplet Library · p. 2
2) (Phase 2) Benchmark Design Suite:
The suite contains 20 benchmark designs organized into four categories spanning foundational 2.5D systems, vertical integration, complex heterogeneous architectures, and targeted stress tests.
- 20 benchmark designs are organized into four categories covering foundational 2.5D configurations, vertical integration, complex heterogeneous systems, and targeted parameter perturbations.The categories collectively exercise diverse integration topologies and design considerations.Source: 2) (Phase 2) Benchmark Design Suite · p. 2
Category 1
- Category 1 D1–D4 covers simple heterogeneous pairs, multi-chiplet systems, heterogeneous systems, and I/O-dominated configurations.Source: 2) (Phase 2) Benchmark Design Suite · p. 2
Category 2
- Category 2 D0, D5–D8 introduces simple stacking, deep TSV-based stacks, double-sided connectivity, and 3D partitioning.Source: 2) (Phase 2) Benchmark Design Suite · p. 2
Category 3
- Category 3 D9–D13 combines HBM-style stacks, independent stacks, non-uniform hierarchies, buried bridges, and full-system integration.Source: 2) (Phase 2) Benchmark Design Suite · p. 2
Category 4
- Category 4 D14–D19 perturbs parameters to exercise congestion, NRE amortization, assembly-process selection, placement regularity, and chiplet-count scaling.Source: 2) (Phase 2) Benchmark Design Suite · p. 2
B. Open-Source Benchmark Package
The benchmark package includes testcase descriptions and supporting artifacts for reproduction and extension, with all designs publicly available through Dryad.
- The 3Dblox repository provides testcase descriptions and supporting artifacts required to reproduce and extend the benchmark suite.Source: B. Open-Source Benchmark Package · p. 2
- The complete benchmark design set is publicly available through the Dryad repository under DOI 10.5061/dryad.76hdr7tb6.Source: B. Open-Source Benchmark Package · p. 2
IV. CONCLUSION
The paper presents 20 open-source 2.5D/3D heterogeneous-integration designs spanning foundational configurations, stacking topologies, hybrid architectures, and stress-test variants. Released with supporting collateral, the suite is intended to support reproducible comparison and future extension.
- The suite provides 20 designs spanning foundational 2.5D configurations, basic 3D stacking topologies, complex hybrid architectures, and targeted stress-test variants.Source: §IV · p. 2
- The benchmark structures can be extended as new integration technologies and physical-design problems emerge.Source: §IV · p. 2
- Releasing 3Dblox designs with supporting open-source physical-design collateral is intended to enable reproducible comparison across academic and commercial 3D design methodologies.Source: §IV · p. 2