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Syn2Logic: End-to-End Neuromorphic Design Automation

Artur Podobas

arXiv:2608.25536v1cs.ARcs.AI

TL;DR

The paper addresses the separation between computational neuroscience modeling and hardware design by proposing eNDA and implementing it as Syn2Logic. Its DSL and compiler generate neuromorphic hardware from neural descriptions, with reported record-setting results across C. elegans simulation, Sudoku solving, and MNIST acceleration.

  • Problem

    Computational neuroscientists and neuromorphic hardware designers operate in mostly isolated, labor-intensive flows, while prior work lacked a combined path from flexible neural models through automated exploration to FPGA and ASIC synthesis.

  • Method

    Syn2Logic implements eNDA with a multi-paradigm DSL and transformations that analyze neural models and networks, optimize hardware, and synthesize neuromorphic platforms.

  • Results

    Across three applications, the flow produced a fast C. elegans accelerator, a Sudoku solver outperforming CP-SAT/SCIP by up to 28x on FPGA, and a 5.6 million FPS/Watt MNIST accelerator on a tiny FPGA.

  • Takeaways & Limitations

    eNDA enables push-button end-to-end generation of specialized neuromorphic systems and supports hardware exploration without writing HDL code.

  • Takeaways & Limitations

    The digital class-4 backend is limited by silicon area to roughly 10^3 neurons on mid-tier FPGAs and potentially 10^4 on high-end FPGAs.

Abstract

from arXiv · show

In this work, we propose a view on electronic Neuromorphic Design Automation (eNDA), which we see as a design automation flow that bridges computational neuroscience modeling with traditional Electronic Design Automation (EDA) flow. We introduce the term, give examples of how it can be implemented, and design a prototype implementation: Syn2Logic. Syn2Logic is an entire eNDA framework, that allows neuroscientists to model neural behavior using a custom DSL and a compiler that takes the same model description down to synthesizable RTL hardware. We end the paper by applying the eNDA-flow through Syn2Logic to show how to -- without writing a single line of hardware description language (HDL) code-- (i) generate what we believe is the fastest C. elegans accelerator that runs significantly faster than state-of-the-art simulators, (ii) create (to the best of our knowledge) the fastest, most generic neuromorphic sudoku solver that outperforms CP-SAT and SCIP on TOP1465 puzzles, and (iii) create a 5.6 million FPS/Watt accelerator on a tiny FPGA that outperforms existing neuromorphic architectures in terms of speed and energy-efficiency on the MNIST dataset.

1 Introduction

Neuromorphic computing offers specialized, potentially faster and more energy-efficient computation, but requires hardware architectures that fit its sparse, event-driven neuron-and-synapse model. The paper proposes eNDA and Syn2Logic to connect neuroscience modeling with automated FPGA/ASIC generation.

  • Neuromorphic computing maps algorithms onto biologically inspired neurons and synapses, often using spiking neural networks for demanding AI, neuroscience, graph, and optimization tasks.
  • Neuromorphic architectures exploit parallelism, event-driven operation, and sparseness while communicating through spikes and computing with neurons and synapses.
  • 2.7x faster and 18.8x more energy-efficient cortical-sheet simulation on a neuromorphic FPGA than an Nvidia V100 illustrates the need for suitable high-performance architectures.
  • eNDA extends EDA and computational neuroscience to generate custom neuromorphic architectures from neural-dynamics descriptions for FPGA and ASIC targets.

2 Neuromorphic Design Automation

Neuromorphic researchers and hardware designers use largely isolated, labor-intensive flows, motivating eNDA as a unified path from neural descriptions to specialized hardware. Syn2Logic implements this approach through a DSL, compiler transformations, model and network analysis, hardware optimization, and neuromorphic synthesis.

  • Existing design flows: Computational neuroscientists model neural dynamics in simulator-oriented languages, whereas hardware designers select hardware-friendly models, manually optimize them, and map HDL descriptions to FPGA or ASIC outputs.
  • Research gap: Prior work had not combined an arbitrary-model hardware-oriented DSL, automated precision/bandwidth/timestep exploration, and direct synthesis to FPGA bitstreams and ASIC layouts.
  • eNDA methodology: eNDA bridges neuroscientific descriptions and EDA by transforming a domain expert’s neural-system model into a custom neuromorphic platform.
  • eNDA methodology: The eNDA flow parses models, builds an intermediate representation, applies hardware-agnostic and target-specific optimizations, analyzes models and networks, and synthesizes neuromorphic hardware.
  • Syn2Logic prototype: Syn2Logic combines hardware-description and neural-modeling language concepts with multiple dispatch to describe hierarchical neuromorphic systems.
  • Syn2Logic prototype: Syn2Logic models networks as event-driven connections carrying tokens, while model state can be changed externally, through ODEs, or inside events.
  • Example network: The generic accelerator description is compact but requires users to configure accelerator state before execution.

3 Results

Syn2Logic reproduces diverse neuron and plasticity dynamics while exposing hardware trade-offs in precision, fusion, area, and speed. The results also identify substantial remaining silicon-area gaps and use-case-dependent fixed-point requirements.

  • Neuron-model correctness: Syn2Logic matches Brian2 closely across LIF, Izhikevich, AdEx, and Hodgkin-Huxley neuron models, with NRMSE values from 0.0% to 0.9%.The LIF, Izhikevich, and AdEx models reproduce reference behavior closely; Hodgkin-Huxley reaches 0.9% NRMSE.
  • Neuron-model synthesis: 137 MHz and less than 500 µm2 characterize the LIF model, while Hodgkin-Huxley is significantly slower and can exceed it by more than 100x in area.Synthesis results show increasing neuron-model complexity raises area and reduces operating speed.
  • Hardware trade-offs: Nearly 50% higher clock frequency from fused data paths trades against area, with non-fused variants 7.6%–74.7% smaller.Fused paths defer rounding until storage, improving frequency but widening datapaths and increasing hardware cost.
  • Limitations and design scope: Neuron and synapse implementations remain much larger than biological counterparts, and suitable fixed-point width depends strongly on the use case and tolerated error.The smallest LIF model is still 4.4x–55x larger than cited biological cells, while plasticity precision can be reduced when higher error is acceptable.
  • Synapse correctness: Pairwise STDP, TripletSTDP, RSTDP, and BCPNN reproduce expected plasticity behavior, with tested fixed-point variants reaching NRMSE values as low as 0.20%.The evaluated rules use induction protocols covering potentiation, depression, rewards, anti-rewards, and multiple BCPNN activity patterns.
  • Synapse synthesis: 60.4 µm2 is the smallest reported synapse area, whereas BCPNN reaches 1269.9 µm2; fused variants are generally larger, with a 71.7% TripletSTDP area benefit.BCPNN is the most expensive rule because it uses a log function, while Pairwise-STDP is the smallest.

4 Conclusion

The paper presents Syn2Logic as a complete push-button neuromorphic design-automation flow and reports three performance records across simulation, optimization, and inference. It also identifies backend capacity and model-language interoperability as future-work concerns.

  • Syn2Logic implements a complete NDA flow for push-button end-to-end generation of neuromorphic systems.
  • The framework produced reported records for C. elegans simulation, generic Sudoku solving, and energy-efficient spike-based MNIST inference.The MNIST accelerator reached 5.6 million frames-per-second per Watt on a 12-year-old toy FPGA, with ASIC estimates above 1 billion frames per second.
  • Generative AI helped transport models between neural-description languages when supported by validation suites.The paper suggests this could eventually unify development across modeling frameworks.
  • The digital backend is extremely performant but cannot easily accommodate many neurons and synapses before exhausting silicon area.The stated scale is on the order of 10^3 neurons on mid-tier FPGAs and potentially 10^4 on high-end FPGAs.
  • Future directions include 3D monolithic integration, temporally shared datapaths, and analog or memristive backends.These directions aim to increase capacity or target alternative post-Moore substrates without changing model descriptions.

5 Methods

The Syn2Logic compiler is a manually written C/C++ implementation whose front end uses FLEX and a hand-written recursive-descent parser.

  • The Syn2Logic compiler contains 17,500 lines of manually written C/C++ code.FLEX and a hand-written recursive-descent parser account for 2,600 lines; the remainder implements intermediate optimizations and backend generation.

5.2 Fixed-Point Representation

Syn2Logic represents generated hardware values in fixed-point format using integer and fractional bit counts that determine range, word length, and quantization.

  • Fixed-point values use the QM:N format, where M denotes integer bits and N denotes fractional bits.The representation has total word length M + N + 1 bits, range ±2^M, and quantization step 2^-N.

5.3 Neuron Models Exploration

The exploration covers LIF, Izhikevich, AdEx, and Hodgkin-Huxley neuron models, including their dynamics, spike rules, parameters, and Syn2Logic reference configurations.

  • LIF: The LIF model integrates membrane potential dynamics and emits a spike at Vth before resetting to Vreset.The described parameters include Cm = 250 pF, τm = 10 ms, Vth = −55 mV, and Vreset = −70 mV.
  • Izhikevich: The Izhikevich model couples dimensionless membrane-like and recovery variables with a threshold-triggered spike-and-reset rule.When v ≥ 30 mV, the model sets v ← c and u ← u + d, using canonical regular-spiking parameters.
  • AdEx: The AdEx model combines an exponential spike-initiation term with a slow adaptation current w and resets voltage at the spike cutoff.The stated configuration uses Vpeak = 0 mV and a spike-triggered adaptation increment b = 80.5 pA.
  • Hodgkin-Huxley: The Hodgkin-Huxley model explicitly resolves action potentials through voltage-gated sodium and potassium channels.Its equations include conductances gNa and gK, gating variables m, h, and n, and standard voltage-dependent rate functions.

0.01 V 55 1 −e−V 5510 , βnV = 0.125 e−V 6580.

Syn2Logic evaluates neuron-model fidelity against software references using controlled numerical settings, fixed-point hardware generation, and normalized error relative to a 5% design budget.

  • LIF, Izhikevich, and AdEx models use Δt = 0.1 ms, while HH uses Δt = 0.01 ms in both frameworks.
  • Initial correctness hardware uses fixed-point Q32:24 with fused operations enabled and constant rounding disabled.
  • Injected-current sweeps span 0–600 pA for LIF, 0–15 for Izhikevich, 0–900 pA for AdEx, and 0–1000 pA for HH.Syn2Logic uses coarser sweep steps because each point requires compilation and QuestaSim simulation.
  • Fidelity is measured with normalized root-mean-square error between test and reference firing-rate curves, scaled by the reference dynamic range.The normalization makes the metric dimensionless and comparable across models with different firing-rate scales.
  • A configuration is considered faithful when NRMSE remains within a 5% design budget.

5.4 Synapse Models

Syn2Logic studies four canonical synaptic-plasticity rules by compiling deterministic spike-driven models, simulating them cycle-accurately, and comparing fixed-point weight trajectories with high-precision references.

  • The evaluated rules are PairSTDP, triplet STDP, reward-modulated STDP, and BCPNN.They cover pair-based, higher-order triplet, three-factor reward-modulated, and probability-based synaptic plasticity families.
  • PairSTDP uses exponentially decaying pre- and postsynaptic traces to update synaptic weight on pre- and post-spikes.The output conductance is emitted from the updated weight on pre-spikes.
  • Triplet STDP adds slow pre- and postsynaptic traces to fast pair traces, with the second-order trace setting the integer-bit requirement.
  • RSTDP accumulates spike-timing eligibility and converts it into a weight change only when a separate reward event arrives.The reward does not reset the eligibility trace.
  • Each rule is driven by a deterministic protocol, compiled with a self-checking VHDL testbench, and simulated cycle-accurately in QuestaSim.
  • Fixed-point fidelity is quantified as weight-trajectory NRMSE relative to high-precision references, using a 5% error budget to map acceptable formats.BCPNN undefined log-odds points caused by P-trace underflow are excluded from the comparison set.

5.5 Caenorhabditis elegans

The C. elegans evaluation compiles a 302-neuron c302 connectome directly to hardware and compares its spike train with three software simulators under matched timing conditions.

  • The reference network contains 302 integrate-and-fire neurons with chemical and electrical connections from the c302 Level A model.Neurons receive uniform tonic input of 2.1 pA and a flat gap-junction conductance.
  • jNeuroML, Brian2, and NEST simulate the same network for 1000 ms using a 0.1 ms timestep.NEST uses 32 OpenMP threads, and the experiment comprises 10,000 steps.
  • Syn2Logic advances the entire network one timestep per clock cycle, so the 1000 ms experiment takes exactly 10,000 clock cycles.The cycle count is independent of firing activity.
  • Q7:15 fixed-point arithmetic and a 0.2 synapse-pruning factor reduce hardware cost while preserving the evaluated accuracy.Only 20% active synaptic weights propagate into neurons, with constants quantized to up to 1% relative error.
  • The generated spike train reproduces software baselines with correlation 0.9967 and 0.94% windowed error against the full-precision 32:32 reference.
  • The same compiler-generated VHDL is evaluated through independent FPGA and ASIC backend flows.The FPGA flow targets Intel Quartus on Agilex 7, while the ASIC flow uses Cadence tools with the ASAP7 library.

5.6 Sudoku Accelerator

The Sudoku accelerator represents candidate cell-digit assignments as spiking Izhikevich neurons and uses WTA dynamics, inhibition, and randomized parameter search to solve benchmark puzzles.

  • The evaluation tunes the solver on 46 Mantere–Koljonen puzzles and tests generalization on TOP1465 and Euler 96.Overlapping puzzles between the Mantere–Koljonen and Euler 96 sets are removed.
  • Performance timing counts puzzle-solving time only, excluding startup and puzzle-configuration overhead.CP-SAT is evaluated with its fastest single-worker configuration.
  • The solver is compared with SCIP, CP-SAT, and Tdoku, representing state-of-the-art optimization, constraint-programming, and specialized Sudoku approaches.
  • 5.6.3 Sudoku Neuron model: The network uses 9 × 9 × 9 = 729 Izhikevich neurons, one for each cell-digit assertion, with two exponentially decaying escape currents.The escape currents allow the winner-take-all network to leave local minima.
  • 5.6.3 Sudoku Neuron model: Inhibitory synaptic current enforces row, column, box, and one-digit-per-cell constraints by scaling inhibition with the number of simultaneous conflicts.
  • 5.6.4 Parameter search: Parameter search samples all twelve tunable parameters jointly because good operating points are isolated spikes in a chaotic single-precision quadratic landscape.The search consumed nearly a week of overnight iterative searches.

5.7 S-MLP Accelerator

The S-MLP accelerator uses a rate-coded spiking multilayer perceptron whose hardware constraints are incorporated during training. FPGA measurements and comparisons position the implementation within the reported MNIST accelerator landscape.

  • Architecture: The 784−128−64−10 network contains 109 184 parameters and uses non-leaky integrate-and-fire neurons with reset-by-subtraction.Inputs are rate-coded, and classification selects the output neuron with the most spikes over 25 or 50 timesteps.
  • Training: Weight pruning and per-neuron bandwidth limits are fine-tuned during training with hardware selection in the loop.The resulting trained weights are the ones used by the generated logic.
  • Evaluation: Test-set accuracies use all 10 000 MNIST images, with repeated checkpoint evaluations varying by ±0.3 points due to the Poisson seed.
  • Power measurement: 0.307 W is measured for the DE10-Lite system-on-chip during accelerator classification.The measurement uses a 0.01 Ω sense resistor in the MAX10 device’s 1.2 V core rail and includes surrounding SoC components beyond the generated accelerator.
  • Baselines: The comparison includes FPGA implementations such as DeepFire2, SyncNN, E3NE, and Minitaur, alongside ASIC platforms including TrueNorth, Loihi, and SpiNNaker.Reported MNIST accuracies across the compared works span 92% to 99.6%.

5.8 Software

The software environment combines high-level spiking-neural-network simulators and training libraries with commercial tools for digital verification, synthesis, physical implementation, and FPGA deployment.

  • Simulation: NEST models network-level spiking dynamics and scales to simulations involving thousands to millions of neurons and connections.
  • Simulation: Brian2 specifies neuron and synapse models as differential equations with units, thresholds, resets, refractoriness, and plasticity rules.Its high-level Python interface is designed to preserve modeling flexibility while maintaining performance.
  • ASIC implementation: Cadence Genus performs RTL synthesis, while Innovus performs physical implementation and place-and-route.The flow uses timing constraints and a standard-cell library for optimization across timing, area, and power.
  • Verification: QuestaSim verifies VHDL, Verilog, and SystemVerilog digital designs before fabrication or FPGA deployment.
  • Training: snnTorch v0.9.4 provides spiking neurons, encoders, surrogate gradients, and loss functions as PyTorch modules for SNN construction and training.
  • FPGA implementation: Altera Quartus compiles FPGA designs, performs timing analysis and simulation, and configures target devices.Quartus Pro 26.1 was used for DE10-Agilex, and Quartus Lite 18.1 for the DE10-Lite MAX10 board.

5.9 Experimental Platform

Experiments used a controlled server environment for performance-sensitive work and two Terasic FPGA platforms spanning mid-range Agilex and low-range MAX10 devices. Supplementary artifacts are planned for release as a Docker image.

  • Server platform: The server has two Intel Xeon Silver 4514Y processors, 32 cores, 64 hyperthreads, and 256 GB of DDR5 RAM.It runs Rocky 9.8 and kernel 5.14.0-687.10.1, with performance-sensitive experiments isolated using Slurm 25.11.4.
  • FPGA platform: FPGA execution uses a DE10-Agilex with 1.4M logic elements and a DE10-Lite MAX10 with 50k logic elements.The platforms provide 139 Mb and 1.6 Mb SRAM, respectively.
  • Reproducibility: The authors plan to release data, scripts, results, Syn2Logic descriptions, VHDL files, bitstreams, grammar, and compiler in an independent Docker image.

Declarations

The Syn2Logic prototype, neural-model descriptions, and manuscript were authored by the paper’s author, with language-model assistance limited to specified development, analysis, and polishing tasks.

  • Authorship and assistance: The author wrote Syn2Logic and the neural-model descriptions by hand, while Claude Fable 5.0 and Opus 5.0 assisted with Syn2Logic files, conversions, plotting, scripting, analysis, and manuscript polishing.
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