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Study of Resistive Switching Dynamics and Memory States Equilibria in Analog Filamentary Conductive-Metal-Oxide/HfOx ReRAM via Compact Modeling
Matteo Galetta, Donato Francesco Falcone, Victoria Clerico, Wooseok Choi, Stephan Menzel, Antonio La Porta, Tommaso Stecconi, Folkert Horst, Bert Jan Offrein, Valeria Bragaglia
TL;DR
Existing compact models do not adequately capture analog resistive switching in CMO/HfOx ReRAM. This paper develops a physics-based compact model and shows that it reproduces multiple switching behaviors while identifying and mapping equilibrium memory states under pulsing and quasi-static conditions.
Problem
Existing compact models inadequately capture analog resistive switching behavior, limiting modeling of emerging ReRAM memory and neuromorphic applications.
Method
The paper develops a physics-based compact model coupling ion migration, electron hopping, parasitic resistances, and thermal effects across varied electrical inputs.
Results
The model reproduces quasi-static I-V characteristics, pulse-driven switching kinetics, and analog bidirectional conductance modulation, while identifying equilibrium stabilization around the symmetry point.
Takeaways & Limitations
The model supports visualization of equilibrium memory states and design optimization for analog neuromorphic systems and non-volatile memory architectures.
Takeaways & Limitations
The model assumes sufficiently low switching voltages prevent interlayer ion migration and treats HfOx conduction as changing only during electro-forming.
Abstract
from arXiv · showhide
Resistive Random Access Memory (ReRAM) devices offer a promising solution for next-generation non-volatile memory and neuromorphic computing systems. Yet, existing compact models fail to capture analog resistive switching behavior of ReRAM devices. This work presents an advanced physics-based compact model for analog filamentary Conductive-Metal-Oxide (CMO)/HfOx ReRAM, capable of reproducing switching characteristics over a broad range of operating conditions. Compared to the state-of-the-art, the model extends the dynamic interplay between ion migration and electron hopping, while also accounting for parasitic resistive elements. Simulations of various voltage inputs are tested to reproduce quasi-static I-V curves, SET switching kinetics under single-pulse programming conditions, and analog accumulative conductance modulation upon bipolar identical pulse streams. Additional simulations reveal the physical criterion underlying the stabilization of the CMO/HfOx-based ReRAM memory state around the equilibrium point, namely symmetry point, under pulsing conditions when a fading memory mechanism emerges. Building upon the evidence of such equilibrium stabilization under pulsing and quasi-static conditions, a procedure is established to visualize and map equilibrium memory states across different input domains. The physical model supports design optimization of switching behavior for analog neuromorphic systems and non-volatile memory architectures. It also enables accurate integrated circuit simulations with CMO/HfOx-based ReRAM technology.
1 Introduction
CMOS scaling has exposed cost and integration challenges for conventional embedded memories, motivating ReRAM as a nonvolatile, low-power, fast memory and in-memory-computing technology. This work develops and evaluates a compact model across diverse electrical inputs and operating timescales, including analog switching stabilization around a symmetry point.
- Motivation: CMOS scaling has made conventional SRAM, DRAM, and flash memories struggle to match processor performance, while advanced embedded memories face rising costs and CMOS-process incompatibility.These limitations motivate alternative embedded-memory technologies.
- ReRAM opportunity: ReRAM combines non-volatility, low power consumption, and fast read/write performance, while crossbar arrays support DNN matrix-vector multiplications with constant time complexity O(1).The architecture enables highly parallel computation for in-memory computing.
- Model contribution: The compact device model is applied to electrical inputs not addressed previously, validating applicability across a broad range of operating time scales.The model includes stochastic electronic-transport variability to reflect conduction non-idealities.
- Model validation: Simulations reproduce experimental quasi-static I-V characteristics, single-pulse programming times, and analog bidirectional accumulative conductance modulation.These tests span distinct switching and programming conditions.
- Equilibrium stabilization: Simulations reproduce analog switching and resistance stabilization around the CMO/HfOx ReRAM symmetry point under experimental pulse schemes.The symmetry point’s physical origin and dependence on input pulse scheme are used to study switching symmetry.
2 Compact Modeling of Analog Resistive Switching Dynamics
The compact model represents analog resistive switching through oxygen-vacancy dynamics in a CMO dome, coupled with field-driven ion migration, electron hopping, parasitic resistances, and electrothermal transients. It uses vacancy concentration as the memory state while dynamically linking defect redistribution to electronic conduction and temperature.
- Physical structure and switching region: CMO is the active layer whose reversible, non-volatile resistivity changes produce the memory effect, while its geometry spreads the electric field toward the top electrode.Under sufficiently low switching voltages, interlayer ion migration is avoided and the CMO controls the switching region.
- Ion migration dynamics: The model uses doubly charged oxygen-vacancy concentration, CV, in the CMO dome as the state variable governing defect displacement over the voltage-input time span.Only V··O vacancies with charge +2 are considered because they have the lowest formation energy.
- Ion migration dynamics: A vertical electric field lowers the migration barrier and drives oxygen-vacancy drift through Mott-Gurney site-to-site hopping along the dome thickness.The ion drift mean velocity vIon is isolated from the ionic drift current density JIon to analyze migration-speed profiles.
- Parasitic and electrothermal effects: The equivalent circuit includes variable CMO resistance, invariant filament and electrode resistors, and a series resistance, while Joule heating drives lumped thermal transients.The thermal model uses capacitance Cth, resistance Rth, reference temperature T0, and electrical power Pe = Ie · VA.
- Electronic transport: Electronic conduction is modeled as defect-mediated electron hopping because CMO is the device conduction bottleneck, with trap-state density dynamically modified by CV.The scaling factor β satisfies 0 < β < 1 and filters occupied or available states that contribute to conduction.
3 ReRAM device electrical response simulations
The compact model reproduces the highly nonlinear quasi-static C8W I-V response using hopping transport and extends terminal-behavior analysis to ion migration. Simulations identify a common ionic switching-onset speed and confined migration length for SET and RESET, while linking vacancy migration to defect concentration and resistance-state modulation.
- 3.1 Quasi-Static I-V Characteristic: The simulated quasi-static C8W I-V characteristic accurately reproduces experimental data over 10 full sweep cycles using the same triangular voltage input.The simulations used RSeries = 0 Ω, with switching onsets marked on the modeled ion drift velocity.
- 3.1 Quasi-Static I-V Characteristic: Hopping transport accurately reproduces the highly nonlinear I-V characteristic, with intra-lattice migration barriers and hopping parameters calibrated exclusively from experimental I-V data.The calibrated hopping parameters are ae and ∆EA.
- 3.2 Switching Kinetics and Temperature-Programming Time Trade-Off: ∼1.1 nm s−1 is the ionic mean speed initiating both SET and RESET migration at their switching onsets despite electrothermal asymmetry.Migration slows as Joule heating is counteracted by decreasing current and conductance.
- 3.2 Switching Kinetics and Temperature-Programming Time Trade-Off: < sM > ∼6 nm for both SET and RESET transitions, suggesting bidirectional migration of the same ionic species within a region thinner than lD.The passage notes that advanced spectroscopy is needed to confirm defect-concentration variations within the dome portion.
- 3.2 Switching Kinetics and Temperature-Programming Time Trade-Off: Oxygen-vacancy migration modulates CMO-dome defect concentration, changing electron-trap-state density and contributing to HRS depletion and LRS repopulation.Figure 2b shows vacancy depletion in HRS and repopulation in LRS.
V < CLRS
The model links resistive-state dynamics to oxygen-vacancy redistribution and nonlinear trap-assisted tunneling, reproducing SET kinetics and analog bidirectional conductance modulation. It also captures equilibrium stabilization, cumulative switching, and realistic conduction variability under pulse programming.
- Resistive-State Dynamics: Oxygen-vacancy redistribution changes trap spacing and TAT activation energy, producing low- and high-resistance states through variations in available conduction paths.Homogeneous traps in LRS support regular TAT paths, whereas RESET-driven vacancy migration toward the filament interface creates a trap deficit in HRS.
- Switching Kinetics: SET and RESET transitions occur when electrothermal energy overcomes the ion-migration barrier, while ∆WA increases with CV during SET.A strong defect-concentration gradient at the CMO/conductive-filament interface thermodynamically favors oxygen-vacancy migration.
- Resistive-State Dynamics: Applied voltage dynamically changes resistance during non-switching phases through nonlinear TAT transport, even when the vacancy concentration remains constant.Joule heating and bias accelerate electron jumps among trap states without requiring a change in ∆CV.
- Switching Kinetics: The SET switching time ∆tSET depends exponentially on VSET, creating a voltage–programming-time trade-off that balances fast switching against excessive heating and degradation.Programming voltages up to approximately 10 · VREAD were used, with |VA| = 0.2 V fixed for read operations.
- Analog Bidirectional Accumulative Conductance Response: Identical bipolar voltage pulses produce cumulative conductance updates and oscillatory stabilization around the symmetry point, which the model closely reproduces.Pulse polarity drives ion displacement and cumulative CV changes, while variations in available electron traps retrieve intermediate resistance states across the G-window.
- Analog Bidirectional Accumulative Conductance Response: The model incorporates stochastic trap occupancy to reproduce conduction variability and realistic analog resistive-switching characteristics.GREAD is modeled as directly proportional to the available electron-trap density, and stochastic TAT captures resistance fluctuation dispersion.
4 Analysis of Memory States Equilibria
The analysis identifies equilibrium defect states as symmetry points arising from balanced oxygen-vacancy migration, with multiple equilibria possible and their locations dependent on the electrical input. It also shows that quasi-static and pulse approaches can identify equivalent memory states, enabling equilibrium-based skew mapping across input domains.
- 4.1 Physical Origin of the symmetry point: Balanced oxygen-vacancy migration defines the equilibrium defect state at the symmetry point.The equilibrium condition is associated with equal migration in both directions.
- 4.1 Physical Origin of the symmetry point: Multiple equilibrium defect states can emerge when the resistive window expands, while changing the electrical input shifts the equilibrium location.The passage identifies distinct equilibria Eq.P.-B1,2,3 and states that Eq.P.-A differs from Eq.P.-B1.
- 4.1 Physical Origin of the symmetry point: Quasi-static and pulse responses produce an identical memory-state window when initialized from the same stage.The EDS obtained from State Dynamic Routes matches the defect state reached by the single-pulse response.
- 4.2 Memory State Mapping Across Input Domains: The equivalence between quasi-static EDS and pulse symmetry points supports mapping equilibrium memory states across input domains.The mapping procedure uses this equivalence to evaluate switching symmetry through the SP skew, where 50% denotes perfect symmetry.
- 4.2 Memory State Mapping Across Input Domains: The skew-mapping procedure is tested with quasi-static I-V sweeps and bidirectional accumulative conductance responses in the same conductance window.The test uses the case A sweep and corresponding conductance-response data.
5 Training Simulations with Tiki-Taka Algorithm through Pulse-Amplitude Tuning
The section evaluates Tiki-Taka training with ReRAM conductance responses and shows that training accuracy and convergence depend strongly on symmetry-point centering. The highest accuracy and fastest convergence occur with VP+ = +1.47 V and VP− = −1.45 V, although this setup narrows the G-window.
- Tiki-Taka requirements: TTv1 relaxes device constraints for SGD convergence by using an additional gradient-accumulation matrix A with ReRAM devices operated around the SP.The TTv1 approach introduces matrix A for gradient accumulation.
- Tiki-Taka requirements: High training accuracy still requires stable conductance states, a Noise-to-Signal Ratio < 100%, and a centered SP.TTv2 considerably relaxes the requirement for reliable conductance states by adding digital low-pass filtering.
- Pulse-amplitude tuning: Training accuracy decreases as the SP shifts from the G-window center, with highly shifted SP producing non-convergent behavior.These results are reported for MNIST classification on a 3-FC (784-256-128-10) network.
- Pulse-amplitude tuning: +1.47 V and −1.45 V produce the highest accuracy and fastest convergence through a strongly centered SP.The pulse-amplitude setup also limits Gmin, resulting in a smaller G-window because of weaker conductance modulation.
6 Conclusion
The proposed physics-based compact model accurately reproduces analog CMO/HfOx ReRAM switching across operating conditions, enabling predictive circuit-level simulations. Its compatibility with differentiable IC design tools supports future SPICE integration and pulse-engineered analog ReRAM applications.
- Conclusion: The model accurately captures analog resistive switching across a wide range of operating conditions with negligible error.Its physical framework reproduces multiple experimental characteristics of the ReRAM memory cell.
- Conclusion: Input-condition-independent accuracy makes the compact model suitable for predictive simulations in circuit-level design environments.The conclusion identifies this capability as a key basis for design use.
- Conclusion: Results underscore the importance of input pulse engineering for analog ReRAM-based RPUs.The passage connects this conclusion to MNIST digit classification results.
- Conclusion: Future work will integrate the model into SPICE-based IC design tools requiring differentiable device descriptions.The model’s inherent compatibility lays groundwork for circuit-level simulations with CMO/HfOx-based ReRAM technology.
7 Experimental Section
The experimental section describes quasi-static electrical characterization of CMO/HfOx-based ReRAM using a parameter analyzer and a staircase voltage ramp. Measurements apply voltage to the top electrode while grounding the bottom electrode, with defined step duration and sweep rate.
- Electrical Characterization: Quasi-static I-V sweeps were performed using an Agilent B1500A Semiconductor Device Parameter Analyzer.
- Electrical Characterization: The voltage signal was applied to the top electrode while the bottom electrode was biased to earth ground.
- Electrical Characterization: The staircase ramp used 10 mV voltage steps, each lasting 100 ms/step, corresponding to a global Sweep Rate (SR) of 0.1 Vs−1.