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Update Disturbance-Resilient Analog ReRAM Crossbar Arrays for In-Memory Deep Learning Accelerators
Wooseok Choi, Tommaso Stecconi, Donato Francesco Falcone, Matteo Galetta, Victoria Clerico, Elisa Zaccaria, Mamidala Saketh Ram, Antonio La Porta, Folkert Horst, Daniel Jubin, Matias Senger, Marilyne Sousa, Steffen Reidt, Ralph Heller, Bernabe Linares-Barranco, Valeria Bragaglia, Bert Jan Offrein
TL;DR
In-memory training with analog ReRAM remains experimentally limited, particularly because fully parallel weight updates can disturb cross-point conductances. This paper develops a CMOS-compatible ReRAM and combines device simulations, array demonstrations, and hardware-aware neural-network simulations to address that challenge. The device sustains disturbance-free behavior beyond 100k pulses and supports fully parallel in-memory weight updates.
Problem
Experimental analog memory-array studies remain limited, while disturbances during fully parallel updates can impair analog training accuracy.
Method
The study develops a 350 nm CMOS-compatible analog ReRAM and evaluates its disturbance physics, array weight mapping, and hardware-aware neural-network behavior.
Results
k < 0.005 with 0.025 standard deviation after 100k pulses, alongside disturbance-free parallel weight mapping and hardware-aware validation of fully parallel updates.
Takeaways & Limitations
The demonstrated ReRAM supports the potential of fully in-memory deep-learning accelerators with parallel weight updates.
Takeaways & Limitations
Millisecond-long pulse widths and k values as large as 3% require further improvement for successful deep-learning acceleration.
Abstract
from arXiv · showhide
Resistive memory (ReRAM) technologies with crossbar array architectures hold significant potential for analog AI accelerator hardware, enabling both in-memory inference and training. Recent developments have successfully demonstrated inference acceleration by offloading compute-heavy training workloads to off-chip digital processors. However, in-memory acceleration of training algorithms is crucial for more sustainable and power-efficient AI, but still in an early stage of research. This study addresses in-memory training acceleration using analog ReRAM arrays, focusing on a key challenge during fully parallel weight updates: disturbances of the weight values in cross-point devices. A ReRAM device solution is presented on 350 nm silicon technology, utilizing a resistive switching conductive metal oxide (CMO) formed on a nanoscale conductive filament within a HfOx layer. The devices not only exhibit 60 ns fast, non-volatile analog switching, but also demonstrates outstanding resilience to update disturbances, enduring over 100k pulses. The disturbance tolerance of the ReRAM is analyzed using COMSOL Multiphysics simulations, modeling the filament-induced thermoelectric energy concentration that results in a highly nonlinear device responses to input voltage amplitudes. Disturbance-free parallel weight mapping is also demonstrated on the back-end-of-line integrated ReRAM array chip. Finally, comprehensive hardware-aware neural network simulations validate the potential of our ReRAM for in-memory deep learning accelerators capable of fully parallel weight updates.
1 Introduction
Analog ReRAM crossbar arrays could support sustainable in-memory training, but experimental array studies remain early and parallel updates introduce damaging disturbances. This work develops and evaluates a disturbance-resilient analog ReRAM platform for fully parallel weight updates.
- Motivation: Analog in-memory computing accelerates inference, while computationally expensive training workloads remain outsourced to off-chip digital processors.This limits the ability of current systems to perform training directly in memory.
- Motivation: Training costs for state-of-the-art AI models exceed 100 million US dollars as neural networks grow and digital hardware faces power-efficiency constraints.The paper presents fully parallel in-memory weight updates as a path toward more sustainable AI.
- Research gap: Experimental studies using analog memory arrays remain in an early stage, motivating systematic work that combines experiments, simulations, and practical parallel update schemes.The paper identifies this combination as necessary for bridging the research gap.
- Update disturbances: Small disturbances in analog synaptic memory can degrade learning accuracy by preventing granular memory states from converging, especially as disturbances accumulate during continuous learning.Digital-memory disturbance standards are not directly applicable to analog memory devices and in-memory training systems.
- Contributions: The study develops and evaluates a CMOS-compatible disturbance-resilient analog ReRAM on 350 nm silicon using CMO/HfOx materials, including 1T1R cells and arrays.COMSOL simulations link filament-induced thermoelectric energy localization to highly nonlinear switching responses, while array experiments demonstrate disturbance-free parallel weight mapping.
- Contributions: Hardware-aware neural-network simulations incorporate ReRAM properties and the parallel update scheme to evaluate the technology's potential for fully in-memory AI accelerators.The study also demonstrates disturbance-free parallel weight mapping on a wire-bonded 1T1R array.
2 Background
Fully parallel outer-product updates encode learning signals through coincident stochastic voltage pulses, but non-coincident pulses can disturb cross-point devices. Strong switching nonlinearity is therefore central to realizing scalable in-memory training without costly per-cell filtering.
- Outer-product update: The outer-product update applies W ← W + ηxd^T, where η is the learning rate, directly to analog memory states.The update must be performed in-memory and in parallel across analog memory arrays for in-memory training acceleration.
- Outer-product update: A stochastic pulse-encoding scheme performs fully parallel outer-product updates in constant time complexity O(1) through probabilistic coincidence of voltage pulses.Coincident pulses at each cross-point occur proportionally to the nominal update ηx_id_j.
- Pulse encoding: The scheme performs gradient calculations and updates by supplying stochastic pulse trains, with resistive devices changing state when full-amplitude pulses coincide.Its operational time O(1) is independent of the weight-matrix size.
- Disturbance suppression: Sparse pulse trains create more non-coincident than coincident pulses, so devices must ignore half-Vs pulses while responding to coincident full-Vs pulses.Strong switching nonlinearity with respect to voltage amplitude is desirable for avoiding update disturbances.
- Disturbance suppression: Using multiple transistors to filter pulses can suppress disturbances but incurs significant penalties in memory density and system scalability.The paper instead presents an analog ReRAM approach with inherently disturbance-tolerant switching enabled by a pre-formed conductive filament.
3 Results
The CMO/HfOx analog ReRAM forms a filamentary, highly nonlinear switching device that suppresses half-Vs update disturbances. Array experiments and hardware-aware simulations show disturbance-free parallel mapping and successful in-memory training.
- Resistive-switching model: COMSOL simulations show that the filament concentrates electric field and temperature in the CMO layer, producing nonlinear conductance changes with voltage amplitude.Joule heating and field concentration accelerate ion migration, so half-Vs pulses do not change conductance.
- Array disturbance resilience: The measured non-linearity factor k is close to zero, indicating negligible half-Vs disturbance in the analog ReRAM.The device remained resistant to conductance changes under stress signals of 0.7 V and -1 V.
- Array disturbance resilience: After 1M non-coincident pulses, conductance showed no tendency to drift, while after 100k pulses the mean k was below 0.005 and standard deviation below 0.025.Tests used +0.7 V and -0.9 V effective pulse drops with 2.5 µs pulse width across multiple devices.
- Array disturbance resilience: Parallel array mapping leaves non-target devices undisturbed, supporting fully parallel weight updates in the integrated ReRAM crossbar.Letter mapping and final conductance changes demonstrate disturbance tolerance during parallel crossbar updates.
4 Discussion
The discussion benchmarks analog emerging memories for deep-learning accelerators and highlights the proposed CMO/HfOx ReRAM’s disturbance resilience. It also identifies device and training-system trade-offs that remain relevant to scalability and learning accuracy.
- Benchmarking: Table 1 benchmarks analog emerging memories for deep learning accelerator applications, including the proposed technology.
- Comparison and limitations: Alternative memories retain unresolved constraints: ECRAM requires improvement in millisecond-long pulses, k as large as 3%, and device area for scalable acceleration.
- Device design: The proposed CMO/HfOx analog ReRAM localizes switching around a pre-formed nanoscale conductive filament, enhancing switching non-linearity.
- Disturbance resilience: 100k disturbance pulses produced no notable conductance shift, with k < 0.005 and 0.025 standard deviation.
- Learning implications: Asymmetric non-linearity factors between kup and kdn can cause substantial accuracy loss, motivating pulse, baseline-voltage, and learning-hyperparameter optimization.
- Learning implications: Training iterations increase the absolute number of non-coincident pulses, potentially amplifying disturbance effects, so dataset size should be optimized accordingly.
5 Conclusion
The study demonstrates a disturbance-resilient analog ReRAM technology for fully parallel in-memory weight updates, combining fast analog switching with experimentally validated array operation and hardware-aware neural-network assessment.
- The ReRAM chip was developed on a 350 nm silicon node using CMOS-compatible materials and processes.
- 60 ns switching and analog memory states provide properties relevant to in-memory training accelerators.The devices operate with fast linear switching during open-loop operation.
- COMSOL simulations identified nanoscale-filament thermoelectric energy concentration and investigated nonlinear responses to input voltage.
- Disturbance-tolerant parallel weight mapping was experimentally demonstrated on a ReRAM array chip.
- Hardware-aware neural-network simulations assessed learning accuracy while incorporating the experimental findings.The results highlight the promise of CMO/HfOx ReRAM technology for in-memory AI hardware accelerators.
6 Experimental Section
The experimental section describes BEOL-integrated CMO/HfOx ReRAM fabrication, electrical characterization, and hardware-aware simulations of fully parallel in-memory training updates.
- Fabrication: The active ReRAM stack includes TiN electrodes, a nanoscale CMO layer, and a sub-stoichiometric HfOx layer integrated with 0.35 µm CMOS.The materials are deposited and patterned using PEALD, sputtering, dry etching, passivation, and via opening.
- Neural Network Simulation: Hardware-aware neural-network simulations modeled a 784–256–10 fully connected network containing 203,264 analog ReRAM memories.The simulations used sigmoid and softmax activations and stochastic-gradient-descent training.
- In-Memory Outer-Product Weight Update: The fully parallel update model generated stochastic bitstreams from neuron signals and modeled coincident and non-coincident pulses across array cross-points.The update count is proportional to ηx_i d_j, and the material model reproduces nonlinear per-pulse weight changes.
- In-Memory Outer-Product Weight Update: The simulations incorporated soft bounds, cycle-to-cycle fluctuations, device-to-device boundary noise, and disturbance effects from half pulses.The bitstream length was initially set to η/dw_min to match the full-precision baseline learning rate.