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Integrated Hardware Annealing based on Langevin Dynamics for Ising Machines

Yongchao Liu, Lianlong Sun, Michael Huang, Hui Wu

arXiv:2608.26100v1cs.AR

TL;DR

Ising machines can become trapped in local minima while solving combinatorial optimization problems. The paper develops hardware annealing based on Langevin dynamics and evaluates it through chip- and behavioral-level simulations, reporting improved ground-state probability, solution quality, and time-to-solution.

  • Problem

    Ising machines may get trapped in local minima, degrading solution quality during ground-state search for combinatorial optimization problems.

  • Method

    The paper proposes a physical hardware annealing algorithm based on Langevin dynamics, using random-noise perturbation and scale-adjusted noise injection in an Ising-machine substrate.

  • Results

    The proposed method reaches the ground state with 86.5% probability, improves solution quality by 97.5%, and reduces time-to-solution by 50% at equivalent solution quality.

  • Takeaways & Limitations

    The simulations indicate that Langevin-dynamics hardware annealing can help Ising machines escape local minima with short time-to-solution.

Abstract

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Ising machines are non-von Neumann machines designed to solve combinatorial optimization problems (COP) by searching for the ground state, or the lowest energy configuration, within the Ising model. However, Ising machines often face the challenges of getting trapped in local minima due to the complex energy landscapes. Hardware annealing algorithms help mitigate this issue by using a probabilistic approach to steer the system toward the ground state. In this paper, we present a hardware annealing algorithm for Ising machines based on Langevin dynamics, a stochastic perturbation by random noise. Theoretical analysis, system-level design, and detailed circuit design are carried out. We evaluate the performance of the algorithm through chip-level simulation using a standard 65-nm CMOS technology to demonstrate the algorithm's efficacy. The results show that the proposed hardware annealing algorithm effectively guides the system to reach the ground state with a probability of 86.5%, significantly improving the solution quality by 97.5%. Further, we compare the algorithm with state-of-the-art hardware annealing methods through behavioral-level simulations, highlighting its improved solution quality alongside a 50% reduction in time-to-solution.

I. INTRODUCTION

Combinatorial optimization problems can require exponentially growing search resources, while Ising machines offer an energy-based alternative but may become trapped in local minima. This paper proposes Langevin-dynamics hardware annealing to improve ground-state search.

  • I. INTRODUCTION: COP solution spaces can expand exponentially with variable count, challenging traditional computing paradigms.The resulting solution-time and hardware-resource demands become considerable.
  • I. INTRODUCTION: Ising machines map COPs onto low-energy search, reducing computation time and hardware requirements relative to exhaustive conventional search.CMOS-based digital and analog annealers are also associated with high solution quality and low power consumption.
  • I. INTRODUCTION: Ising machines may get trapped in local minima, degrading solution quality as spin count and solution-space size increase.Annealing algorithms are therefore studied to help the system escape local minima.
  • I. INTRODUCTION: Simulated-annealing techniques use digital spin-flip operations that store configurations, detect spin values, and randomly flip selected spins.These methods are widely adopted in digital annealers, whereas analog annealers follow a contrasting approach.
  • I. INTRODUCTION: The proposed physical hardware annealing algorithm uses Langevin dynamics, introducing stochastic perturbation through random noise.It is evaluated for all-to-all connected COPs at chip and behavioral levels.
  • A. Ising model: An Ising model represents coupled discrete spins whose energy decreases as spins align according to their interactions.Programmable coupling coefficients Jij and external fields hi allow the physical system to function as an energy-based COP computer.

B. Langevin dynamics

Langevin dynamics models particle motion under potential, friction, and random noise. Its stationary distribution favors lower interaction potentials, and reducing temperature increases the ground state's probability.

  • B. Langevin dynamics: Langevin dynamics models Brownian motion of particles with mass m in a potential U(x), incorporating friction and random impacts.The random force ξ(t) is described as zero-mean white noise, while β represents fluid friction.
  • B. Langevin dynamics: The Fokker–Planck equation describes how the joint probability density P(x,t) evolves for a Langevin-governed system.It provides the probability-distribution view used to analyze the dynamics.
  • B. Langevin dynamics: At steady state, the distribution is proportional to exp(−U(x)/kT), so lower interaction potential has higher probability.This stationary distribution connects the dynamics to preference for low-energy states.
  • B. Langevin dynamics: As temperature T approaches zero, the probability distribution of the ground state increases significantly.The annealing interpretation follows from progressively favoring lower-energy configurations.

C. Max-cut problem

The paper maps weighted max-cut to the Ising ground state and uses Langevin noise to explore solutions before reducing perturbations for convergence. The schedule combines strong initial exploration, gradual annealing, and final equilibrium.

  • C. Max-cut problem: Max-cut partitions weighted-graph vertices into two subsets while maximizing the total weight of crossing edges.
  • C. Max-cut problem: The max-cut objective maps exactly to an Ising model without an external magnetic field, making its solution the Ising ground state.
  • Langevin dynamics: Random noise is injected into the coupling-current summation path to perturb individual spins and produce the annealed spin output.
  • Langevin dynamics: Noise is scaled to each spin’s total coupled current, with the perturbation modeled using a Gaussian random variable.
  • Langevin dynamics: When noise dominates, spins fluctuate away from local minima and explore the solution space; when the Hamiltonian dominates, the system approaches equilibrium.
  • Langevin dynamics: The annealing schedule starts with κ > 1, gradually decreases κ, then stops noise injection so the system can converge toward equilibrium.

IV. HARDWARE IMPLEMENTATION

The hardware implementation applies the theoretical annealing design in a BRIM-based N-spin Ising machine, with dedicated system- and circuit-level components.

  • IV. HARDWARE IMPLEMENTATION: The implementation validates the proposed annealing algorithm on a comprehensive N-spin BRIM-based Ising machine.

A. System architecture design

The BRIM system combines off-chip problem handling with on-chip control, memory, annealing, and resistive-coupler computation. Its Langevin module tunes noise amplitude across coarse and fine controls while preserving coupling-current operation.

  • A. System architecture design: The architecture comprises an off-chip processor, on-chip control logic, a Langevin dynamics annealing module, on-chip SRAM, and BRIM.
  • A. System architecture design: The processor maps input problems and retrieves solutions, while central control initializes spins, configures couplers, runs annealing, and reads final states in a pipeline.
  • A. System architecture design: The Langevin module uses a noise generator, DC adjuster, and VGA, with 8-bit coarse tuning and 16-bit fine tuning for the annealing schedule.
  • A. System architecture design: The injected noise current does not affect spin input voltage because the spin input buffer has low input impedance.

B. Circuit level implementation

The Langevin-dynamics annealing hardware combines a thermal-noise source, DC adjustment, and variable-gain amplification to inject controllable noise into the Ising machine. Coarse and fine tuning set and gradually reduce the noise amplitude during annealing.

  • The noise generator comprises a noise source, DC adjuster, and variable gain amplifier.
  • Thermal noise from electronic components is amplified to adjustable levels for Langevin-dynamics annealing.
  • The DC adjuster biases the noise signal at 1/2Vdd, preventing continuous DC-current injection that could fix spins at a power rail.
  • The amplifier uses 8-bit coarse tuning for initial noise amplitude and 16-bit fine tuning to gradually decrease noise during computation.

V. PERFORMANCE EVALUATION AND ANALYSIS

The evaluation tests the proposed annealing algorithm on MAX-CUT problems at chip and behavioral levels. It examines solution quality, transient behavior, scalability, comparison with spin-flip annealing, and device-variation effects.

  • MAX-CUT problems are used as the simulation testbench because they map directly to the Ising formulation.
  • Chip-level: Chip-level evaluation uses a 50-spin BRIM implemented in commercial 65nm CMOS with analog circuit blocks and synthesized digital blocks.
  • Chip-level: Chip-level simulations analyze solution quality, transient response, layout, and area breakdown.
  • Behavior-level: Behavior-level simulations assess scalability on larger problems by comparing the proposed method with spin-flip annealing using BKS proximity and TTS.

A. Chip-level performance

Chip-level simulations evaluate ground-state attainment and BKS distance, transient convergence, and layout implications. The proposed hardware annealing substantially improves both solution probability and solution quality over the no-annealing case.

  • The chip-level figures cover probability and BKS distance, transient waveforms, and BRIM layout and area breakdown.
  • 86.5% probability of reaching the ground state improves on 17.5% without hardware annealing, nearly 5 times higher.
  • 97.5% improvement reduces average distance from the BKS from 11.4 without annealing to 0.28 with the proposed algorithm.
  • With noise amplitude initialized at 90µA and κ > 1 for every spin, the system explores energy states and reaches the ground state within the annealing schedule.
  • The chip layout places the noise generator beside spin current-summation ports, enabling direct noise-current injection and reducing interconnection overhead.

B. Behavior-level performance

Behavioral evaluation on a 2000-spin BRIM compares Langevin-dynamics annealing with spin-flip annealing across G-set MAX-CUT problems. Langevin dynamics achieves lower average BKS distance and a 50% TTS reduction at the same solution quality.

  • On 30 G-set problems, Langevin dynamics achieves an average distance from the BKS of 1.8 versus 2.6 for spin-flip annealing.Both methods use a 2.2µs annealing time, and each result is the best of 50 runs.
  • 50% reduction in TTS is achieved by Langevin dynamics while maintaining the same solution quality as spin-flip annealing.
  • The reported spin-flip comparison excludes spin-update time, which may underestimate its total time requirement.
  • The behavioral comparison includes cut-value distributions and annealing behavior for G022, plus average BKS distance across 30 G-set problems.

C. Device variation

Behavioral simulations tested injected-noise current variations of 3%, 5%, 10%, and 20% across annealing times for G022 and G039. The proposed hardware annealing remained resistant to PVT variation in the injected current.

  • 3%, 5%, 10%, and 20% variations were applied to the noise current magnitude in behavioral simulations for G022 and G039.Solution qualities were compared across different annealing times.
  • The proposed hardware annealing has robust resistance to PVT variation in the injected current.

VI. CONCLUSION

The proposed Langevin-dynamics hardware annealing algorithm demonstrates advantages over alternative algorithms. Simulations indicate that it helps escape local minima with a short time-to-solution and may enhance Ising-machine performance.

  • The proposed hardware annealing algorithm demonstrates promising advantages over alternative algorithms.
  • The algorithm effectively assists in escaping local minima with a short TTS.
  • The results suggest potential for enhancing Ising-machine performance.
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