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PICasso: An AI-Enabled Design Framework for Autonomous Optimization of Silicon Photonic Devices
Deepak Vungarala, Deniz Najafi, Abdulrahman Aljoudi, Zahra Ghanaatian, Navid Khoshavi, Gourav Datta, Arman Roohi, Mahdi Nikdast, Shaahin Angizi
TL;DR
PIC design automation must address fragmented workflows and the gap between syntactically valid LLM outputs and physically realizable circuits. PICasso combines structured, PDK-aware generation with verification and SAX-based optimization, evaluated on PIC-Set using task-level metrics. Across the benchmark, it improves specification satisfaction and reduces insertion loss while producing manufacturable layouts.
Problem
PIC design workflows are fragmented and manual, while existing LLM approaches often produce syntactically valid designs that are physically unrealizable or functionally incorrect.
Method
PICasso uses a PDK-aware NL→YAML→GDS pipeline with automated placement and routing, DRC/LVS validation, SAX simulation, closed-loop regeneration, and PIC-Set evaluation metrics.
Results
PICasso improves specification satisfaction across benchmark tasks, reaching 90.7% structural Spec@3 and 52.0% functional Spec@3 on Complexity-3 circuits, while reducing mean insertion loss from 4.98 dB to 3.25 dB.
Takeaways & Limitations
PICasso enables LLMs to generate manufacturable PIC layouts satisfying physical and functional constraints, with runtimes competitive with manual GUI-based workflows.
Abstract
from arXiv · showhide
We present PICasso, an AI-assisted framework for automated synthesis, verification, and optimization of photonic integrated circuits (PICs) from natural-language specifications. PICasso couples a structured NL -> YAML -> GDS generation pipeline with PDK aware knowledge injection, automated placement and routing, DRC/LVS validation, and SAX-based photonic simulation. To systematically evaluate AI-driven photonic design, we introduce PIC-Set, a benchmark of 36 parameterized PIC design tasks spanning core photonic primitives and multi-component circuits. Using PIC-Set, we benchmark several state-of-the-art Large Language Models (LLMs) under a unified evaluation protocol, including new metrics such as structural and functional $Spec@k$, optimization efficiency, and robustness under perturbations. Across the benchmark, PICasso significantly improves end-to-end specification satisfaction compared to vanilla LLM generation. Structural $Spec@3$ reaches up to 92.7% and functional $Spec@3$ up to 52% on high-complexity circuits. In addition, PICasso consistently reduces circuit insertion loss, lowering the mean loss from 4.98 dB to 3.25 dB (1.74 dB improvement) through simulation-guided optimization. These results demonstrate that structured domain constraints, physical verification, and simulation feedback transform LLMs from brittle netlist generators into practical PIC design agents capable of producing manufacturable layouts with competitive runtimes relative to manual GUI-based workflows.
I. INTRODUCTION
PICasso addresses fragmented, manually intensive PIC design workflows by combining structured constraints, verification, simulation, and benchmarked evaluation. The framework and PIC-Set aim to make LLM-driven PIC synthesis more reliable, manufacturable, and scalable.
- PIC design workflows remain fragmented across incompatible tools, forcing manual translation that introduces errors and delays time-to-market.
- Existing LLM-based PIC approaches rely on heuristic prompting, trial-and-error repair, and minimal domain knowledge, producing designs that may be syntactically valid but physically unrealizable or functionally incorrect.
- PICasso integrates structured YAML generation, PDK-aware knowledge injection, pilot validation, DRC/LVS verification, and closed-loop regeneration.
- PIC-Set contains over 36 parameterized component- and circuit-level design tasks for systematic evaluation of LLM-driven PIC design.
- PICasso introduces an automated two-stage optimization loop and metrics including structural and functional Spec@k and optimization efficiency.
- Together, PICasso and PIC-Set support reliable generation of manufacturable, optimized PICs when LLMs are paired with structured domain constraints and physical verification.
II. BACKGROUND
LLM use in hardware design has expanded across generation, optimization, and verification, but applications to PIC design remain sparse and often require substantial expert intervention. AI-driven simulation loops nevertheless suggest a path toward reducing manual tuning and exploring broader design spaces.
- LLM hardware-design systems automate HDL/HLS generation, verification, repair, and simulation-guided optimization across RTL-to-GDSII workflows.
- AI-driven, simulation-based loops can reduce manual expert tuning and enable broader exploration of the design space.
- PIC research remains limited to preliminary efforts such as LLM-generated FDTD scripts and AI-based photonic-device optimization.
- Earlier PIC workflows were not fully autonomous because experts defined specifications and iteratively corrected coding errors.
III. PICASSO
PICasso maps high-level photonic intent to manufacturable, PDK-compliant layouts through constrained generation and feedback-driven refinement. Its pipeline uses structured specifications to restrict outputs and automatically converts detected violations into corrective constraints.
- PICasso is an automated, constraint-driven synthesis pipeline from high-level photonic intent to manufacturable, PDK-compliant layouts.
- Prompt-constrained generation supplies structured, domain-informed specifications that restrict the LLM output space to valid photonic circuits.
- Feedback-driven refinement identifies syntactic, semantic, and physical violations and translates them into corrective constraints for iterative regeneration.
A. Framework
PICasso augments natural-language circuit descriptions with PDK knowledge, validates generated YAML, compiles layouts with automated placement and routing, and applies physical checks before optimization. Compared with prior frameworks, it combines these stages in a single closed loop.
- Framework: Knowledge injection augments circuit specifications with YAML grammar, PDK component and port definitions, admissible parameters, spacing rules, and canonical examples.
- Framework: Pilot validation checks formatting, schema compliance, parameter use, port consistency, spacing, and placement or routing completeness before execution.
- Framework: YAML compilation instantiates components, performs geometric placement, and invokes automated routing that respects bend-radius, cross-section, and PDK spacing constraints.
- Framework: Physically validated designs enter SAX-based optimization for geometry tuning and circuit-level phase and coupling refinement toward lower insertion loss and improved balance.
- Framework: PICasso uniquely combines structured NL→YAML generation, PDK constraints, automated placement and routing, full physical verification, and spectrum-driven optimization in one closed loop.
B. PIC-Set: A Curated PIC Benchmark
PIC-Set is a curated benchmark of parameterized silicon-photonic primitives and circuits built under a unified technology and simulation stack. It supports consistent evaluation through standardized layouts, constraints, models, and topology-level splits.
- PIC-Set covers photonic primitives commonly used in modulators, WDM filters, and switching fabrics.Examples include MMIs, directional couplers, phase shifters, Y-branches, and waveguide tapers.
- Parameterized generation enforces consistent parameter ranges, layout conventions, and PDK assumptions across circuit instances.
- PIC-Set entries include literature-derived target loss budgets for representative circuits.Examples include approximately 1.3 dB for ring add-drop filters, 2.2 dB for 16-channel AWGs, and 0.7 dB for 2 × 2 thermo-optic switches.
- Topology-level partitioning prevents leakage across parametrically similar circuits and provides separate design, validation, and test splits.Entries include YAML netlists, reference GDS/OASIS layouts, parameter bounds, structural constraints, and applicable circuit models.
C. Optimization Framework
PICasso separates device-level geometry tuning from circuit-level transmission refinement. It uses empirical or PDK targets for local optimization and SAX-based simulation with multistart Nelder–Mead for circuit optimization.
- PICasso uses a two-tier optimization strategy for device performance and circuit-level transmission behavior.The separation treats local component refinements and global interference effects distinctly but cohesively.
- Device-Level Optimization: Device-level optimization adjusts geometry and material parameters to match empirical measurements or PDK performance specifications.The resulting configuration is intended to more closely follow expected foundry behavior.
- Circuit-Level Optimization: Circuit-level optimization uses SAX simulations to tune phase shifts and coupling coefficients across the layout.These variables shape multi-path interference in the full PIC.
- Circuit-Level Optimization: Multistart Nelder–Mead uses several random initializations to avoid shallow local minima while minimizing insertion loss.The objective maximizes the squared dominant singular value of the circuit transfer matrix while preserving functional mapping.
IV. EVALUATION METRICS
PICasso evaluates generated circuits through structural validity, functional behavior, and optimization efficiency rather than binary or syntax-only correctness. The metrics are designed to distinguish physically valid, functionally compliant, and improved layouts across benchmark tasks.
- Structural specification satisfaction checks YAML parsing, compilation, routing, and other structural constraints imposed by the DSL, PDK, and layout engine.The metric addresses limitations of binary pass/fail and syntax-only benchmarks.
- Functional specification satisfaction tests SAX-simulated behavior against topology-specific tolerances from PIC-Set.Criteria include power transfer, insertion-loss trends, wavelength selectivity, and applicable switching or splitting ratios.
- Optimization efficiency measures normalized insertion-loss reduction between the initial and optimized layouts.It uses IL_before and IL_after, adds ε = 10^-6 to avoid near-zero denominators, clips the result to [0, 1], and averages structurally valid circuits.
V. EXPERIMENT RESULTS
Across 36 PIC-Set tasks, PICasso improves structural and functional specification satisfaction across models and complexity tiers, while supporting broader validated circuit synthesis with competitive runtimes.
- PICasso improves structural and functional specification satisfaction across all evaluated models and complexity tiers.
- 90.7% structural Spec@3 and 52.0% functional Spec@3 are achieved on Complexity-3 circuits under PICasso.Vanilla generation fails to produce functionally correct designs on these large circuits.
- 100% structural Spec@3 and 100% functional Spec@3 are achieved by Claude Sonnet 4.5 on Complexity-2 tasks.
- PICasso produces manufacturable layouts satisfying physical and functional constraints, rather than merely unreliable circuit-generator outputs.
- PICasso supports 36 tasks, including 12 previously unsupported circuits, with full physical validation, spectral evaluation, and optimization.Its runtime remains competitive with prior multi-agent frameworks despite deeper validation.
A. Optimization analysis
The optimization analysis compares initial losses among structurally valid vanilla and PICasso circuits, while the pipeline contribution table isolates successive validation and optimization stages.
- 48 vanilla and 158 PICasso circuits remain after identical structural-pass and file-availability filtering across five LLM back-ends.The retained samples must instantiate from YAML and pass DRC checks, with evaluable YAML or GDS files.
- 6.13 dB is the reduction in median initial circuit loss, dropping from 6.85 dB to 0.72 dB for PICasso.The reduction reflects many PICasso-generated circuits with near-zero insertion loss.
- 100% structural correctness is reached from V3 onward, while functional Spec@5 remains undefined through V1–V3 by design.V3 adds pilot validation; V4 adds DRC/LVS/SAX, and V5 is the full PICasso pipeline.
- 25–60 minutes are required by prior workflows, compared with 4–8 minutes for PICasso tasks.PICasso maintains competitive runtimes while performing deeper pipeline steps than netlist- or schematic-level baselines.
B. Demonstration of PICasso
The pipeline contribution analysis shows that validation stages progressively convert generated PIC designs into structurally and functionally evaluable outputs.
- 25–42% structural correctness and zero functional Spec@5 are reached by raw and knowledge-injected generation in V1–V2.Outputs routinely fail port-consistency and routing checks before reaching the layout engine.
- 100% structural correctness is reached across all tiers with pilot validation alone in V3.
VI. CONCLUSION
PICasso combines an end-to-end LLM-driven PIC design framework with a 36-task benchmark and evaluation metrics for synthesis, verification, and optimization. Across models, it improves specification satisfaction, reaches perfect Spec@3 for lower-complexity tasks under Claude Sonnet 4.5, reduces insertion loss, and operates faster than manual GUI workflows, while phase-sensitive high-complexity circuits remain challenging.
- Framework: PICasso couples a PDK-aware NL→YAML→GDS pipeline with DRC/LVS checks, SAX simulation, and two-stage optimization for manufacturable PIC generation.The framework supports autonomous synthesis, verification, and optimization from natural-language intent.
- Evaluation: The 36-task PIC-SET benchmark and Spec@k and optimization-efficiency metrics enable reproducible evaluation across models, topologies, and complexity tiers.
- Results: Mean insertion loss falls from 4.98 dB to 3.25 dB, a 1.74 dB improvement, with tasks completed in 4–8 minutes versus 25–60 minutes manually.
- Limitations: Functional failures persist on phase-sensitive high-complexity circuits such as 64-QAM and 90° hybrids because Nelder–Mead convergence is insufficient.Gradient-based or learned-surrogate optimization is identified as the primary open direction.