PaperlayerView exact revision on arXiv

Source-linked AI summary

Ankhdjet: An Open-Source Compiler for Mask-Programmed Ternary Compute-in-ROM on an Open PDK

Mohnish Pai

arXiv:2608.26206v1cs.ARcs.ET

TL;DR

Open infrastructure has not yet made model-specific compute-in-ROM silicon reproducible from ternary checkpoints through fabrication-ready signoff. Ankhdjet compiles HuggingFace ternary weights into via-mask programs for a SKY130 compute-in-ROM macro and achieves open-tool signoff twice with different masks, while submitting a fabrication vehicle.

  • Problem

    The paper asks whether ternary model-specific silicon can be made reproducible with entirely open infrastructure.

  • Method

    Ankhdjet compiles HuggingFace ternary checkpoints into via-mask programs for a fixed SKY130 compute-in-ROM macro and adversarially verifies each assembly level.

  • Results

    The flow achieves KLayout DRC zero, netgen LVS zero, and clean timing twice with different weight matrices, while the digital readout uses one eighth the analog area.

  • Takeaways & Limitations

    Ankhdjet demonstrates that a ternary model can become an open, reproducible mask-set artifact on a fabricable open PDK.

  • Takeaways & Limitations

    No silicon measurements or measured energy results are available because the fabrication vehicle is still awaiting return and reported energy is simulated.

Abstract

from arXiv · show

Large-language-model inference is dominated by weight movement: every generated token re-reads every weight. Ternary quantization (BitNet b1.58) shrinks each weight to 1.58 bits with reported parity at the 2B-parameter scale, small enough that hardwiring the weights into a read-only mask becomes plausible, and a commercial chip (Taalas HC1) has validated hardwired weights on an advanced node behind closed tooling. This paper asks whether model-specific silicon can be made reproducible with entirely open infrastructure. We present Ankhdjet, an open-source compiler that lowers a HuggingFace ternary checkpoint (BitNet b1.58 and its kin) to a via-mask program of a fixed compute-in-ROM macro on the open SKY130 PDK, verified end to end with open tools. We defend two claims: (1) the first open-source weights-to-mask compute-in-ROM compiler on a fabricable open PDK, taken through full open-toolchain signoff (KLayout DRC zero, netgen LVS zero, clean timing) twice with two different weight matrices through an identical flow in which only the mask differs; and (2) the first compute-in-ROM macro submitted for fabrication on an open PDK (TinyTapeout/ChipFoundry SKY130 shuttle ttsky26c, silicon expected 2027). The compiler's read is fully digital (full-swing bitline sampling into standard cells, so the emission ports to any node by synthesis); an analog comparator readout of the same machine is retained as a measured variant, replaced by the digital readout at one eighth the area. We additionally report the per-level adversarial verification methodology that caught three DRC-invisible silent shorts, a negative result on storing two ternary weights per transistor at 130 nm, and which analog sense techniques survive at which nodes. Read energy is from extracted-parasitic simulation (0.98-1.73 pJ per sensed weight); no energy measurements are claimed, and the fabricated vehicles are demonstrators.

I. INTRODUCTION · II. RELATED WORK

Autoregressive inference repeatedly moves all model weights, motivating ternary hardwiring as model-specific silicon. Ankhdjet addresses reproducibility by compiling HuggingFace ternary checkpoints into via-mask compute-in-ROM macros on the open SKY130 PDK and supporting open verification, while limiting energy claims to extracted-parasitic simulation.

  • I. INTRODUCTION: Each generated token re-reads the entire weight set, so energy and latency depend on weight movement when edge batch sizes provide no reuse.DRAM and on-chip SRAM both impose per-token weight-movement costs.
  • I. INTRODUCTION: 1.58 bits per weight makes ternary values suitable for structural storage as positive, negative, or disconnected transistor connections, while removing multiplication.BitNet b1.58 trains weights in {−1, 0, +1} with per-tensor scales; its 2B4T release reports quality comparable to similar-size full-precision peers.
  • I. INTRODUCTION: Ankhdjet compiles a HuggingFace ternary checkpoint into a via-mask program for fixed compute-in-ROM macros on the fabricable SkyWater SKY130 open PDK.The stated goal is a reproducible artifact that can be regenerated, re-verified, and submitted to a foundry shuttle.
  • I. INTRODUCTION: The compiler’s first novelty claim is full open-toolchain signoff twice with different weight matrices, byte-identical configuration, and only the mask changed.The reported signoff includes KLayout DRC zero, netgen LVS zero, and clean static timing.
  • I. INTRODUCTION: Three DRC-legal silent shorts were caught by flat-extracting each hand-assembled structure and comparing it with its generated transistor-level schematic.This methodology targets errors that chip-level structural signoff cannot see.
  • I. INTRODUCTION: The paper reports energy and power only from extracted-parasitic simulation and labeled vectorless reports, with nothing measured and no measured-silicon efficiency victory claimed.Numbers are distinguished by provenance, including signoff runs, simulation corners and extraction levels, and calibrated model estimates.
  • II. RELATED WORK: Ankhdjet is positioned at the intersection of three research threads, with prior work and the compiler’s boundaries summarized explicitly in Table I and the accompanying discussion.The related-work section states what each prior work established and what Ankhdjet does and does not claim beyond it.

A. ROM-Based Compute Architectures … D. Taalas

The paper positions Ankhdjet against prior ROM-based compute, open CIM compilers, open-PDK accelerator silicon, and Taalas’s commercial hardwired-model architecture. These precedents establish the architectural, automation, silicon, and commercial context for Ankhdjet’s open experiment.

  • A. ROM-Based Compute Architectures: 16 nm FinFET 1T ROM and 40 nm 16 Mb contact-programmed mask ROM provide modern anchors for dense, manufacturable ROM.Computing in ROM is newer, with DCiROM providing fully digital compute-in-ROM macros for task-level DNN inference.
  • A. ROM-Based Compute Architectures: BitROM is identified as the closest prior work, defining a ternary compute-in-ROM architecture with one-transistor cells storing two ternary weights each.The passage positions BitROM as the direct architectural predecessor to this paper.
  • B. Compute-in-Memory Compilers: OpenC2 and OpenACM establish that compute-in-memory macro compilation can be open, while AutoDCIM and SynDCIM demonstrate automated CIM macro generation.SynDCIM adds performance-aware subcircuit synthesis and validates with a 40 nm test chip.
  • C. Accelerator Silicon on Open PDKs, and Ternary Silicon: OpenSpike taped out a spiking neural-network accelerator on SKY130 with OpenRAM memories and a fully open flow before this work.This established open-EDA neural-accelerator tapeout precedent on an open PDK.
  • C. Accelerator Silicon on Open PDKs, and Ternary Silicon: TT06 and TT09 implemented BitNet-style 1.58-bit matrix multipliers as digital logic, but both held weights in runtime registers.Slim-Llama additionally demonstrated a fabricated binary/ternary LLM processor at ISSCC 2025.
  • D. Taalas: Taalas HC1 hardwires an 8B-parameter model into an N6 die using roughly 53 B transistors, with model swaps confined to two metal masks.Public statements also describe a mask-programmable 1T cell with via-selectable bitline connection.
  • D. Taalas: The designs differ in implementation scope: Taalas uses N6 and closed artifacts, whereas Ankhdjet uses a minimum viable node and an entirely open artifact set.The passage explicitly characterizes these choices as opposite experiments.
  • D. Taalas: Taalas and Ankhdjet place parameters in mask ROM, read them locally once per token, use weight-free digital units for other decode operations, and retain the KV cache in writable memory.The KV cache is the one block that cannot be converted into masks through area alone.

III. THE COMPILER AND THE MASK-ONLY CONTRACT … C. Backend: The RTL View

Ankhdjet converts ternary HuggingFace checkpoints into a self-contained design bundle containing per-layer mask programs, RTL, and physical collateral. Its backend separates model-specific via-mask programming from fixed, pre-verified RTL structure while preserving standalone elaboration, simulation, and verification.

  • III. THE COMPILER AND THE MASK-ONLY CONTRACT: The compiler is a pip-installable Python package that converts a checkpoint into a digest-covered design bundle for placement and checking.The bundle contains per-layer mask programs, a self-contained RTL view, and per-shape physical abstracts of the assumed macro.
  • A. Frontend: Checkpoint to Ternary IR: The frontend accepts HuggingFace checkpoints with ternary matmul weights, including BitNet b1.58, through configuration-only or full-weight ingestion paths.The full-weight path decodes safetensors payloads while detecting storage format per tensor; three formats are supported.
  • A. Frontend: Checkpoint to Ternary IR: The bf16-tied output projection remains off-fabric and is recorded as an off-fabric parameter count rather than silently omitted or included.This guardrail reflects that the embedding-tied table is not ternary silicon.
  • A. Frontend: Checkpoint to Ternary IR: A layer with unloadable weights retains correct dimensions behind a loudly flagged placeholder, enabling area estimation while blocking emission and verification.This preserves dimensional accounting without allowing an unverifiable layer into the generated design.
  • B. Backend: Mask Programs: The backend tiles each N × M ternary matrix into macro-shaped chunks, zero-pads ragged edges as physical zero weights, and emits +/-/0 mask matrices.The mask text is the physical interface: the array generator uses it to select each cell’s via and jog choice, making it the per-model mask difference.
  • C. Backend: The RTL View: The SystemVerilog backend emits instances and parameters only; all behavior resides in a hand-written, pre-verified RTL library.Consequently, compiler bugs can mis-parameterize pinned modules but cannot manufacture novel logic.
  • C. Backend: The RTL View: The emitted bundle includes copied library sources, behavioral .memh mask views, a parameterized smoke bench, and a file list for standalone elaboration and simulation.A digest manifest covers the complete bundle, and checkpoint-to-RTL names are legalized and collision-checked at the emission boundary.

D. Physical Abstracts and PDK Packs · E. The Invariant: Weights Live Only in the Mask · F. Bit-Exact Reference Chain

Ankhdjet packages shape-specific physical abstracts from independently declared PDK capabilities while ensuring weights alter only via-mask finishing geometry. Numerical correctness is enforced through four exactly compared models, with RTL and physical artifacts tied to each weight matrix.

  • D. Physical Abstracts and PDK Packs: Each compiled shape receives a LEF footprint, Liberty timing and power view, and blackbox Verilog abstract generated from its PDK pack.The pack is a data-only directory whose manifest independently declares optional estimator, abstract-generation, and physical-collateral capability tiers.
  • D. Physical Abstracts and PDK Packs: PDK packs resolve through environment paths, installed package entry points, or the bundled copy, allowing private commercial packs without compiler changes.Restricted-pack status propagates into emitted manifests, and hardened binding re-emits identical grid tops over per-chunk physical collateral.
  • E. The Invariant: Weights Live Only in the Mask: A weight matrix changes exactly one artifact: the array’s via-1/metal-jog finishing geometry; placement, circuitry, abstracts, floorplan, and flow configuration remain invariant.One verified abstract serves every same-shape variant, making model recompilation a mask respin rather than a re-implementation.
  • E. The Invariant: Weights Live Only in the Mask: The mask encodes +1 with BL+, −1 with BL−, and 0 with no drain via, while all other terminal roles and masks remain identical.This invariant was exercised through two signoffs for two matrices using one flow.
  • F. Bit-Exact Reference Chain: Numerical correctness uses four models compared by exact integer equality without tolerance, forming a descending reference chain from software to hardware.The chain anchors correctness at PyTorch F.linear and then validates progressively more implementation-specific representations.
  • F. Bit-Exact Reference Chain: The pure-math oracle validates ternary unpacking and bit-serial decomposition, while the hardware-order oracle mirrors row-sequential physical readout and accumulation.The discarded parallel-wordline abstraction was impossible with 1T cells; the row-sequential model is the RTL’s ground truth.
  • F. Bit-Exact Reference Chain: Verilator simulates emitted SystemVerilog cycle-by-cycle against the hardware-order reference, extending exact comparison through RTL.The physical flow also emits each matrix’s mask program and transistor-level schematic for extracted-netlist matching.

IV. THE SKY130 CIROM MACRO … C. Digital Readout of Record: Full-Swing Sampling

The SKY130 CiROM macro uses a 1T NOR array with clocked precharge and full-swing digital sampling for parallel ternary-weight reads. Its silicon-verified configuration contains 2,048 weights, while the digital readout replaces comparator bands at substantially lower area.

  • IV. THE SKY130 CIROM MACRO: The 1T NOR topology places cells in parallel between each bitline and ground, enabling a selected row to discharge every selected column independently in one step.This supports the full-parallel random-row read required by the per-token matrix-vector operation.
  • IV. THE SKY130 CIROM MACRO: 2,048 ternary weights occupy a 64×32 array read through a five-state cycle at a 25 ns clock, or 125 ns per read.The configuration exercises the complete architectural path, including 64-row one-hot decoding and 32 columns.
  • A. Bitcell: 2.21 µm2 per ternary weight is achieved with a single NMOS cell at 1.70 µm × 1.30 µm pitch.Mask geometry routes +1 to BL+, −1 to BL−, and leaves 0 floating; adjacent-jog abutment rules arose from a caught silent short.
  • A. Bitcell: 0.54 ns and 1.07 ns are the selected-cell discharge times to 0.9 V and 0.3 V, respectively, against an 8 ns evaluate state.These measurements at ss, 100°C, 1.62 V provide better-than-4× margin on every read timing constraint; extracted wire-only bitline capacitance is 27–37 fF.
  • B. Clocked Precharge, No Keeper: 21.7–43.3 ns is the slow-corner time for static pseudo-NMOS pull-ups to recharge to 90% of the rail, exceeding the 25 ns cycle.The macro therefore uses clocked PMOS precharge, which parks both bitlines at the rail while idle.
  • C. Digital Readout of Record: Full-Swing Sampling: 68 µm2 per weight column is the digital sampling-logic area, versus 540 µm2 for the comparator bands it replaces.Each bitline uses one input buffer and one capture flop; the strobe clocks the flop after a discharged bitline crosses the buffer threshold.
  • C. Digital Readout of Record: Full-Swing Sampling: Full-swing digital sampling is sufficient for ternary reads because a single one-hot row drives each line, eliminating the comparator mismatch tax.The read FSM’s strobe captures the buffer output after the bitline crosses its switching threshold within the evaluate state.

D. Analog Variant: Why Two Single-Ended Comparators per Column … V. VERIFICATION METHODOLOGY

The analog variant uses comparator-based ternary sensing whose offset and loading constrain correctness at 130 nm. The verification methodology independently flat-extracts each assembled level, catching DRC-invisible shorts and flow errors before signoff.

  • D. Analog Variant: Why Two Single-Ended Comparators per Column: A differential comparator cannot represent ternary zero: when both bitlines remain high, latch offset resolves the near-zero differential to a random but column-coherent ±1.The three read outcomes are BL+ discharged (+1), BL− discharged (−1), or neither (0); complementary comparator outputs never equal (0, 0).
  • D. Analog Variant: Why Two Single-Ended Comparators per Column: At 130 nm, minimum-size comparator inputs have σoffset ≈130 mV, exceeding the ±50 mV reference-accuracy budget; larger devices close the mismatch gap.The implemented input pair is W = 8 µm, L = 2 µm, with 16 µm^2 gate area per device.
  • D. Analog Variant: Why Two Single-Ended Comparators per Column: About 150 fF of routed output load flips latch decisions at the extracted slow corner, so the Liberty view limits HIT pins to 60 fF and places buffers beneath them.The issue arises because the latch races two output nodes while the internal complement node is nearly unloaded.
  • E. The Analog Sense Band: Sixteen comparators form a flat-verified sense band measuring 59.3 µm × 73.0 µm, or about 270 µm^2 per comparator including shared rails.Metal-3 risers carry the band’s buried bitline, VREF, strobe, and HIT pins to the macro boundary for routing and extraction.
  • V. VERIFICATION METHODOLOGY: Each hand-assembled level receives independent Magic flat extraction and netgen comparison against a generated transistor-level schematic, from bitcell through full chip.The methodology treats every assembled structure as an independent connectivity claim requiring its own adversarial check.
  • V. VERIFICATION METHODOLOGY: Three DRC-legal, chip-signoff-invisible shorts were caught: neighboring BL+–BL− mask-jog abutment, well-to-comparator diffusion merging, and all 16 HIT outputs shorted to VDD.Macro- or band-level flat LVS exposed each defect and drove corresponding mask or layout fixes.
  • V. VERIFICATION METHODOLOGY: Flow checks prevented analog corruption: an analog-aware SDC and dont-touch removed an inserted clock buffer from VREF, while realistic capacitances corrected buffering of 130 fF-class analog pins.The final VREF netlist has zero gates on it.
  • V. VERIFICATION METHODOLOGY: KLayout’s full SKY130 DRC deck is authoritative, while Magic over-approximation is calibrated against shipped analog and digital shuttle designs; fills and ECOs remain in-flow.The calibration measured 544 Magic items on a shipped analog design and 83,174 on a shipped digital design, all in wide-metal spacing.

VI. RESULTS · A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles

Ankhdjet completed full-chip open-toolchain signoff twice with different weight matrices, changing only the mask-programming geometry. Both analog-comparator and digital-standard-cell readout variants passed the same core verification flow with clean timing and functional regression.

  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: 0.85 mm × 0.30 mm: the analog signoff vehicle integrates a 64 × 32 array, clocked precharge, 64 comparators, external VREF, and a read FSM.The vehicle runs at a 25 ns clock.
  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: KLayout DRC zero and netgen LVS zero: the analog vehicle also reports zero max-slew, max-capacitance, and max-fanout violations.Netgen reports that the circuits match uniquely.
  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: +16.2 ns setup slack and +0.13 ns hold slack: the analog vehicle meets worst-corner timing at min_ff_n40C_1v95.Nominal TT hold slack is +0.36 ns.
  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: Twice: checkerboard and committed seeded sparse matrices pass through identical configuration, floorplan, abstracts, constraints, and signoff flow, with only mask geometry changing.The sparse test0 matrix contains 500 cells of +1, 513 of −1, and 1,035 of 0.
  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: Any {+, −, 0} matrix of the required shape compiles to the same signoff, because the weight file changes only the generated mask-programming geometry.The two demonstration matrices are test patterns.
  • A. Full-Chip Signoff: Mask-Only Delta, Both Readout Styles: +16.3 ns setup slack and +0.11 ns hold slack: the digital variant replaces comparator bands and VREF with full-swing bitline samplers in standard cells.It preserves identical die, array placement, clock, and read contract, while achieving netgen LVS zero, zero signal-integrity violations, and green regression on both matrices.

B. The Fabrication Vehicles · C. Area Accounting · D. Estimator Methodology

The paper reports open-toolchain fabrication vehicles with clean signoff and controlled digital-versus-analog readout comparisons, while area accounting shows sense periphery dominates at 64 rows. Cross-PDK area and throughput estimates are generated by a calibrated estimator chain with explicit architectural and performance components.

  • B. The Fabrication Vehicles: 10,501 µm2 of routed logic sits beside the same 5,345 µm2 array macro in the digitally hardened vehicle.The vehicle achieved KLayout DRC zero, uniquely matching netgen LVS, and clean static timing at all nine corners.
  • B. The Fabrication Vehicles: Identical array, programming layer, and test0 mask make readout style the only variable between the digital and analog vehicles.The digital vehicle computes ternary matrix-vector products on die from host-streamed activations, without an on-die activation store.
  • B. The Fabrication Vehicles: 161 µm × 225.76 µm is the analog vehicle’s 1×2 tile footprint, carrying one 64×32 array with 2,048 mask-programmed weights.All 64 row signatures are distinct against the committed test0 matrix, supporting address-decode fault testing.
  • B. The Fabrication Vehicles: 14 of 15 shuttle prechecks pass for the analog vehicle, with routing DRC zero, full-deck KLayout cleanliness, and fully classified LVS.The remaining precheck is attributed to Magic; the residual anonymous p-substrate LVS class is verified benign because substrate ties to ground.
  • C. Area Accounting: 3.4× is the sense-periphery tax at 64 rows per bitline: two comparators per column cost about 540 µm2 versus about 160 µm2 for the column array.Because the tax is fixed per column while the array grows with row count, rough parity is reached at 256 rows.
  • D. Estimator Methodology: Five terms form the cross-PDK area model: programmed cells, periphery, KV-cache SRAM, a fixed-function attention engine, and die overhead.Periphery is anchored by synthesizing the actual controller and accumulator RTL against each node’s libraries, while each readout tier prices its own sense circuitry.
  • C. Area Accounting: ≈2.5N µm2 is the per-column array cost at N rows, derived from the 2.21 µm2 cell and one-in-eight tap row.This relationship is recorded in the SKY130 as-built area accounting.
  • D. Estimator Methodology: Three independently back-fitted knobs dominate the cycle model: clock derate, inter-layer wire-transport cycles, and KV-access cycles.They draw respectively on open-PDK tapeout and placed-clocked anchors, published interconnect scaling data, and foundry SRAM datasheets plus OpenRAM.

E. Cross-PDK Model Estimates

Calibrated cross-PDK estimates show that readout choice and periphery dominate model-scale area, while the same frontend successfully exercises broad ternary-checkpoint coverage with explicit unsupported-scale handling.

  • Cross-PDK model estimates: 14% of total area is attributed to the cell and BiROMA-bound anchor at the 22M-parameter reference shape, indicating periphery-dominated SKY130 area.The estimates are calibrated outputs, not measurements.
  • Cross-PDK model estimates: 285 mm2 is the estimated digital-tier area versus 458 mm2 for the analog tier at the same shape and anchor.The readout tier is therefore a first-order area term at model scale.
  • Cross-PDK model estimates: 23M parameters is the largest shape fitting an 815 mm2 die budget at the as-built 130 nm anchor.The implementation’s stated value is reproducibility and contract validation rather than deployment density.
  • Checkpoint coverage: 6,912 mask programs in the TriLM design bundle audit bit-exact against its checkpoint, and its RTL elaborates standalone.The frontend’s modelagnosticism is exercised through published ternary releases from five organizations.
  • Checkpoint coverage: 7.0 B ternary weights are completely decoded by the largest packed release, while unsupported per-tensor scaling is refused with a diagnosis.Faithful support requires per-group scaling because the scale grid cannot be carried by a per-tensor scale.

F. Simulated Read Energy, Power, and Throughput

The section reports capacitance-extracted dynamic read energy and corner-sensitive leakage, while deriving throughput arithmetically from the verified FSM and signoff clock. It finds recharge-dominated energy, substantial reference-current demand, and 8.0M row reads/s at full macro sense, reduced by tile serialization.

  • F. Simulated Read Energy, Power, and Throughput: Dynamic read energy is reported from switched-node capacitances with greater confidence than simulated timing because resistance extraction was unavailable.The deck evaluates the C-extracted 64 × 32 macro plus one sense-amplifier comparator pair at the FSM’s 125 ns five-state cycle.
  • F. Simulated Read Energy, Power, and Throughput: 3.66 pJ/V^2 implied switched capacitance per read corresponds to ≈1.1 pF across columns and reproduces the independently extracted ∼35 fF-per-bitline figure.Evaluate draws < 0.1 pJ because discharge dumps bitline charge to ground, while recharge restores the bitline charge.
  • F. Simulated Read Energy, Power, and Throughput: 5× idle-leakage variation from tt/27°C to ff/125°C accompanies a 0.24 µW cost for holding the array’s precharged bitlines.Rectified charge is 0.7–1.6 pC per comparator pair per cycle, corresponding to about 150 µA average rectified current through VREF at continuous tile-rate reads.
  • F. Simulated Read Energy, Power, and Throughput: 8.0M row reads/s and 256M weight reads/s result from five 25 ns states at full 32-column sense; tile serialization reduces this to 4.0M reads/s and 64M sensed-weight reads/s.The tile requires at least ten cycles per read, including five cycles of pin-budget overhead.

VII. TWO READOUT TIERS: A MEASURED COMPARISON · VIII. A NEGATIVE RESULT: TWO TERNARY WEIGHTS PER TRANSISTOR AT 130 NM

The digital readout is the measured correction to the analog tier, reducing area and simulated read energy while preserving the same digital compute machine. At 130 nm, storing two ternary weights per transistor fails in discharge-domain sensing and is uneconomic in voltage-domain periphery despite feasible core physics.

  • VII. TWO READOUT TIERS: A MEASURED COMPARISON: Both tiers implement identical digital bit-serial accumulation and differ only in converting a precharged bitline state into a sampled bit.The analog tier uses a clocked comparator against shared VDD/2; the digital tier waits for full swing and samples through an input buffer.
  • VII. TWO READOUT TIERS: A MEASURED COMPARISON: 8.0× area reduction replaces two 8,656 µm2 sense bands with 32 samplers synthesizing to 1,081 µm2.This corresponds to roughly 540 versus 68 µm2 per weight column.
  • VII. TWO READOUT TIERS: A MEASURED COMPARISON: 4–5× lower total read energy is obtained by the digital tier as built, because comparator power dominates the analog tile without partial-swing savings.Comparators account for 81% of the 19.2 pJ tile read, while the macro itself is 3.66 pJ.
  • VII. TWO READOUT TIERS: A MEASURED COMPARISON: Partial-swing analog energy savings remain hypothetical at production geometry and require early evaluation termination, which the fabricated design does not implement.The fabricated wordline holds through the strobe, so evaluation is not terminated early.
  • VII. TWO READOUT TIERS: A MEASURED COMPARISON: The digital alternative was built and measured before the analog necessity premise was retired, correcting the readout choice for ternary compute-in-ROM.Ternary removes the multiplier, while accumulation remains digital in this machine.
  • VIII. A NEGATIVE RESULT: TWO TERNARY WEIGHTS PER TRANSISTOR AT 130 NM: (E=−1, O=0) and (E=0, O=−1) are electrically indistinguishable in shared-minus discharge sensing, disproving the pitch-competitive variant structurally.Both configurations target {SM, G}; simulation shows discharge agreement within 5 × 10−11 V.
  • VIII. A NEGATIVE RESULT: TWO TERNARY WEIGHTS PER TRANSISTOR AT 130 NM: 0.184 V worst-case margin shows SKY130 voltage-domain core physics is feasible, but the required rails make the two-weight scheme uneconomic in periphery.The margin occurs at slow corner, 100◦C, with 63 off-cells loading the line; the estimated viability window is roughly 65–28 nm.

IX. SCALING AND NODE HANDOFFS · A. The ASAP7 Endpoint, Anchored

The paper maps compute-in-ROM scaling from SKY130 toward ASAP7 and 7 nm-class designs, where sensing overhead, analog techniques, and digital implementation determine the viable architecture. ASAP7 results are predictive estimates anchored by identical-flow synthesis and physical-design artifacts, not fabricable silicon.

  • IX. SCALING AND NODE HANDOFFS: At N=64, fully parallel sensing adds 3.4× overhead; approximate parity occurs at N=256 as fixed comparator area is amortized.The as-built design uses two ≈270 µm2 comparators per column, versus ≈2.5N µm2 of array area per column.
  • IX. SCALING AND NODE HANDOFFS: A 256-row bitline with 8:1 column-muxed single-ended binary sensing models a roughly 10–12% sense tax, pending unfinished mux-resistance simulation.The estimate is not silicon and follows mainstream 4–16:1 ROM compiler practice.
  • IX. SCALING AND NODE HANDOFFS: Offset oversizing, multi-level sensing, and other analog techniques each have node-specific limits, motivating handoffs as technology scales.Offset oversizing is described as ceasing to be appropriate at roughly 28 nm, where auto-zeroing becomes cheaper in area.
  • IX. SCALING AND NODE HANDOFFS: At 7 nm-class nodes, the endpoint is mask ROM storage, a small clocked binary sense amplifier, and synthesized digital accumulation and control.Ternary computation uses an AND gate and popcount, reducing the marginal benefit of analog accumulation.
  • A. The ASAP7 Endpoint, Anchored: ASAP7 is a predictive 7 nm proxy rather than fabricable silicon, with claims bounded by an estimator and identical-flow synthesis anchors.The digital-tier controller maps to 107.85 µm2 in ASAP7 RVT libraries versus 22,208 µm2 at SKY130.
  • A. The ASAP7 Endpoint, Anchored: The estimator places BitNet b1.58 2B4T’s 2.08B-weight ternary fabric with a 4096-token KV cache on 300–340 mm2 at 0.36–2.5M estimated tokens/s.These are calibrated model estimates, not silicon, and vary with bitline depth and activation width.
  • A. The ASAP7 Endpoint, Anchored: The reported rates are decode-fabric rates rather than system rates because bf16 lm_head and sampling remain on the host.At the 64-row/A4 point, the host head alone implies roughly 1.6 PFLOP/s sustained bf16; no system claim is made.
  • A. The ASAP7 Endpoint, Anchored: Mask-only programming creates a checkpoint-custody problem, while identical-transistor cells place the weight in via-1 and metal-jog finishing geometry.The paper identifies this as a security corollary but does not pursue it.

X. LIMITATIONS · XI. CONCLUSION

Ankhdjet’s open compiler establishes a reproducible ternary weights-to-mask path through SKY130 verification, while the paper clearly limits its evidence to signoff, extraction, and simulation before silicon returns in 2027. The conclusion frames the work as an open artifact and verification story rather than a deployable LLM chip.

  • X. LIMITATIONS: No silicon measurements exist yet; fabrication is pending, with silicon expected in 2027 and bench characterization deferred to follow-up work.Silicon-adjacent values are explicitly limited to signoff, extraction, or simulation.
  • X. LIMITATIONS: No measured energy is reported; read energy and leakage use capacitance-only extraction, while digital power is a vectorless ceiling.Analog figures omit resistive and short-circuit components, and no measured-silicon efficiency comparison is claimed.
  • X. LIMITATIONS: The analog vehicle demonstrates ternary-row reading rather than the MAC, whereas the hardened digital companion carries the matrix-vector product but remains unfabricated.The analog accumulation chain is Verilator-verified RTL in digital regression, not part of the analog silicon.
  • X. LIMITATIONS: 64 × 32 is the only silicon-verified macro shape; 128–256-row production geometry remains an extrapolation gated by validation.No deeper-bitline measurement exists for either readout style, and sense margins rely on extracted-parasitic simulation.
  • X. LIMITATIONS: At 130 nm, real models do not fit open shuttles, so the contribution is a reproducible compiler-to-silicon path and verification story, not a deployable LLM chip.This is the paper’s stated scale limitation.
  • XI. CONCLUSION: Ankhdjet compiles a HuggingFace ternary checkpoint into a via-mask program for a fixed, fully verified SKY130 CiROM macro and demonstrates both digital and analog readout tiers.The digital sampler replaces analog sensing at one eighth the area, while the same contract emits both tiers.
  • XI. CONCLUSION: The conclusion adds a bounded negative result for two-weights-per-transistor storage at 130 nm and maps where analog sense techniques expire.Silicon returns in 2027 will test extraction- and Monte-Carlo-supported sense margins and the analog tier’s remaining energy hypothesis.
Loading 2608.26206v1…