Source-linked AI summary

Distributed Training using an Intelligent Network

Nihar Shah, Ben Blier

arXiv:2608.26453v1cs.LGcs.DCcs.NI

TL;DR

Distributed training across WANs is constrained by bandwidth, latency, and topology, motivating a design that makes the network an active training participant. The paper combines multicast and FPGA-based aggregation with topology-aware synchronization scheduling, and reports that optimal schedules change with network capabilities while simulations demonstrate coupled benefits. The paper remains primarily theoretical because the DoubleZero network does not yet connect enough GPU clusters for full model training and peer comparison.

  • Problem

    WAN distributed training faces limited bandwidth, high latency, and uneven connectivity, making continuous parameter exchange difficult as training expands beyond individual data centers.

  • Method

    The paper combines WAN multicast for replicating outbound updates, in-line FPGAs for aggregating inbound streams, and an optimization framework for topology-aware rotating-clique synchronization schedules.

  • Results

    The simulations show that optimal synchronization schedules change as the network’s capabilities change, while multicast and FPGA aggregation enable faster exchanges and lower GPU idling time.

  • Takeaways & Limitations

    The combined systems and algorithms design offers a self-contained approach for distributed training on programmable WANs and can narrow the gap to colocated training.

  • Takeaways & Limitations

    The evaluation is primarily theoretical because DoubleZero does not connect enough GPU clusters for earnest model training or comparison with peer systems.

Abstract

from arXiv · show

Distributed training across a wide area network (WAN) is challenging, as continuous parameter exchange by islands of compute is constrained by limited bandwidth, high latency, and uneven topology. We propose making the network an active participant in training. On the systems side, such networks should leverage (i) multicast technology to replicate outbound traffic and (ii) in-line FPGAs to aggregate inbound traffic, to ease egress and ingress bottlenecks. These technologies are used for training across workers within a data center, but this paper extends them to the WAN. On the algorithms side, we develop an optimization framework that produces rich synchronization schedules (namely, rotating cliques of islands) around the underlying network topology and these technologies, to maximize information exchange. Finally, we illustrate this on a nine-city topology modeled on the DoubleZero network, a live programmable WAN equipped with both technologies, and show how the optimal schedules shift with the network's capabilities. Together, these can narrow the gap to the gold standard of colocated training.

1 Introduction

The paper proposes making the WAN an active participant in distributed training through network-assisted replication, aggregation, and topology-aware synchronization schedules. It combines these components in a self-contained design whose schedules adapt to network capabilities.

  • Motivation: Distributed WAN training is difficult because long, low-capacity, asymmetric links make synchronization a bottleneck and can leave workers idling.Existing approaches often synchronize less frequently, compress updates, or tolerate stale parameters.
  • Systems proposal: The systems proposal uses multicast to replicate model updates and in-line FPGAs to aggregate inbound streams across the WAN.Multicast reduces island egress pressure, while FPGA aggregation reduces ingress traffic and both operate at line rate.
  • Algorithms proposal: The algorithms proposal constructs rotating cliques from network topology and capabilities, trading off information transmission against synchronization time.The framework selects an efficient synchronization point rather than relying on schedules that largely ignore the network.
  • Illustrative design: In each round, islands are partitioned into disjoint cliques, with multicast replicating each sender’s stream and FPGA aggregation producing one merged access-link stream per receiver.The illustrated seven-island setup uses different clique partitions across rounds, including triangles, pairs, and a leftover triangle.
  • Combined proposal: The two components can operate independently, but the paper argues that using them together better exploits their potential.The proposal extends technologies previously used within data centers to WAN training and is illustrated on a DoubleZero-inspired setting.

2 Related Work

Prior distributed-training systems addressed WAN constraints mainly by changing communication frequency, volume, or completeness. This paper instead extends network-assisted aggregation and multicast to the WAN and embeds synchronization scheduling in network properties.

  • Aggregation systems: Centralized parameter servers became aggregation bottlenecks, motivating decentralized collectives such as ring all-reduce within data centers.Subsequent systems further optimized gradient aggregation inside a single data center.
  • Aggregation systems: PANAMA moved aggregation onto data-center FPGAs and distributed aggregated updates using multicast, but assumed colocated workers with negligible latency and plentiful bandwidth.The paper positions its contribution as extending this systems pattern to WAN conditions.
  • WAN challenges: WAN training introduces severe bandwidth and latency challenges, while naive data-center techniques do not directly transfer to links that are limited, asymmetric, and failure-prone.The cited discussion includes trillion-parameter exchange requirements on the order of ten terabits per second and millisecond-scale latency.
  • Algorithmic responses: Existing algorithmic responses communicate less often, communicate less volume, or communicate partially through methods such as federated averaging, DiLoCo, compression, and gossip.These approaches adapt training around constrained infrastructure rather than making the network itself an active participant.
  • Algorithmic responses: The paper’s algorithmic contribution lies in partial communication: it derives richer synchronization schedules from network topology and capabilities.This extends matching-based and gossip-inspired approaches toward schedules tailored to the WAN.

3 Network Technology

WAN training faces limited bandwidth, asymmetric connectivity, and high latency, so this section proposes network-assisted replication and aggregation to reduce ingress and egress pressure. It also describes how multicast, FPGA memory, and loss handling support the design.

  • Motivation: WAN training suffers limited bandwidth, asymmetric connectivity, and tens or hundreds of milliseconds of latency.These conditions make synchronization difficult compared with data-center training.
  • Multicast: Multicast lets each island send one outbound payload while the network replicates it downstream, relieving egress and core-network duplication.Replication occurs at distribution-tree branches rather than separately at the sender.
  • Reliability and accumulator functions: Multicast precludes TCP, so packet completeness requires loss handling such as sequence numbers, side-channel requests, or newer snapshots.The proposed design protects the post-aggregation hop with sequence numbers and a resend buffer; momentum remains outside the network.
  • FPGAs: FPGAs aggregate inbound streams at WAN edges so each receiving island gets a single stream over its ingress link.This extends data-center aggregation techniques to WAN training.
  • FPGAs: High-bandwidth FPGA memory supports aggregation when island streams arrive at different times, but memory capacity becomes an input to topology selection.The AMD Alveo V80 cited for DoubleZero carries 32 GB of high-bandwidth memory.
  • FPGAs: Each in-flight weight occupies an HBM slot keyed by hashed weight identifier and is forwarded when completion, timeout, or conflict triggers eviction.Conflicts can produce two partial sums, which the receiving island combines because aggregation is associative.

4 The Synchronization Schedule

The paper models WAN synchronization as rotating clique exchanges whose schedules are optimized for information diffusion under network constraints. It balances synchronization time against disagreement while incorporating topology, latency, serialization, and contention.

  • Synchronization schedules: The framework partitions islands into small, rotating cliques to structure information exchange instead of assuming all-to-all synchronization every step.Each clique averages member states, and rotating membership enables indirect propagation between islands.
  • Synchronization schedules: Each round is represented by an N × N mixing matrix W(k), with clique members assigned uniform mixture weights and non-members assigned zero weight.The exposition assumes block-structured matrices, though any non-negative symmetric doubly-stochastic matrix preserves the section’s logic.
  • Information diffusion: Products of successive mixing matrices trace how each generation’s parameter changes diffuse across islands through direct and intermediary transfers.The resulting Φ matrix records the weight island i holds from generation j after h synchronization rounds.
  • Objective function: The objective minimizes survival-curve error, measuring the disagreement remaining for each generation after synchronization and averaging across recurring schedule phases.Perfect diffusion would assign every entry of Φ the value 1/N; the normalized error starts at one for a newborn generation and declines toward zero through mixing.
  • Objective function: The schedule trades off round duration T against average lifetime disagreement A: longer rounds permit richer schedules, while shorter rounds restrict feasible synchronization patterns.Network quality affects both margins, and feasibility couples time and memory through shared offsets and clique stream rates.
  • Schedule feasibility: Feasibility is governed by cross-island latency and serialization, while concurrent cliques can contend for links and individual cliques can throttle themselves.Serialization is D/b, where D is payload size and b is the binding bottleneck rate; b depends on hardware and schedule-induced congestion.

5 System Simulation

The simulation evaluates four synchronization schedules on a nine-city DoubleZero-like WAN, showing that the best schedule depends on the network’s capabilities and the tradeoff between mixing quality and time.

  • Setting: The simulation models nine important cities with realistic latencies, 100 Gbps links, 20 Gbps island ingress and egress, and a one-gigabyte model state.The topology is inspired by the DoubleZero network.
  • Illustrative Schedule: The rotating-triangles schedule mixes within regions first, then across regions, using cliques that connect all islands directly or indirectly within two periods.For example, New York and Tokyo exchange information through Los Angeles and Singapore rather than directly.
  • Illustrative Schedule: 565ms is the rotating-triangles schedule’s time cost, producing an objective score of 1271 milliseconds-error units under the no-FPGA-memory setup.The schedule’s objective combines average error per phase with the time required for the schedule to operate.
  • Optimizing Schedules: Across four schedules, all-to-all has perfect mixing, triangles ranks second, regional third, and pairs last because pairwise propagation traverses neighbors over multiple rounds.The four schedules are triangles, pairs, all-to-all, and regional.
  • Optimizing Schedules: 449ms makes pairs fastest and 477ms makes regional second-fastest, while all-to-all is infeasible without FPGA memory because arrival times cannot be coordinated.Triangles requires 565ms in this setup.
  • Optimizing Schedules: With 32 GB of FPGA memory, all-to-all becomes feasible at 676ms and scores best overall, whereas triangles is best in the no-memory setup.The optimal ordering therefore changes when network capabilities change.
  • Comparing to Synchronous SGD: Compared with synchronous SGD, the proposed system tolerates parameter staleness to reduce GPU idling, while multicast and FPGA aggregation further lower exchange time.Synchronous SGD has no staleness but makes GPUs idle 80% of the time; tolerating one second of staleness enables five-times-faster training.

6 Conclusion

The paper argues that WAN training should treat the network as an active participant through coupled systems and algorithmic innovations. However, the work remains primarily theoretical because the current DoubleZero deployment lacks enough GPU clusters for full training comparisons.

  • 6 Conclusion: The paper combines WAN multicast and FPGA technologies with an optimization framework for synchronization schedules.Multicast replicates updates, FPGAs aggregate inbound streams, and the framework derives schedules from network properties.
  • 6 Conclusion: The systems and algorithms components are designed together as a self-contained approach to distributed training.The paper states that the two components are built for each other and evaluates their coupling through simulations.
  • 6 Conclusion: The paper is primarily theoretical because DoubleZero does not yet connect enough GPU clusters to train a model in earnest or support peer-system comparisons.The authors identify closing the gap with colocated training as a next step.

A Model Extensions

The framework uses simplifying assumptions to remain tractable, but several assumptions can create inefficiencies and should be relaxed for real-world deployment.

  • A Model Extensions: The framework is simple and mostly symmetric, using uniform round lengths, homogeneous clique stream rates, completed exchanges, and uniform targets.These assumptions were introduced in the name of a tractable model.
  • A Model Extensions: Many core assumptions can and should be relaxed in real-world deployments because they create inefficiencies.The paper groups possible relaxations into time, routing, resource-sharing, hardware-placement, and resilience categories.
  • A Model Extensions: The paper enumerates these extensions without implementing them.The discussion presents them as directions for extending the model rather than evaluated features.

A.1 Time Efficiency

The core model imposes fixed, non-overlapping rounds so every exchange finishes before the next begins. Extensions allow schedules to match communication distances and overlap data movement.

  • A.1 Time Efficiency: Every round lasts T seconds, and every exchange must complete within that round.This is the core model’s simple notion of time.
  • A.1 Time Efficiency: Varying round lengths could alternate short-range and long-range mixing, using short rounds for adjacent islands and long rounds for distant islands.This relaxation supports schedules spanning different geographic communication distances.
  • A.1 Time Efficiency: Overlapping rounds could allow an FPGA to accept round k+1 data while draining round k data.The core model instead prevents round k+1 traffic from beginning before round k movement completes.

A.2 Network Efficiency

The network model simplifies routing, capacity sharing, stream rates, FPGA placement, and failures. Proposed extensions add finer control over these resources and improve practical robustness.

  • A.2 Network Efficiency: The core model routes along shortest paths and splits shared-link capacity equally among routes.The paper identifies this as potentially inefficient when some cliques are slower or under-provisioned.
  • A.2 Network Efficiency: Per-sender stream rates could reduce memory pressure by slowing nearby islands while distant contributions arrive.The baseline instead fixes stream rates at the clique level.
  • A.2 Network Efficiency: Intelligent capacity sharing could reallocate unused capacity from some cliques to starved cliques.This extension changes the optimization from a linear program into a convex program.
  • A.2 Network Efficiency: Flexible routing could free core-link capacity for bottleneck cliques and restore symmetry within a clique.Such routing may deliberately add latency through more circuitous paths.
  • A.2 Network Efficiency: Moving FPGAs into the network core could condense data streams on the fly, but would require a fine-grained data-movement model.The current setup places FPGAs at the network edge before each island’s final hop.
  • A.2 Network Efficiency: Real-world deployment must tolerate latency jitter, outages, FPGA failures, and islands joining, leaving, or failing mid-run.The model excludes these events, while tolerance may reduce efficiency but enhance robustness.

A.3 Parameter Exchange

The paper’s network layer is its main contribution, while parameter-exchange relaxations could make training more efficient or robust. These include smaller payloads, history-aware weighting, heterogeneous targets, and forgetting.

  • Parameter-exchange relaxations are presented as complementary possibilities beyond the paper’s primary network-layer contribution.The paper briefly enumerates these possibilities for completeness.
  • Smaller payloads: Smaller parameter deltas can ease schedule feasibility thresholds by reducing payloads, including when islands lack a common benchmark.The approach can trade payload size against mixing quality in the no-common-benchmark case.
  • Non-uniform weights: Non-uniform doubly-stochastic weights can encode history, upweighting contributions from islands with independent history.Rows and columns of the generalized matrix still sum to one.
  • Non-uniform targets: Heterogeneous compute or data can motivate arbitrary target weights π instead of 1/N and alternative mappings from distance to aggregate loss.The core model instead assumes homogeneous islands and uses the L1 norm across all islands.
  • Forgetting: A discount ρ could model partial forgetting of old updates and align the area function more closely with real-world training.The core model assumes updates accumulate without decay.
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