Source-linked AI summary
PRO-RAN: Processor-Level Characterization of Open RAN Centralized and Distributed Units
Moojan Kamalzadeh, Larry Horner, Linqi Xiao, Abhishek Bhattacharyya, Ehsan Bahaloo Horeh, Padmapriya Patil, Venkateswarlu Gudepu, Andrea Fumagalli
TL;DR
Aggregate metrics provide limited visibility into function-level execution costs and processor bottlenecks in disaggregated O-RAN CU and DU software. The paper presents a controlled framework using independently deployed OCUDU functions, matched hardware and traffic, and process-scoped Intel VTune analysis. Under equal 300-s profiling intervals, CU and DU CPU time increased under load, with distinct execution characteristics and a stronger CU microarchitectural shift.
Problem
Aggregate metrics such as CPU utilization and throughput do not identify function-level execution costs or processor microarchitectural bottlenecks in disaggregated CU and DU software.
Method
The study independently profiles OCUDU CU and DU processes under matched hardware and traffic conditions using Intel VTune Hotspots and TMA.
Results
Under equal 300-s profiling intervals, accumulated process CPU time increased from 17.3 s to 37.4 s for the CU and from 462.0 s to 628.4 s for the DU, while CU Back-End Bound increased from 47.3 % to 58.2 %.
Takeaways & Limitations
The distinct CU and DU measurements motivate function-specific processor analysis for resource provisioning, placement, software optimization, and hardware acceleration.
Takeaways & Limitations
Future work is needed for multi-UE workloads, additional traffic profiles, broader radio configurations, and other CU/DU implementations and computing platforms.
Abstract
from arXiv · showhide
Open Radio Access Network (O-RAN) disaggregates RAN protocol functions and enables Centralized Unit (CU) and Distributed Unit (DU) software to execute on general-purpose computing platforms. Different CU and DU protocol responsibilities produce different processor workloads and execution paths. Conventional performance metrics, including CPU utilization and throughput, quantify aggregate resource usage without identifying function-level execution costs or processor microarchitectural bottlenecks. Processor-level characterization, on the other hand, provides insights into resource provisioning, function placement, software optimization, and hardware acceleration. The paper describes a controlled characterization framework that evaluates independently deployed CU and DU functions under matched hardware and traffic conditions. The experimental platform integrates the Linux Foundation OCUDU implementation with an emulated User Equipment, a ZeroMQ-based radio interface, and an Open5GS core. Automated validation confirms registration and bidirectional packet delivery before process-scoped Intel VTune Hotspots and Top-Down Microarchitecture Analysis. Under traffic load, accumulated process CPU time increases from 17.3 s to 37.4 s for the CU and from 462.0 s to 628.4 s for the DU during equal 300-s profiling intervals. The measurements identify distinct CU and DU execution characteristics and motivate function-specific processor analysis and optimization.
1 Introduction
O-RAN disaggregation creates distinct CU and DU processor workloads, while aggregate metrics provide limited visibility into their execution costs and bottlenecks. The paper addresses this gap with controlled, process-level characterization under matched conditions.
- Motivation: 5G service demands increase computational requirements for software-based RAN protocol processing.These demands accompany growing throughput, latency, reliability, and scalability requirements.
- Motivation: CU and DU responsibilities produce different computational workloads even on identical processor platforms.The CU handles higher-layer control- and user-plane functions, while the DU handles lower-layer radio processing, scheduling, and time-sensitive operations.
- Research Gap: CPU utilization, throughput, latency, and memory consumption quantify aggregate usage but do not reveal function-level execution paths or processor bottlenecks.Similar CPU utilization can conceal differences in software routines, synchronization, cache accesses, and memory-access patterns.
- Research Gap: Processor-level profiling identifies processor-time-consuming routines and pipeline behavior relevant to allocation, placement, optimization, and acceleration decisions.The paper frames this visibility as useful for shared and cloud computing infrastructure.
- Approach: The study evaluates independently deployed OCUDU CU and DU functions under identical hardware and traffic conditions.The platform combines OCUDU with an emulated UE, a ZMQ-based radio interface, and an Open5GS core.
- Approach: The framework combines process-scoped Intel VTune Hotspots and TMA to connect software execution paths with processor microarchitectural behavior.Hotspots attributes processor time to functions, while TMA categorizes Retiring, Front-End Bound, Back-End Bound, and Bad Speculation.
2 Related Work
Prior O-RAN work provides open platforms for deployment, interoperability, experimentation, and processor analysis, including profiling for CPU-affinity and frequency decisions.
- Open O-RAN Platforms: Open-source O-RAN platforms support deployment, experimentation, interoperability evaluation, and AI/ML data collection on testbeds.Examples include Campus5G, X5G, and OpenRAN Gym; X5G also includes GPU-accelerated PHY processing and a near-real-time RAN Intelligent Controller.
- Processor-Level Studies: Prior processor-level studies use hardware counters and microarchitectural metrics to analyze RAN software execution.One study profiles an srsRAN DU with CPU utilization, cache misses, context switches, and IPC for CPU-affinity and frequency selection; another applies Intel VTune to a monolithic OAI platform.
3 System Model
The system model combines an emulated UE, DU, CU, and 5G Core with a processor-profiling framework for controlled end-to-end analysis. Workload tools establish matched baseline and sustained-load conditions before process-level profiling.
- 5G Architecture: The end-to-end 5G architecture contains an emulated UE, DU, CU, and 5G Core.The model is paired with a processor-profiling framework.
- Functional Split: The UE exchanges IQ samples with the DU through a ZMQ-based radio interface.The DU performs PHY, MAC scheduling, and RLC functions, while the CU performs higher-layer protocol processing.
- Profiling Framework: Workload tools generate controlled end-to-end traffic and establish matched baseline and sustained-load operating conditions.Profiling tools monitor independently executing CU and DU processes under each condition.
4 Experimental Setup
The experimental setup uses an automated standalone 5G OCUDU testbed with matched processor configurations, validated traffic conditions, and process-scoped Intel VTune collections for CU and DU analysis.
- Testbed: The testbed deploys an emulated UE, OCUDU DU and CU, and an Open5GS core network in an end-to-end standalone 5G system.Automation supports deployment, traffic generation, end-to-end validation, and process-scoped processor profiling.
- Implementation: The UE and DU exchange digitized IQ samples through a ZMQ-based radio interface, with modifications enabling cell acquisition and 5G registration.The UE host also runs the uplink traffic client, while the core-network side hosts the corresponding endpoint.
- Hardware Control: CU and DU hosts use identical single-socket platforms with 40 physical cores and 80 logical processors.Memory, operating-system, kernel, frequency, affinity, SMT, and container-resource configurations remain identical across measurements.
- Automation: OCUDU CU and DU run as independent Kubernetes workloads, with Ansible controlling deployment, traffic execution, validation, profiling, symbol resolution, and result extraction.The workloads execute the ocu and odu processes, respectively.
- Radio Configuration: The experiments use standalone NR FDD in band n3 with 10 MHz bandwidth, 15 kHz subcarrier spacing, 52 PRBs, and one emulated UE.The configuration supports modulation up to 64-QAM.
- Radio Configuration: The Option 2 split uses F1-C and F1-U for control- and user-plane traffic, while ZMQ replaces physical RF hardware for IQ exchange.Radio timing, scheduling, PHY processing, registration, and PDU-session procedures remain active.
- Workload Conditions: Baseline maintains UE registration and an established PDU session without application traffic, whereas load applies sustained bidirectional traffic.The evaluation keeps radio, software, and hardware configurations identical across conditions.
- Validation: Validation confirms UE registration, PDU-session establishment, and bidirectional packet delivery before profiling begins.Checks cover CU PDCP activity, UE PDSCH reception, DU BSR activity, UE PUSCH transmission, and core-side packet reception.
5 Results
Under matched baseline and sustained-load conditions, CU and DU processes exhibit distinct function-level CPU-time and microarchitectural responses. The CU becomes more traffic-responsive and back-end constrained, whereas the DU remains timing-driven with a more stable distribution.
- Evaluation method: Process-scoped VTune Hotspots and TMA evaluate CU and DU execution under matched baseline and sustained-load conditions.Hotspots attributes processor time to software functions, while TMA categorizes pipeline behavior.
- 5.1 Function-Level CPU-Time Distribution: CU execution shifts from event waiting toward packet processing, synchronization, and lower-ranked support functions under sustained traffic.Packet I/O, buffer traversal, shared-state access, task-queue operations, and packet transmission or reception increase under load.
- 5.1 Function-Level CPU-Time Distribution: DU IQ-sample reception remains dominant, while timing, synchronization, buffering, memory-copy, and scheduling functions stay approximately stable.Most additional DU CPU time appears in lower-ranked functions, and continuous radio processing creates a substantial traffic-independent baseline.
- 5.2 Microarchitecture Behavior: CU Back-End Bound increases from 47.3 % to 58.2 %, while Retiring remains nearly constant at 23.6–23.9 %.Front-End Bound decreases from 13.5 % to 10.1 %, and Bad Speculation decreases from 15.6 % to 7.8 %.
- 5.2 Microarchitecture Behavior: DU Back-End Bound remains dominant, decreasing from 54.5 % to 49.9 %, while Retiring increases from 27.5 % to 29.4 %.Its smaller baseline-to-load shift reflects substantial continuous radio-processing workload before sustained application traffic.
- Overall comparison: Overall, CU load produces a clearer processor-level shift, whereas DU load adds CPU time mainly across lower-ranked functions while leading operations remain stable.The measurements therefore distinguish CU and DU execution characteristics under matched conditions.
6 Summary and Future Work
The paper presents a processor-level characterization framework for independently deployed OCUDU CU and DU functions. Results show different load responses, while future work expands workloads, configurations, implementations, and computing platforms.
- 6 Summary: The framework uses process-scoped Intel VTune Hotspots and TMA to characterize OCUDU CU and DU CPU-time distribution and microarchitectural behavior.The evaluation applies matched baseline and sustained-load conditions in an end-to-end 5G system.
- 6 Summary: CU accumulated process CPU time increases from 17.3 to 37.4 s, while DU CPU time increases from 462.0 to 628.4 s during equal 300-s profiling intervals.CU shows a stronger load-dependent microarchitectural shift, including Back-End Bound increasing from 47.3 % to 58.2 %; DU changes more gradually.
- 6 Summary: The measured CU/DU differences motivate function-specific resource provisioning, placement, software optimization, and hardware acceleration.These implications follow from the distinct processor-level behaviors identified by the characterization.
- 6 Future Work: Future work expands evaluation to multi-UE workloads, additional traffic profiles, broader radio configurations, implementations, and computing platforms.The stated scope identifies the next experimental dimensions.