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Performance Evaluation of Fast Fourier Transforms on Emerging RISC-V Hardware with Vector Extension Support
Daniel Seibel, Kaveh Haghighi Mood, Jayesh Badwaik, Prateek Chawla, Stepan Nassyr, Andreas Herten
TL;DR
FFT performance on emerging RVV 1.0 processors remains underdeveloped despite the operation's central role in scientific computing. The paper introduces juFFTe, combines generated and explicit vectorization, and benchmarks it against FFTW across three RISC-V systems. juFFTe improves performance by up to a factor of three on supported workloads, while the evaluation identifies hardware- and compiler-dependent optimization limits.
Problem
Production FFT libraries provide limited RISC-V support, motivating broader evidence about high-performance FFT implementations on RVV 1.0 hardware.
Method
The paper introduces juFFTe and evaluates its RVV 1.0 vectorized DFT kernels against FFTW3 using double-precision, single- and multi-core benchmarks on three RVV-capable CPUs.
Results
Up to a factor of three average performance improvement is reported for juFFTe over FFTW, depending on hardware.
Takeaways & Limitations
RVV 1.0 enables promising FFT performance improvements, but effective optimization depends on hardware-specific vectorization strategies and platform capabilities.
Takeaways & Limitations
RVV FFT optimization still requires multiple vectorization strategies and advanced roofline analysis to identify bottlenecks and adapt kernels to hardware capabilities.
Abstract
from arXiv · showhide
This manuscript presents a performance evaluation of Fast Fourier Transform (FFT) implementations on emerging processors supporting the RISC-V Vector Extension (RVV 1.0). By introducing juFFTe, a light-weight high-performance library for discrete Fourier transforms, it is demonstrated how effective vectorization of performance-critical FFT kernels can be achieved on RVV-enabled hardware. Comprehensive benchmarks on three RVV 1.0-ready processors, the SiFive X280, the X100 core of the SpacemiT K3 and the C920v2 core of the Sophon SG2044, reveal substantial performance improvements of juFFTe (https://github.com/FZJ-JSC/juFFTe) over the widely used FFTW3 library. Although RVV-enabled platforms show promising results at this stage of development, a comparison with AMD's Zen 5 architecture indicates that RISC-V needs further maturing to reach the performance of established micro-architectures.
1 Introduction
FFT is a foundational operation in scientific computing, but its performance depends on algorithmic design and hardware-specific vectorization. The paper introduces juFFTe and evaluates it on RVV 1.0 hardware against FFTW.
- FFT accelerates DFTs used in numerical algorithms across computational mechanics, electromagnetics, chemistry, and physics.
- Performance-critical smaller DFTs require vectorization tailored to the target CPU or accelerator.
- juFFTe is a modern Fortran DFT library that uses RVV 1.0 vectorization, modular kernels, and a unified FFTW-compatible API.
- The evaluation benchmarks juFFTe on the SiFive X280, SpacemiT K3, and Sophon SG2044 in single- and multi-core scenarios against FFTW.
- The study reports average juFFTe performance improvements of up to a factor of three, attributed to superior vectorization and parallelism.
- The paper compares RVV-enabled systems with an x86 reference system after reviewing RVV optimizations and FFT theory.
2 Related Work
Prior work explored FFT acceleration through RISC-V ISA extensions and RVV implementations. This work extends those efforts with juFFTe and systematic evaluations across multiple RVV 1.0-ready processors.
- Earlier studies accelerated FFT using additional instructions for the RISC-V NutShell processor and an extension to RVV called Zoozve.
- juFFTe adds RVV 1.0 support and evaluates multiple novel RVV-ready hardware implementations systematically against FFTW.
3 Fast Fourier Transform
The paper formulates the DFT as a matrix-vector operation and explains radix splitting as the basis of FFT algorithms. Different data-access frameworks trade contiguous access against workspace requirements.
- The DFT of a complex vector is represented using the Fourier matrix and twiddle factors.
- When N = rm, radix splitting decomposes a length-N DFT into length-r and length-m DFTs.
- Recursive radix splitting produces mixed-radix, four-step, and six-step FFT algorithms.
- The factorization uses point-wise multiplication between arrays as part of the FFT decomposition.
- Stockham algorithms suit vector hardware through contiguous memory access and avoidance of bit-reversal permutations, at the cost of extra workspace.
4 Library Optimizations
juFFTe combines compiler-assisted and explicit RVV vectorization, including generated vector-length-agnostic kernels. Manual intrinsics remain necessary for some RVV operations because current compilers under-vectorize them.
- juFFTe uses compiler auto-vectorization alongside explicit C or assembly kernels to exploit vector units across platforms.
- SPIRAL generates RVV 1.0 kernels whose vector-length-agnostic design is binary compatible across implementations with different vector lengths.
- Current GCC/GFortran and Flang compilers cannot effectively vectorize complex floating-point block transpositions, requiring RVV intrinsics.
- The v_pack() routine uses strided segment loads and unit-stride segment stores to use the available vector length in a vector-length-agnostic manner.
- Future compilers may address the transposition issue, while juFFTe's modular structure isolates performance-critical kernels for such optimizations.
5 Benchmarks
Benchmarks evaluate juFFTe against FFTW across three RVV 1.0 processors, varying transform sizes and thread counts. juFFTe’s advantage depends on cache behavior, vectorization strategy, and hardware, while Zen 5 remains substantially faster in single-core comparisons.
- Benchmark methodology: The evaluation measures complex-to-complex 1D DFT time across transform sizes on three RVV 1.0-capable CPUs.Performance is approximated from execution time using 5N log2(N)/t, with peak compute and memory bandwidth measured for the systems.
- SiFive X280: On the SiFive X280, juFFTe consistently outperforms FFTW through approximately N ≈16000, the 128 kiB L2-cache limit.Segmented vector loads and stores provide more bandwidth than unit-stride operations; beyond cache limits, performance initially converges as computations become memory-bound.
- SpacemiT K3 – X100: On the SpacemiT X100, juFFTe is faster near L1-cache-sized transforms, but FFTW remains competitive within L2 because of unit-stride loads and in-lane shuffling.For larger N, either implementation can be up to 80% faster depending on transform size; with eight cores, juFFTe is almost 50% faster in most larger-N L2 cases under FFTW_ESTIMATE.
- Sophon SG2044: On the Sophon SG2044, juFFTe is faster than FFTW for every benchmarked N from 10^6 to above 10^9, averaging 3x speedup with 64 threads.The results suggest that juFFTe’s six-step algorithm is especially effective at higher core counts in shared-memory systems.
- Comparison against Zen 5: Zen 5 is significantly faster than all tested RISC-V CPUs across the full single-core transform-size range.The C920v2 and X100 reach about 15% of Zen 5’s average performance, while the X280 struggles especially for small and large N because of lower frequency and DRAM bandwidth.
6 Conclusion
juFFTe achieves considerable speedups over FFTW on RVV 1.0-enabled RISC-V CPUs, but effective optimization requires hardware-specific vectorization strategies. The authors identify further analysis and tooling needed to reach maximum performance across current and future systems.
- RVV 1.0-enabled RISC-V CPUs show considerable juFFTe speedups over FFTW in both single- and multi-core DFTs.
- RVV provides multiple DFT-kernel vectorization options whose performance varies across hardware.These options include strided memory operations and permutation instructions.
- Advanced roofline-model analysis is needed to identify performance bottlenecks and adapt vectorization to hardware capabilities.
- The authors plan an auto-tuner combining multiple RVV vectorization strategies for existing and future RISC-V hardware.
- The authors also plan an assembly generator with explicit RVV instructions because compiler auto-vectorization can be unreliable.