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Great Expectations: Benchmarking the Real-World Performance of RVV 1.0 in HPC
Stepan Nassyr, Prateek Chawla, Daniel Seibel, Jayesh Badwaik, Kaveh Haghighi Mood, Andreas Herten
TL;DR
The paper asks whether emerging RVV 1.0 hardware is viable for HPC as commercially available RISC-V processors adopt the extension. It benchmarks these platforms with synthetic and standard HPC workloads against NVIDIA Grace, finding rapid progress alongside persistent hardware-specific bottlenecks and a remaining performance gap.
Problem
The study revisits whether newly emerging RVV 1.0-capable RISC-V processors are viable for HPC.
Method
The authors benchmark five RVV 1.0-capable processors using synthetic and standard HPC workloads, comparing results with NVIDIA Grace.
Results
RVV 1.0 hardware shows strong generational improvement, with the SpacemiT K3 reaching up to 80% compute efficiency and leading sustained HPL and HPCG throughput.
Takeaways & Limitations
Closing remaining readiness gaps requires scaling core counts while eliminating pipeline and bandwidth bottlenecks.
Takeaways & Limitations
A substantial performance gap remains between the evaluated RISC-V platforms and NVIDIA Grace.
Abstract
from arXiv · showhide
Following the ratification of the RISC-V Vector Extension (RVV 1.0), new commercially available silicon has been adopting the extension. This paper revisits the question of RISC-V viability for High-Performance-Computing (HPC) by benchmarking the latest RVV 1.0-capable hardware (SiFive X280 (Tenstorrent Blackhole), SpacemiT X60 (K1) and X100/A100 (K3), and T-Head C920v2 (Sophon SG2044)). We assess these platforms using standard HPC benchmarks (BLAS, FFTW, HPL, HPCG) and synthetic workloads (STREAM, FMA throughput) and compare them to a state-of-the-art HPC ARM64 chip (NVIDIA Grace). Our findings show that while RVV 1.0 delivers significant performance improvements over scalar execution, hardware-specific implementation challenges remain. We detail these performance characteristics and discuss the remaining hurdles for RISC-V, including RVV, to become a mainstay in the HPC landscape.
1 Introduction
RISC-V has matured from a permissively licensed, low-power-oriented ISA toward HPC, with RVV 1.0 providing a portable vectorization foundation. This work benchmarks emerging RVV 1.0 platforms across computational, memory, and standard HPC workloads to reassess RISC-V viability.
- RVV 1.0 standardizes vectorization for RISC-V through a vector-length-agnostic programming model.Applications can remain independent of hardware vector length, unlike fixed-width SIMD approaches.
- RVV supports flexible vector registers, efficient memory access, and permutation and gather/scatter operations relevant to HPC kernels.These features target dense linear algebra, stencil computations, and memory-bound workloads.
- RVV 1.0-capable RISC-V processors have begun emerging for HPC workloads, following earlier evaluations of proposed RVV 0.7 systems.The evaluated platforms span Tenstorrent Blackhole, SpacemiT K1 and K3, and Sophon SG2044.
- The study benchmarks BLAS, FFTW, HPL, HPCG, STREAM, and floating-point throughput workloads across RVV 1.0 hardware.The benchmark set characterizes computational capabilities and memory-subsystem behavior.
- NVIDIA Grace provides an ARM-based comparison baseline for contextualizing the efficiency of the emerging RISC-V platforms.
2 Background
The evaluation combines architectural comparison with synthetic and application benchmarks to examine RVV processors’ compute capabilities, memory behavior, and HPC workload performance. It covers both peak throughput and realistic dense, transform, and sparse workloads.
- Hardware: All evaluated processors support RVV 1.0 but differ in vector configurations, datapath lengths, and cycles required for full-VLEN instructions.The X60, X100, and C920v2 use SIMD-like configurations, while the X280 and A100 are closer to vector units.
- Benchmarks: The benchmark suite combines synthetic tests for peak compute and memory behavior with application benchmarks exposing execution and memory-subsystem bottlenecks.
- FMA throughput: The FMA benchmark measures peak computational throughput across datatypes using independent RVV vfmacc instruction chains.FP16 is included alongside the primarily used FP64 and FP32 precisions.
- FMA throughput: Inserted vle instructions test frontend capacity, L1 port width, and contention between the VFPU and VLSU.
- STREAM: STREAM measures sustainable memory bandwidth with little to no computation per byte transferred.
- BLAS: BLAS evaluation focuses on BLIS and OpenBLAS, with automatic per-core blocksize optimization for BLIS.The optimized parameters include KC, MC, and NC.
- FFTW: FFTW benchmarks RVV 1.0-ready discrete Fourier transform kernels, which are more memory-bound than level-3 BLAS and HPL workloads.
- HPL: HPL evaluates HPC floating-point performance by solving dense linear systems with LU factorization and partial pivoting.
3 Evaluation
The evaluation combines synthetic and application benchmarks to characterize vector execution, memory behavior, and practical performance across RVV 1.0 processors. Results reveal strong but uneven capabilities: RISC-V platforms can approach peak compute or compete in efficiency, yet memory bottlenecks and implementation-specific behavior limit performance against NVIDIA Grace.
- Synthetic workloads: Pure FMA chains reach advertised peak performance, but frequent loads cause substantial slowdowns, especially on the SpacemiT A100.X100 and X280 approach peak with one vector load per four FMAs, while X60 and A100 remain degraded across tested ratios because of VFPU/VLSU contention.
- Synthetic workloads: Grace sustains over 150 GB/s in L1 and L2, while RISC-V bandwidth remains below theoretical peaks or drops sharply in some cases.The bandwidth gap cannot be explained solely by Grace’s higher frequency because some RISC-V cores have higher theoretical bandwidth per cycle.
- Synthetic workloads: Segmented memory instructions deliver platform-dependent results: X280 reaches its L1/L2 theoretical peak only with them, whereas A100 slows significantly.X60 and X100 achieve about 50% of unit-stride bandwidth, SG2044 about 70%, and Grace about 75% with comparable two-element SVE instructions.
- BLAS: 559.6 GFLOP/s FP64 and 1369.8 GFLOP/s FP32 make SG2044 the raw GEMM leader, while X100 and A100 achieve the best reported compute efficiencies.Grace still leads all RISC-V platforms in absolute GEMM performance, but X100 and A100 are competitive in large-matrix efficiency.
- FFTW: Grace outperforms every RISC-V platform in FFTW by three to five times, although its roughly 40% peak efficiency is closer to the RISC-V maximum of 28%.X100 reaches 4 GFLOP/s for L2-bound transforms, while X280 performance is limited because FFTW kernels lack segment loads and stores.
- HPL: In HPL, X100 provides the best multithreaded RISC-V result, but SG2044’s 54.22% panel-factorization time severely reduces its overall performance.Grace reaches about 1084 GFLOP/s with 24 threads, compared with 417.43 GFLOP/s raw DGEMM for SG2044 at 64 threads.
- HPCG: A100 provides the best reference HPCG-kernel performance, while X100 improves over X60 by 3.43× in DDOT and 2.15× in SpMV.Despite this progress, A100 reaches 0.34 GFLOP/s per core for DDOT and X100 0.49 GB/s per core, versus Grace’s 0.77 GFLOP/s and 6.77 GB/s.
4 Conclusion
Current RVV 1.0 hardware exposes micro-architectural and memory-hierarchy bottlenecks that limit utilization, although newer designs show substantial gains and narrowing gaps. The results support a path toward HPC viability through both scaling core counts and improving internal pipelines and bandwidth.
- Hardware limitations: Execution-port contention and memory-hierarchy constraints frequently prevent workloads from fully utilizing current RVV compute pipelines.These limits were exposed by synthetic compute and memory-throughput benchmarks.
- BLAS and macro-benchmarks: Most platforms achieve only 30%–50% compute efficiency in BLAS because they struggle to overcome the memory wall.The SpacemiT K3 reaches up to 80% on both X100 and A100 cores after improving its vector front-end and memory bandwidth.
- BLAS and macro-benchmarks: The SpacemiT K3 achieves up to 80% compute efficiency on both X100 and A100 cores and leads sustained HPL and HPCG throughput.Its gains are attributed to improvements in the vector front-end and memory bandwidth.
- FFT and macro-benchmarks: FFTW favors the Sophon SG2044 and SpacemiT X100 for complex memory access patterns because of their out-of-order execution.This contrasts with the K3's dominance in sustained HPL and HPCG throughput.
- Cross-architecture comparison: NVIDIA Grace retains a substantial performance advantage over the evaluated RISC-V processors beyond differences in clock frequency and manufacturing fabrication.The conclusion also reports rapid inter-generational improvements across the evaluated RISC-V designs.
- Implications: Closing remaining readiness gaps requires scaling core counts while eliminating internal pipeline and bandwidth bottlenecks.The 64-core Sophon SG2044 and SpacemiT K3 illustrate these two design directions, respectively.