Source-linked AI summary
Gen-TAS: A Generative AI-Aided Hardware-Software Task Allocation Framework for FPGA-GPP Heterogeneous Systems
Mary Kong, Yuqin Zhao, Semih Vazgecen, Cristian Sestito, Themis Prodromakis
TL;DR
FPGA-GPP task allocation is difficult because differing latency, communication, resource, and power objectives require extensive analysis and exploration. Gen-TAS combines task-graph analysis, knowledge-base retrieval, RAG-grounded reasoning, explainable strategies, human selection, and deterministic implementation to generate requirement-driven allocations, with stable results across workloads and LLMs.
Problem
Allocating application tasks between GPP and FPGA remains challenging because user objectives can require different strategies affecting latency, resources, communication, and power.
Method
Gen-TAS combines task-graph extraction, retrieval from characterized implementations, RAG-grounded allocation reasoning, explainable strategy generation, human-in-the-loop selection, and deterministic FPGA SoC implementation.
Results
Across CNN and SDR workloads, four objectives, and three LLMs, Gen-TAS generated stable, reproducible, requirement-driven allocations, with speedups up to 2.45× for ImageProc and 92.53× for CAMC.
Takeaways & Limitations
Gen-TAS connects natural-language design requirements to practical heterogeneous implementations while reducing manual exploration and the expertise barrier to FPGA-GPP design.
Takeaways & Limitations
Future work targets expanded knowledge, implementation feedback, finer-grained partitioning, multi-accelerator generation, and broader heterogeneous platforms.
Abstract
from arXiv · showhide
FPGA-GPP heterogeneous systems combine software flexibility with the performance and energy efficiency of reconfigurable hardware. However, determining which application tasks should execute on the GPP or FPGA requires extensive expertise and design-space exploration, particularly when user objectives vary across latency, communication, resource utilisation, and power. This paper proposes Gen-TAS, a knowledge-grounded LLM framework for user-specific FPGA-GPP task allocation. By combining task-graph analysis with RAG, Gen-TAS grounds LLM reasoning in historical implementation knowledge and generates multiple explainable strategies tailored to the specified objectives. Human-in-the-loop selection and a deterministic backend connect LLM-generated decisions to reproducible FPGA SoC implementations. Experiments on CNN and SDR workloads across multiple LLMs demonstrate stable, requirement-driven allocation. Under latency-oriented objectives, implementations following the selected strategies achieve speedups of up to 2.45$\times$ and 92.53$\times$, respectively, relative to the corresponding all-GPP baselines while other objectives select strategies that trade some acceleration performance for FPGA-GPP communication, resource utilisation, or FPGA power.
I. INTRODUCTION
Gen-TAS addresses requirement-driven FPGA-GPP task allocation, where mapping decisions affect latency, resources, communication, and power. It combines task analysis, retrieved implementation knowledge, explainable candidate strategies, user selection, and deterministic implementation.
- FPGA-GPP partitioning remains a significant design challenge because mapping directly affects latency, resource utilisation, communication overhead, interface design, and system-level performance.
- User requirements can demand different allocation strategies for latency-oriented, resource-constrained, and power-aware designs.
- Gen-TAS proposes requirement-driven, function-level task allocation across FPGA and GPP execution domains.
- Gen-TAS integrates task-graph extraction, knowledge-base retrieval, RAG-grounded reasoning, explainable strategy generation, human-in-the-loop selection, and deterministic implementation.
- Across two workloads, four design objectives, and three LLMs, Gen-TAS generates requirements-oriented, stable, and reproducible allocations.
- Speedups reach 2.45× for ImageProc and 92.53× for CAMC relative to corresponding all-GPP implementations.
A. System Model and Overall Framework
Gen-TAS models applications as ordered task graphs and assigns each function to either GPP execution or FPGA acceleration. It combines user objectives, platform information, and implementation knowledge to generate candidate allocations for selection and deterministic realization.
- Gen-TAS performs function-level allocation by assigning each HLS C/C++ computational function or processing stage to the GPP or FPGA.
- The application is represented as an ordered task graph G = (T, E), with partitionable sub-functions in T and data dependencies in E.
- A candidate partition assigns every application task to either GPP or FPGA, while the current backend maps contiguous FPGA tasks to one hardware region.
- The workflow comprises source analysis, knowledge retrieval, allocation generation, deterministic implementation, on-board deployment, and evaluation.
- Gen-TAS supplies the LLM with task information, retrieved evidence, platform constraints, and design objectives to generate and rank candidate allocations for designer selection.
B. Task Analysis and Allocation Generation
Gen-TAS extracts task and communication characteristics from source code, retrieves relevant implementation records, and prompts an LLM to generate ranked FPGA-GPP partitions with evidence-based rationales.
- Task dependencies are derived from call sequence and inter-task data flow, while descriptors capture operations, dimensions, precision, and buffer sizes.
- Communication volume is derived from buffer size and data precision, and cross-domain dependencies create hardware-software communication boundaries.
- The knowledge base stores measured placement, latency, resource, timing, power, communication-boundary, and transfer-latency characteristics.
- Gen-TAS retrieves the 12 highest-scoring knowledge-base records using token-based cosine similarity, without imposing a minimum similarity threshold.
- The LLM returns three ranked candidate partitions by default, specifying task sets, communication boundaries, and rationales based on source and knowledge-base evidence.
- The framework considers both acceleration potential and boundary communication because transfer and execution overheads can exceed computational benefits.
C. Partition Validation and Deterministic Implementation
Gen-TAS validates generated partitions against deterministic constraints before presenting them for selection, then encodes the selected strategy for reproducible backend implementation.
- Generated partitions must use valid task identifiers, assign every task exactly once, keep FPGA and GPP sets disjoint, and form a contiguous FPGA group.
- Duplicate partitions are removed while preserving task sequence, but ranking compliance is confirmed only through implementation and measurement.
- Validated candidates, retrieved evidence, and rationales are presented to the designer for selection.
- The selected partition is encoded with task sets, hardware-boundary I/O, source files, and implementation configuration for deterministic backend generation.
A. Experimental Setup
Gen-TAS is evaluated on an AMD ZCU104 FPGA-GPP platform using CNNImageProc and CAMC under four design objectives and three LLMs. Evaluation measures allocation validity, requirement satisfaction, consistency, runtime, and implementation performance.
- Platform and Evaluation: Experiments use an AMD ZCU104 platform with an XCZU7EV-2FFVC1156 Zynq UltraScale+ MPSoC.Gen-TAS generates Vitis HLS and Vivado scripts, bitstreams, and PYNQ software for on-board evaluation.
- Workloads and Models: CNNImageProc and CAMC are evaluated under latency-, communication-, power-, and resource-oriented objectives using GPT, Gemini, and Claude.All models receive identical source code, task graphs, requirements, retrieved knowledge, and generation settings.
- Evaluation Metrics: Gen-TAS evaluates allocation validity, requirement satisfaction, consistency, LLM runtime, and implementation performance.A successful run requires valid allocation, passing FPGA implementation, and on-board functional validation.
B. Case Studies
The evaluation uses two representative workloads with different task structures: a five-stage CNN image processor and a three-stage SDR modulation-classification application. Their computational, control, memory-access, and data-transfer characteristics support fine-grained allocation analysis.
- Workload Selection: Two representative workloads validate Gen-TAS across different task structures.The workloads are used to assess task allocation rather than to represent a broader application population.
- CNNImageProc: CNNImageProc decomposes Fashion-MNIST CNN processing into five tasks with distinct computation and data-transfer characteristics.The stages include convolution, ReLU-pooling, and dense-classification functions.
- CAMC: CAMC decomposes SDR processing into axis initialisation, matrix generation, and array product tasks spanning control, memory access, and matrix operations.These behaviours provide a contrasting task structure for FPGA-GPP allocation evaluation.
C. User-Defined Design Objectives
Gen-TAS takes user-defined objectives as a primary input and evaluates allocations across latency, communication, power, and resource priorities. The objectives use workload-specific baselines, thresholds, and implementation-cost reporting to expose allocation trade-offs and infeasibility.
- Objective Directions: User objectives directly influence generated FPGA-GPP allocation strategies across four objective directions.The directions are constrained latency, communication-aware allocation, power prioritisation, and strict resource utilisation.
- Reporting and Baselines: Table II reports rank-1 partitions, implementation cost, hardware-cost reductions, consistency, latency, speedup, power, and LLM time across objectives and LLMs.F and G denote FPGA and GPP placement; speedup is relative to the corresponding all-GPP implementation.
- Workload Bounds: CNNImageProc and CAMC use workload-specific all-GPP and all-FPGA latency, resource, and power measurements as design bounds.CNNImageProc latencies are 37.877 ms and 14.685 ms, while CAMC latencies are 32.445 ms and 0.356 ms for all-GPP and all-FPGA implementations, respectively.
- Constrained Latency: Constrained latency minimises end-to-end latency while requiring LUT and total-power reductions relative to the all-FPGA baseline.The objective also avoids communication-dominated partitions and sets workload-specific LUT and power limits.
- Communication-Aware: Communication-aware allocation minimises latency while preferring mixed placement when computational benefit exceeds transfer, cache-coherency, and control overhead.LUT utilisation and total estimated power must not exceed the corresponding all-FPGA values.
- Power Prioritisation: Power prioritisation minimises total estimated power first and latency second, targeting reductions relative to the all-FPGA baseline.The objective targets at least 1% total power reduction and 10% LUT reduction.
- Strict Resource: Strict resource utilisation imposes LUT and power reductions relative to all-FPGA operation while minimising latency among mixed partitions.Its limits are intentionally outside the characterised feasible power region, making it an infeasibility stress test.
D. Quantitative Results
Gen-TAS generates objective-dependent allocations with workload-specific performance and implementation-cost trade-offs, while repeated RAG-grounded experiments show stable results across LLMs. Reported outcomes include substantial speedups, resource and power reductions, and differing LLM generation efficiencies.
- CNNImageProc: 2.45× speedup is achieved for CNNImageProc under constrained-latency and communication-aware objectives with FFFFG partitioning.The partition also reduces LUT, FF, DSP, and BRAM usage by 18.7%, 10.2%, 68.0%, and 27.6%, respectively.
- CAMC: 3.53× speedup is achieved for CAMC with GFF selected for most objectives, alongside reductions of 17.2% LUTs, 13.2% FFs, 27.6% DSPs, and 1.8% FPGA power.The reported reductions accompany the GFF allocation across most objectives.
- Objective Trade-offs: 92.53× speedup is achieved by the FPGA FFF partition, while GPT selects FGG for strict resources with lower hardware cost and 1.38× speedup.The FGG selection reduces LUT, FF, DSP, and BRAM usage by 26.6%, 20.3%, 72.4%, and 93.9%, respectively, and FPGA power by 5.4%.
- Stability and LLM Efficiency: 22 of 24 workload-objective-LLM configurations reproduce the dominant partition in at least four of five runs, including 15 with complete five-of-five consistency.Gemini has mean generation times of 22.161-35.994s, compared with 58.913-71.699s for GPT and 76.910-103.820s for Claude.
IV. CONCLUSION
Gen-TAS integrates retrieval-augmented generation and implementation knowledge to generate requirement-driven FPGA-GPP allocations that are stable, reproducible, and practical across multiple settings. Future work targets broader knowledge, feedback, partitioning, platforms, and retrieval improvements.
- Gen-TAS integrates RAG and implementation knowledge for requirement-driven task allocation in FPGA-GPP heterogeneous systems.
- Evaluations across multiple LLMs, user-defined objectives, and application domains demonstrate stable and reproducible generation of practical hardware-software allocations.
- Gen-TAS bridges natural-language design requirements and executable heterogeneous implementations while reducing manual exploration and the expertise barrier.
- Future work will expand the knowledge base and incorporate implementation feedback to improve retrieval quality and allocation robustness.
- Further directions include finer-grained partitioning, multi-accelerator generation, more heterogeneous platforms, and enhanced LLM prompting and retrieval.