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Neuromorphic architectures as numerical solvers for computational neuroscience
Jakob Jordan, Ole Richter, Congyang Li, Mihai A. Petrovici, Rajit Manohar
TL;DR
Existing spike-based neuromorphic hardware is not well suited to continuously coupled neuronal models. The paper treats their simulation as distributed numerical solving, proposes multi-bit packets and higher-order solvers, and reports reduced computation, communication, energy, and delay, with benefits limited by arithmetic precision.
Problem
Spike-oriented neuromorphic implementations are poorly suited to rate-based models that use continuous coupling rather than spiking interactions.
Method
The paper develops design principles for digital neuromorphic accelerators by viewing continuously coupled models as distributed ODE solvers and message-passing systems.
Results
Higher-order solvers reduce computation and communication costs while lowering numerical error, and the resulting architecture provides practical energy and delay advantages.
Takeaways & Limitations
Multi-bit packets and higher-order numerical methods support neuromorphic architectures tailored to continuously interacting models, complementing spike-based systems.
Takeaways & Limitations
Higher-order methods are more efficient only for sufficiently small error tolerances, and adaptive time steps introduce interpolation challenges.
Abstract
from arXiv · showhide
Neuromorphic computing is closely associated with spiking neuronal networks. However, an alternative class of so-called "rate-based" models arising from computational neuroscience and machine learning forgoes spiking interactions and instead relies on continuous coupling between neurons. Existing neuromorphic implementations designed around spike-based interactions are not well-suited for emulating such models. Here view the distributed simulation of these models as message-passing algorithms on parallel hardware. Leveraging prior art in numerical algorithms and distributed simulation, we outline steps that enable the design of efficient digital neuromorphic accelerators for non-spiking neuronal models. In particular, we show that multi-bit packets, rather than spikes, are the most efficient communication strategy in packet-switched networks and that compared to basic numerical integration methods, higher-order differential equation solvers decrease both computation and communication costs while achieving lower numerical error, but that these benefits are ultimately limited by arithmetic precision. Using our proposed design principles, we convert an existing neuromorphic architecture into a distributed numerical solver - a spikeless neuromorphic system - for continuously-coupled neuronal models. We thereby demonstrate that our theoretical considerations indeed translate into practical advantages, namely reduced energy consumption and delay.
1 Introduction
Neuromorphic systems can be viewed as distributed ODE solvers, but spike-oriented hardware is poorly matched to continuously coupled neuronal models. Efficient implementations therefore require communication and numerical-integration designs tailored to continuous interactions.
- 1 Introduction: Neuromorphic systems simulate abstracted neuronal and synaptic dynamics represented as nonlinear ordinary differential equations.These systems aim to accelerate simulations or reduce their energy expenditure.
- 1 Introduction: Spiking hardware efficiently exploits sparse binary events, but many computational-neuroscience models instead use continuous coupling between variables.This mismatch motivates treating their distributed simulation as a numerical-solving problem.
- 1 Introduction: Send-on-delta communication works when system changes are sparse, but high-accuracy simulation may require exceedingly small time steps and long runtimes.Larger steps can cross multiple quantization levels, requiring values with higher resolution than one bit.
- 1 Introduction: The proposed design principles target efficient neuromorphic systems for continuously coupled models.The paper studies multi-bit communication and higher-order ODE solvers, including their computation, communication, error, precision, energy, and delay trade-offs.
2 Spikes are (only) a good choice for communicating binary events
For continuously coupled models, communicating non-binary values favors packetized multi-bit representations over spike codes. Packet payloads reduce communication resources, while joint routing also limits dynamic-energy overhead.
- 2 Spikes are (only) a good choice for communicating binary events: Linear spiking codes encode T + 1 values in T time bins and therefore require resources proportional to the number of values.Rate, latency, and interspike-interval codes are examples of this class.
- 2 Spikes are (only) a good choice for communicating binary events: Combinatorial phase-based codes encode 2^T values in T time bins, achieving logarithmic resource scaling.They implement bit-serial communication of binary representations.
- 2 Spikes are (only) a good choice for communicating binary events: Multi-bit packets can encode 2^BT values in T time bins when each packet carries a B-bit payload.Because routing headers already contain 16b-32b information, adding a small payload causes negligible additional costs.
- 2 Spikes are (only) a good choice for communicating binary events: Multi-bit packets reduce resources relative to phase-based codes in proportion to payload size and can reduce synaptic operations per second five-fold.The theoretical resource advantage follows because multiple bits are routed jointly rather than individually.
- 2 Spikes are (only) a good choice for communicating binary events: Rate-based codes have the highest dynamic-energy cost, whereas latency codes use at most one event and multi-bit packets reduce control overhead relative to phase-based codes.Phase-based and multi-bit packet dynamic-energy costs scale logarithmically with the number of communicated values.
3 Higher-order solvers increase temporal sparsity
Viewing continuously coupled neuronal models as distributed differential-equation solvers shows that higher-order methods can reduce communication frequency and computational work at matched error.
- Numerical solver formulation: Numerical methods approximate continuously coupled models on a finite time grid with known error bounds, determining when neuron states need communication.Runge-Kutta methods use intermediate function evaluations, or stages, to achieve higher order.
- Computational cost: For tolerated error ϵ = 10^-4, increasing solver order below p = 9 decreases the total number of function evaluations.The predicted minimum occurs at p = −log(ϵ), giving p = 9 for ϵ = 10^-4.
- Computational cost: At tolerated error 10^-4, a third-order solver requires more than two orders of magnitude fewer function evaluations than a first-order solver.The comparison uses a toy network with an analytically solvable low-pass-filter model.
- Temporal sparsity: For τ = 0.5ms and comparable numerical error, forward Euler requires a 2MHz event frequency, whereas a third-order method requires 30kHz, reducing frequency by more than 60×.The third-order method uses h = 0.1ms, while the first-order method uses h = 0.0005ms.
- Hardware considerations: Higher-order solver benefits exclude additional hardware costs for storing intermediate right-hand-side evaluations and loading neuronal state into registers.These costs are considered separately in the paper’s later hardware analysis.
4 Higher-order solvers decrease required computations while minimizing errors in finite precision
Finite arithmetic precision adds a rounding-error floor to numerical integration. Balancing integration and rounding errors yields an optimal step size, with higher-order methods generally permitting larger steps and lower error in the analyzed regime.
- Finite-precision error: Finite-precision state updates introduce arithmetic error that accumulates over repeated integration steps.The preceding analysis considers integration error but initially ignores arithmetic error from finite bit widths.
- Finite-precision error: Global rounding error scales as O(1/h), increasing when the integration step size decreases.This scaling opposes integration error, which decreases with smaller step size.
- Error balancing: The sum of rounding and integration errors therefore has an optimal step size that minimizes total error.The analysis assumes the two error contributions combine linearly with scaling factors a and b.
- Solver-order effects: Increasing solver order increases the optimal step size and lowers the computation required to balance rounding and integration errors.The paper also shows that error at the optimal step size is lower for higher-order methods.
- Scope boundary: Higher-order methods are more efficient than lower-order methods only for sufficiently small error tolerance.The relevant precision parameter b depends on chosen arithmetic precision and expected state-value range.
5 NeuroScale case study
The NeuroScale case study implements multi-bit communication and higher-order ODE solvers for continuously coupled neuronal models. Back-annotated simulations reproduce behavioral results and show practical advantages constrained by finite precision.
- Architecture: NeuroScale uses a packet-switched mesh network and local core memory to implement distributed simulation of continuously coupled neuronal models.The architecture communicates remotely stored neuronal states when computing each neuron's differential-equation right-hand side.
- Solver implementation: Higher-order solvers require intermediate evaluations and communication before each stage, with neuronal-state memory increasing with the number of stages.The implementation compares RK1, RK2, and RK3 methods using mixed-precision fixed-point arithmetic and expanded packet payloads.
- Accuracy and work: Higher-order solvers achieve lower error as step size decreases, until finite-precision arithmetic errors dominate.Figure 5 describes this precision-limited behavior for FP32 arithmetic, while the case study observes the same pattern in hardware simulations.
- Validation: The back-annotated trajectories are bitwise identical to a custom behavioral simulator using sequential implementations of the corresponding solvers.This validates agreement between the synthesized neuromorphic design and the behavioral reference for the simulated network.
- Practical costs: Normalized delay follows normalized function evaluations, while wider memories add an energy offset without changing the higher-order scaling behavior.Sequential dependencies make resource use scale linearly with the number of function evaluations; parallel propagation does not alter this scaling.
6 Conclusion
The paper frames neuromorphic systems as distributed ODE solvers and derives design principles for continuously coupled models. It argues for multi-bit communication, higher-order solvers, and adaptive stepping while noting precision and implementation trade-offs.
- Viewing neuromorphic systems as distributed ODE solvers yields design principles for continuously coupled models and is supported by proof-of-concept empirical measurements.
- Multi-bit packets are argued to be the most efficient communication strategy in packet-switched networks.
- Precision matters: Higher-order methods are more efficient than lower-order methods only for sufficiently small error tolerance.
- Precision matters: Small numerical errors help simulated trajectories reflect the mathematical model and separate modeling behavior from implementation details.
- Higher-order solvers can reduce communication frequency, delay, and energy for continuously coupled ODE systems.
- Consequences for the design of spiking neuromorphic hardware: Spiking implementations face interpolation and root-finding challenges when larger solver steps could cause spike times to fall between coarse time-grid points.
- Outlook: Adaptive step sizes can reduce unnecessary computation and communication while enabling online error control, but require interpolation when input states are unavailable at update times.
- A Spiking codes: With B payload bits, multi-bit communication encodes 2^BT N different values, while single-neuron transmission requires log2 v / B time bins.
B Methods
The methods section considers two leaky integrators with linear feedforward coupling and names second- and third-order Ralston Runge–Kutta methods.
- The assumed model consists of two leaky integrators with linear feedforward coupling.
- RK2 is identified as the Ralston method.
- RK3 is identified as the Ralston method.
B.3 Number of function evaluations
The number of function evaluations is governed technically by the number of solver stages, which is approximately proportional to solver order.
- The first term technically scales with the number of stages s, not solver order p, although s is almost proportional to p.
B.4 Optimal order for given error tolerance
Figure 7 compares the optimal step size with the error achieved at that step size for two values of c.
- Figure 7 plots optimal step size on the left and error at the optimal step size on the right.The black solid line denotes c = 10−9, and the black dashed line denotes c = 0.135.
B.6 Larger optimal step size for higher-order method
The section states a step-size condition involving p and c: p > log c.
- p > log c is the stated condition.
B.7 Smaller error at optimal step size for higher-order method
The implementation models neurons as leaky integrators with ReLU activation and specifies network, initialization, quantization, and evaluation details.
- Each neuron is modeled as a leaky integrator with a nonlinear activation function.
- The activation function is φ(x) = ReLU(x).
- The configuration uses N = 43, T = 9.1, and 21 neurons per core.
- Neurons are randomly assigned parameter combinations.
- Weights use shifted and scaled Kaiming initialization, 25% density, and Q4.12 quantization.Weights are shifted by −0.2, scaled by 4.0, and randomly downsampled.
- Energy and delay are obtained through Spice simulations, Cadence Genus, and AMC-generated memory models.Memory read and write energy and delay come from Spice simulations.