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SmartBAN on Silicon by Structured Behavioral Modeling

Masato Yoshimi, Takahiro Ito, Kento Tanaka, Hirokazu Tanaka

arXiv:2608.29036v1cs.NI

TL;DR

SmartBAN provides a standardized TDMA-based WBAN protocol, but commercial-hardware implementation is absent and internal behaviors remain underspecified. The paper addresses these gaps with Mealy-type behavioral models and model-driven realization, validating the design across sixteen nodes and comparing it with BLE. The evaluation reports sub-millisecond jitter, over 99.99% packet delivery, autonomous recovery, and a determinism–efficiency tradeoff against BLE.

  • Problem

    SmartBAN specifies frame formats and channel structure but lacks internal transition logic for phase control and connection lifecycle and parametric guidance for slot timing and scheduling.

  • Method

    The paper constructs Hub and Node Mealy-type finite automata as a hardware-independent blueprint, then realizes timing and scheduling on a commercial wireless SoC.

  • Results

    Sixteen concurrent sensor nodes evaluated over 25 h achieved sub-millisecond timing jitter, >99.99% packet delivery, and autonomous disconnection recovery, with a same-SoC BLE comparison.

  • Takeaways & Limitations

    The behavioral model supports an operational SmartBAN realization and provides a foundation for future on-body evaluation, encryption, downlink support, and priority-based scheduling.

  • Takeaways & Limitations

    Evaluation used clean bench-top conditions without body shadowing or co-channel interference, and porting beyond the nRF54L15 family remains unverified.

Abstract

from arXiv · show

Wireless body area networks (WBANs) are a key enabling technology for the Internet of Medical Things (IoMT). SmartBAN, standardized by ETSI and later adopted as an IEC international standard, defines a lightweight WBAN protocol with time-division multiple access (TDMA)-based physical (PHY) and media access control (MAC) layers, yet no implementation on commercial hardware has been reported. The standard specifies frame formats and channel structure but leaves internal device behaviors unspecified: phase control and connection lifecycle lack transition logic, while slot-level timing and scheduling policy lack parametric guidance. This paper addresses these omissions through structured behavioral modeling and model-driven implementation. Two Mealy-type finite automata -- one for the Hub (3 states, 5 transitions), one for each Node (5 states, 8 transitions) -- capture phase control and connection lifecycle as a hardware-independent design blueprint whose transition tables map directly to firmware dispatch logic; slot-level timing and scheduling policy are resolved through realization on the nRF54L15, a commercial Arm Cortex-M33 wireless system-on-chip (SoC) running Zephyr real-time operating system (RTOS). Experiments with sixteen concurrently scheduled sensor nodes over 25 hours validate the design for the initial connection and uplink data paths: all 13 modeled transitions were exercised with sub-millisecond per-slot timing jitter ($P_{99} <$ 754 $μ$s, slot-independent across all 16 slots), 99.99% packet delivery, and autonomous disconnection recovery. A same-SoC Bluetooth Low Energy (BLE) comparison quantifies the determinism-efficiency tradeoff: SmartBAN achieves substantially lower timing jitter at higher energy cost, the majority of which is attributable to software radio processing rather than the protocol-level duty cycle.

I. INTRODUCTION

WBANs support IoMT applications but must provide low latency, low power, multi-node support, and reliability. SmartBAN addresses these needs with TDMA-based deterministic access, while this paper fills implementation gaps through behavioral modeling and commercial-SoC validation.

  • WBANs must support low latency, low power, multiple nodes, and reliability under body shadowing for IoMT applications.
  • SmartBAN uses TDMA-based channel access to provide each sensor Node a deterministic uplink slot, unlike BLE connection-event scheduling as peripherals increase.
  • The paper models unspecified behaviors as finite automata, realizes them on a commercial wireless SoC, and validates the system experimentally.
  • Two Mealy-type automata capture phase control and connection lifecycle while slot timing and scheduling are resolved through structured realization.
  • The validation covers behavioral conformance, communication quality, long-term stability, and a same-SoC BLE comparison across sixteen concurrent sensor nodes.

A. Protocol Overview

SmartBAN combines beaconing, scheduled TDMA uplinks, acknowledgments, and contention-based connection management in a repeating inter-beacon interval. The standard defines these structures but leaves several internal behaviors and allocation policies unspecified.

  • A. Protocol Overview: SmartBAN defines a star network with one Hub coordinating up to 16 sensor Nodes.
  • A. Protocol Overview: The PHY uses 40 channels in the 2.4 GHz ISM band, with GFSK at 1 Mbit s^-1 and optional BCH forward error correction.
  • A. Protocol Overview: Each inter-beacon interval contains a timestamped D-Beacon, deterministic TDMA uplink slots with immediate acknowledgments, and a slotted-Aloha contention period.
  • A. Protocol Overview: The paper realizes the three MAC operations needed for Node-to-Hub connection and uplink collection, while accommodating the others as bounded model extensions.
  • Specification Gaps: The standard leaves phase switching, slot timing, connection transitions, and scheduling policy unspecified, including beacon-loss recovery and slot allocation criteria.

C. Related Work

The paper uses compact Mealy-type automata as implementable SmartBAN behavior models, linking Hub–Node interactions to firmware dispatch logic. The models cover channel-phase control, connection lifecycle, and bounded extensions while deferring platform-dependent timing and scheduling details.

  • No WBAN standard had been fully realized on a commercial off-the-shelf SoC, while prior IEEE 802.15.6 work remained partial or research-platform based.
  • The models are intended as design blueprints, with optional SmartBAN operations represented as bounded extensions preserving single-valuedness and bounded reachability.
  • Mealy-type finite automata were chosen over timed automata because transition outputs translate directly into firmware dispatch logic without an intermediate verification step.
  • The SmartBAN behavior model comprises separate Hub and Node finite automata, each specified by states, events, actions, an initial state, and a transition function.
  • Hub–Node coupling maps each transmit action to the corresponding receive event, while address filtering lets N Node replicas execute independently.
  • The Node model uses a timeout escape to return from DCH to CCH, then follows reconnection transitions into the CONN–UPLINK cycle; uplink retransmission continues until acknowledgment.

A. Software Architecture

The implementation uses a four-layer architecture on the nRF54L15, separating application, MAC, PHY, and hardware abstraction responsibilities. A portability boundary keeps the MAC and PHY hardware-independent while isolating SoC-specific changes in the HAL.

  • The four layers are Application, MAC, PHY, and HAL, with sensor acquisition, connection and scheduling, radio processing, and register-level virtualization assigned respectively.
  • The MAC and PHY layers are hardware-independent, so porting to another SoC requires replacing only HAL modules below the portability boundary.

B. Behavioral Model Realization

The behavioral automata are realized in the MAC layer through timer- and frame-driven dispatch, with parameterized timing, sequential slot allocation, and timeout-based recovery. The PHY supplies radio and error-correction functions required by the realization.

  • Each automaton transition maps one-to-one to a MAC-layer dispatch branch driven by slot-boundary timers or received-frame events.
  • RTC compare events establish slot boundaries, while D-Beacon timestamps reprogram Node timing to compensate for inter-IBI clock drift.
  • CRC validation, BCH decoding, and frame-type dispatch select handlers for the current device state, with I-Ack frames pre-assembled before SAP slots.
  • The PHY uses proprietary GFSK at 1 Mbit s−1 with BCH(127,113,t=2) forward error correction and a fixed data channel for scheduled traffic.
  • The MAC maintains runtime Node Tables for connection context, and timing and configuration values are compile-time parameters.
  • The Hub assigns consecutive free slots sequentially from slot 1 for up to Nmax = 16 nodes.
  • Connection robustness uses retry backoff, assignment timeouts, and missed-beacon detection to trigger autonomous CCH recovery and rescanning.
  • Uplink retransmission reuses the same transmit buffer until an I-Ack is received.

V. EXPERIMENTAL EVALUATION

Experiments used identical nRF54L15-based Hub and Node hardware in an indoor 1 m setup, assessing modeled transitions, timing, and packet delivery across 16 concurrently scheduled Nodes.

  • Experimental setup: The setup used identical commercial nRF54L15 hardware for the Hub and Nodes, with the Hub additionally connected to a host PC for logging.The Node platform included an IMU and battery holder, and experiments were conducted indoors at a 1 m Hub–Node distance.
  • Behavioral conformance: All 13 modeled transitions fired at least once during the 25 h session, with no undefined state-event pairs observed.Per-transition counts ranged from 1 for τN8 to 6.55×10^6 for τH5.
  • Connection lifecycle: One timeout-triggered disconnection was followed by the modeled reconnection sequence, demonstrating autonomous lifecycle recovery.The Node returned to CCH and completed τN1 → τN2 → τN4 → τN5.
  • Timing precision: P99 slot timing remained slot-independent at 737–754 µs across the scheduled slots.For slot 1, σ = 371 µs; fewer than 0.1% of frames in other slots arrived approximately one IBI late.
  • Frame exchange: Per-node packet delivery was highly equitable across 16 Nodes, with a coefficient of variation of 0.004%.The result supports uniform TDMA slot utilization.

C. Standard-Compliant Communication

The communication evaluation found error-free MAC delivery under the tested indoor conditions and identified substantial board-level current overhead during protocol operation.

  • Communication quality: No MAC-level packet loss occurred with 16 Nodes in either BCH mode.The interference-free channel produced no errors for BCH to correct, so coding gain was not measurable.
  • Energy efficiency: The SoC spent 92% of each IBI in low-power sleep, while RX overhead dominated the gap between nominal and measured current.Software BCH decoding, CRC verification, frame parsing, and RTOS scheduling latency contributed to the RX overhead.
  • Energy model: The average-current analysis used a three-state weighted model combining TX, RX, and idle duty cycles.The comparison against measured values is described using the model of Ruan et al.

D. Long-Term Stability

The 25 h test showed sustained operation with live IMU traffic, very high packet delivery, and recovery from one transient disconnection.

  • Sustained operation: The 25 h continuous test showed no time-dependent degradation, including memory leaks, timer drift, or buffer exhaustion.All Nodes transmitted live IMU sensor data throughout the test.
  • Packet delivery: Aggregate PDR exceeded 99.99%, with per-node values ranging from 99.983–99.998%.Mean RSSI ranged from −62 to −42 dBm, with no PDR correlation to RSSI in that range.
  • Disconnection recovery: One Node reconnected within 264 ms after a disconnection, while the resulting maximum inter-frame gap was 2.4 s.The gap was consistent with timeout detection plus reconnection latency.
  • Current-model validation: Using measured state currents reduced the model’s maximum absolute error to 7%.Nominal-current estimates underestimated measured average current by 4.8–10.9×, whereas measured parameters closely matched the implementation.

B. BLE Comparison

On identical nRF54L15 hardware, SmartBAN provided more stable timing than BLE but consumed more energy, with most of the excess attributed to implementation overhead.

  • Timing: SmartBAN maintained σ = 371 µs while BLE’s arrival-interval variation grew nearly tenfold from N=1 to N=16.SmartBAN’s fixed TDMA slots remain aligned to the D-Beacon reference as the number of Nodes increases.
  • Energy: SmartBAN consumed 4.4× more energy than BLE.Both protocols achieved high PDR under the matched comparison conditions.
  • Energy model: The nominal-duty-cycle model predicted SmartBAN at approximately 289 µA, comparable to BLE’s 317 µA baseline.This comparison indicates that protocol-level duty cycle was not the dominant factor in the measured energy difference.
  • Energy overhead: 1112 µA, or 79% of SmartBAN’s total measured current, was implementation overhead concentrated in the RX state.Software-defined operations accounted for the difference between 1401 µA measured current and 289 µA model-predicted current.
  • Channel diversity: SmartBAN uses one fixed data channel, whereas BLE uses adaptive hopping across 37 data channels.The stated channel asymmetry would favor BLE’s PDR in interference-rich environments.

C. Limitations and Future Work

The implementation’s scope is bounded by clean bench-top conditions, one SoC family, TDMA-oriented modeling, and partial protocol-operation coverage. Future work prioritizes dynamic on-body evaluation and extensions such as encryption and priority-based scheduling.

  • Experimental scope: The evaluation used clean conditions without body shadowing or co-channel interference, so dynamic on-body multipath fading remains untested.The reported RSSI spread was 20 dB, and on-body fading may stress timeout and reconnection mechanisms beyond bench-top evaluation.
  • Experimental scope: Portability beyond the nRF54L15 remains unverified despite a hardware-independent boundary in the software architecture.
  • Model and protocol scope: The automaton decomposition is naturally suited to TDMA-based protocols, while CSMA standards would require additional contention-resolution modeling.
  • Model and protocol scope: First-fit slot allocation is a standard heuristic rather than a novel scheduling contribution.
  • Model and protocol scope: The implementation realizes only operations (1), (2a), and (2b), with operations (3)–(6) represented as bounded behavioral-model extensions.
  • Future work: Future work prioritizes on-body evaluation under dynamic channel conditions, encryption, priority-based scheduling, and optional SmartBAN features.
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