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FIREQ: FPGA Instrumentation for Readout and Qubit control

Giuseppe La Capra, Fabio Calabrese, Giorgio D'Amico, Christian Conti, Andrea De Simone, Deborah Volpe, Angelo Nucciotti, Roldolfo Carobene, Claudio Gatti, Andrea Giachero, Fabrizio Riente

arXiv:2608.29399v2quant-pheess.SY

TL;DR

Existing RFSoC frameworks face overhead and extensibility challenges in repeated superconducting-qubit workflows. FIREQ addresses these with modular firmware and a PYNQ-based software stack, achieving low BRAM use, precise RF control, and validated qubit measurements.

  • Problem

    Existing open RFSoC frameworks can incur overhead from host–device interaction, repeated configuration, and data movement during high-repetition workflows, while extensibility remains limited.

  • Method

    FIREQ combines modular AXI-compliant RFSoC peripherals with a PYNQ-based client-server stack, envelope interpolation, and memory-efficient acquisition buffering.

  • Results

    FIREQ generates pulses up to 9.3 GHz with 107 ps pulse-duration and 1.7 ns event-timing resolution, maintains full-rate I/Q generation and acquisition with low BRAM use, and yields T1 = 6.94µs and T2* = 13.50µs.

  • Takeaways & Limitations

    FIREQ serves as both a superconducting-qubit control and readout platform and an environment for evaluating alternative control and readout IP architectures.

Abstract

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We present FIREQ (FPGA Instrumentation for Readout and Qubit control), an open-source RFSoC-based framework for the control and readout of superconducting qubits. FIREQ combines a modular AXI-compliant firmware architecture with a PYNQ-based software stack designed to support extensible hardware integration, deterministic experiment timing, and low-overhead execution of repeated calibration and characterization workflows. The firmware implements direct RF synthesis and acquisition, trigger-based sequencing, programmable pulse generation, frequency-multiplexed readout, and memory-efficient acquisition and waveform buffering. The software adopts a client-server architecture with streamed data transfer and dependency-aware configuration updates to reduce host-device and reconfiguration overhead during parameter sweeps. On an AMD Zynq UltraScale+ RFSoC ZCU216, FIREQ generates RF pulses up to 9.3 GHz with a pulse-duration resolution of 107 ps and an event-timing resolution of 1.7 ns. FPGA resource utilization is compared with representative open-source RFSoC control frameworks, showing a low BRAM footprint while retaining full-rate I/Q generation and acquisition. The RF output is characterized in terms of phase noise, noise spectral density, and inter-channel timing skew. End-to-end operation is validated on a superconducting qubit through resonator spectroscopy, Rabi, Ramsey, and relaxation measurements, yielding T1 = 6.94 us and T2* = 13.50 us. FIREQ can therefore be used both as a qubit-control platform and as an experimental environment for evaluating alternative control and readout IP architectures.

I. INTRODUCTION

FIREQ addresses scaling challenges in superconducting-qubit control by combining modular RFSoC firmware with a configurable software stack. It provides resource-efficient signal generation and acquisition, extensibility, and validated qubit operation.

  • Motivation: Existing RFSoC frameworks can incur host–device, reconfiguration, and data-movement overhead during high-repetition workflows, while extensibility remains important for custom IP integration.These constraints contribute to effective experiment latency alongside RF hardware and software–hardware interface performance.
  • Framework overview: FIREQ integrates signal generation, acquisition, and processing on an RFSoC platform using modular AXI-compliant peripherals and a PYNQ-based software stack.The software provides peripheral abstraction, hierarchical configuration, and dependency-aware updates for integrating new IP cores.
  • Contributions: FIREQ introduces on-the-fly envelope interpolation to reconstruct pulse envelopes from fewer reference samples, reducing waveform-memory requirements and enabling envelope reuse.The technique is designed to reduce hardware resource utilization while preserving programmable pulse generation.
  • Contributions: FIREQ maps decimated and accumulated acquisition buffers to UltraRAM, reserving higher-bandwidth BRAM for datapaths with stricter throughput requirements.This memory organization targets the BRAM constraints of FPGA-based I/Q generation and acquisition.
  • Validation: The framework characterizes phase noise, noise spectral density, and inter-channel timing skew, then validates operation through calibration and coherence measurements on a superconducting qubit.The reported validation includes standard qubit-control and readout experiments.

II. BACKGROUND

Qubit states are represented as normalized superpositions of computational-basis states, with measurement probabilities determined by coefficient magnitudes. The Bloch sphere provides a geometric representation in which polar angle encodes readout probabilities and azimuth encodes relative phase.

  • A. Qubit states: A quantum state can be expressed as a complex linear combination of N orthonormal basis states, with coefficient magnitudes determining measurement probabilities.For each coefficient, Px = |Cx|2 gives the probability of measuring the corresponding basis state.
  • A. Qubit states: Conventional qubit operation uses the ground and first excited states, |0⟩ and |1⟩, as the computational basis.The qubit state is written as |ψ⟩ = α|0⟩ + β|1⟩ with |α|2 + |β|2 = 1.
  • A. Qubit states: Qubit control changes state amplitudes and phases, whereas readout projects the state onto a measurement basis and repeated shots estimate outcome probabilities.The state is also represented geometrically on the Bloch sphere.
  • A. Qubit states: On the Bloch sphere, the polar angle θ determines readout probabilities and the azimuth ϕ represents the relative phase between the coefficients.A global phase can be factored out because it has no measurable effect on operations or measurement statistics.

B. Control and readout of superconducting qubits

Superconducting qubits are controlled through resonant microwave pulses whose amplitude, duration, and phase determine state rotations. FPGA/RFSoC platforms integrate waveform generation, acquisition, processing, and timing to support scalable qubit control and readout.

  • Control principles: Microwave pulse amplitude and duration determine the qubit rotation angle, while a 90° phase shift implements orthogonal equatorial rotations.Quadrature modulation can be produced through external analog mixing or direct digital synthesis followed by RF-DAC conversion.
  • FPGA/RFSoC platforms: FPGA/RFSoC control platforms integrate signal generation, acquisition, processing, and timing for superconducting-qubit experiments.Representative implementations and their characteristics are compared in Table I.
  • Related frameworks: QICK provides direct digital synthesis and acquisition with deterministic pulse sequencing through a soft-core processor and integrated peripherals.Its architecture targets low-latency control and readout and supports advanced protocols such as active reset and feedback-based error mitigation.
  • Related frameworks: Multiple-FPGA synchronization extensions enable distributed qubit control across boards.This supports scaling the control system beyond a single FPGA.
  • Related frameworks: RISC-Q proposes a Quantum Control System-on-Chip using RF generators, RF decoders, and specialized accelerators for multiple qubit technologies.The architecture extends beyond superconducting qubits to neutral-atom and trapped-ion platforms.

III. MOTIVATIONS AND DESIGN RATIONALE

Scaling superconducting-qubit systems motivates compact, resource-efficient control architectures that reduce interconnect burdens while preserving extensibility. FIREQ addresses this through modular hardware and software components connected by standardized interfaces and a client-server execution model.

  • Motivation: 26The passage identifies physical interconnects between the quantum processor and control electronics as a strong scaling constraint.
  • Design rationale: FIREQ serves as both a room-temperature FPGA control/readout platform and a testbed for resource-efficient mixed-signal processing IPs.Its modular architecture allows individual hardware blocks to be integrated, replaced, and evaluated with limited impact on the rest of the system.
  • System architecture: FIREQ comprises an FPGA firmware overlay, an RFSoC-resident server, and a host-side client.The server translates client requests into hardware commands and returns acquired data over the network, while the client defines and executes experiments.
  • Firmware architecture: The firmware connects modular peripherals to the APU through memory-mapped AXI4-compatible interfaces.Peripherals handle timing, signal generation, acquisition, pulse routing, and frequency multiplexing, with experiment configuration completed before execution.
  • Hardware operation: 35The supplied passage states that the signal-generation and acquisition IPs avoid interpolation or decimation to reduce working throughput.

1. Timing engine

FIREQ sequences time-critical drive and readout operations with trigger-based control and programmable pulse definitions. Its shared generator and routing architecture supports phase-coherent drive/readout generation while reducing duplicated generator hardware.

  • Timing engine: Up to 15 parallel one-clock-cycle triggers schedule time-critical drive and readout events.Drive triggers address signal generators, while readout triggers synchronize generation and acquisition.
  • Signal generation: The signal generator combines an envelope lookup table with a DDS engine to produce phase-coherent pulses at programmable carrier frequencies.Drive pulses can be followed by independently configurable readout pulses.
  • Signal generation: A memory-mapped FIFO indexes WDW memory, whose control words determine the drive-pulse sequence.The illustrated order is GATE 0, GATE 1, GATE 0.
  • Signal generation: Reusing one generator for drive and readout, with downstream multiplexing IPs, increases routing flexibility and reduces generator instances per qubit.This differs from architectures using separate drive and readout generators or dedicated multiplexed-readout blocks.
  • Signal generation: 15Each pulse is encoded by a 128-bit Wave-Definition Word, and each generator stores up to 256 words in internal WDW memory.
  • Signal routing: Pulse-level metadata specifies drive/readout type and routing destinations, including programmable subsets of drive DACs and common frequency-multiplexed readout channels.Readout waveforms are summed by a frequency-multiplexing IP before being sent to a shared readout channel.

4. Signal Acquisition

FIREQ reduces acquisition and waveform-memory demands through flexible output modes, UltraRAM buffering, and on-the-fly envelope interpolation. Its acquisition and generation architecture is evaluated against other RFSoC frameworks using post-implementation and normalized resource metrics.

  • Acquisition outputs: Full-rate raw I/Q and decimated or accumulated outputs support both demodulated-signal streaming and lower-memory energy or power measurements.Decimated samples provide a low-pass-filtered demodulated signal, while accumulated values measure acquired-pulse energy or power.
  • Memory allocation: UltraRAM stores decimated and accumulated acquisition buffers, reserving higher-bandwidth BRAM for datapaths with stricter throughput requirements.The design uses UltraRAM to address BRAM capacity constraints from envelope storage, lookup tables, and waveform buffers.
  • Envelope interpolation: Reduced reference samples are linearly interpolated on the fly, decoupling stored-sample count from pulse duration and reducing envelope-memory requirements.The interpolator retrieves two LUT samples using the integer address and computes the output from the address fraction.
  • Resource comparison: The resource comparison uses complete post-route RFSoC designs, while normalized metrics include only generation and acquisition subsystems and exclude control overhead and acquisition buffers.The compared implementations target the AMD Zynq UltraScale+ RFSoC ZCU216.
  • Resource comparison: QubiC per-qubit resources could not be estimated because its meta-HDL-generated hierarchy obscures channel boundaries and prevents straightforward static isolation.The comparison reports total FPGA utilization for QubiC, but not a normalized per-qubit estimate.
  • Envelope interpolation: A single DSP slice implements the interpolation function, adding five clock cycles compared with three cycles for direct LUT lookup.The implementation uses the UltraScale+ DSP pre-adder to compute the sample difference, while the DDS path executes in parallel.

7. Resource-utilization comparison

FIREQ is evaluated against open-source RFSoC frameworks using normalized per-qubit resource metrics and software-execution considerations. It maintains a low BRAM footprint while using dependency-aware updates and streamed acquisition to reduce repeated-workflow overhead.

  • Hardware resources: The resource comparison uses openly available repositories and standard or recommended builds for the evaluated frameworks.HiSEP-Q 2.0 is excluded because a valid ZCU216 implementation could not be obtained from its public repository.
  • Hardware resources: Normalized per-qubit metrics estimate resources for drive and readout generation and acquisition when total device utilization is not directly comparable.The comparison accounts for shared hardware blocks across qubits; QubiC is excluded because its hierarchy does not permit unambiguous per-qubit decomposition.
  • Hardware resources: FIREQ maintains a low BRAM footprint comparable to RISC-Q while retaining flexibility and reconfiguration capability.Its envelope interpolation feature slightly increases DSP utilization, while LUT and FF consumption remains comparable across evaluated solutions.
  • Software execution: Streamed acquisition and host-side offloading separate experiment management from hardware execution and reduce effective runtime overhead.The client–server architecture is designed to reduce data-movement and host–device interaction costs.
  • Software execution: Dependency-aware updates recompute only configuration changes associated with modified parameters between consecutive sweep iterations.This targets calibration and characterization sweeps whose repeated iterations can reach tens to hundreds of millions.

1. Client

The FIREQ client presents a high-level experiment interface while the server handles communication, hardware configuration, execution, and runtime errors through separate threads. This organization supports concurrent command reception, experiment execution, and result transmission.

  • Client: The client defines experiments through a declarative, compiler-like syntax and converts them into hierarchical hardware configurations.Parameters may be expressed in physical units or hardware-specific quantities such as clock cycles.
  • Server: The server uses sender, receiver, and execution threads with separate responsibilities for packets, control commands, and hardware operations.The execution thread configures hardware, executes experiments, and handles runtime errors.
  • Server: Hardware access is restricted to the execution thread, while incoming commands and outgoing results use shared queues.This avoids race conditions and allows command reception, experiment execution, and result transmission to proceed concurrently.
  • Server: Acquisition batches, zero-copy memory views, and binary chunks reduce per-shot software overhead during data transfer.The client reassembles binary chunks into complete floating-point arrays using compact metadata headers.

3. Firmware abstraction layers

FIREQ uses a tree-based, driver-centric abstraction in which hierarchical configuration propagates through modular hardware nodes. Its characterization combines RF-noise and timing measurements with phase-noise evaluation of generated tones.

  • Firmware abstraction layers: Each IP instance is represented as a node in a hierarchical system tree with standardized configuration and dependency-aware propagation.Nodes can represent peripherals or dynamically created child objects such as pulses and envelopes.
  • Firmware abstraction layers: The system tree applies hierarchical configuration recursively from the system root to affected peripheral nodes and supports callback-based returns.Configuration can modify hardware parameters and create or update child nodes.
  • Instrument characterization: The instrument is characterized using phase noise, noise spectral density, and inter-channel timing skew measurements.Phase-noise measurements use continuous RFSoC tones and multiple carrier frequencies and output amplitudes.
  • Instrument characterization: At 1 MHz offset, the highest-output-amplitude phase noise is below -116 dBc/Hz, a level reported as compatible with high-fidelity gate operation.At larger offsets, low-amplitude measurements approach the instrument noise floor.
  • Instrument characterization: Noise spectral density is estimated from 50-ohm termination and differential-DAC measurements analyzed with Welch’s method.The spectra cover measurements between DC and 1 MHz using 8M samples acquired at 8MSps.
  • Instrument characterization: The relative timing-skew measurement uses simultaneous pulse pairs across channels whose DACs belong to different RFSoC tiles.The resulting distribution has an absolute mean skew of approximately 1.8 ps and a standard deviation of 0.84 ps.

B. Qubit measurements

FIREQ was validated on a superconducting qubit through readout calibration and measurements of relaxation and dephasing times. The resulting coherence values were obtained from fitted exponential curves, with software overhead varying by experiment duration.

  • Qubit measurements: Readout resonator spectroscopy and punch-out calibrate the readout frequency, amplitude, and gain for operation in the dispersive regime.The gain is selected to provide adequate signal-to-noise ratio while remaining compatible with the calibrated response.
  • Qubit measurements: T1 = 6.94 µs and T2* = 13.50 µs were obtained by fitting the corresponding exponential relaxation and dephasing curves.The measurements are shown in Fig. 9(e) and (f).
  • Qubit measurements: Calibration procedures combine parameter sweeps with repeated-shot acquisition, producing total shot counts from millions to tens of millions.The execution path was designed to minimize firmware, software, and communication overhead.
  • Qubit measurements: Short 3 µs-per-iteration experiments incur up to 26% software overhead, whereas longer routines amortize the fixed cost to roughly 1%.The per-iteration software latency is described as essentially constant across experiments.
  • Qubit measurements: The qubit-characterization results obtained with FIREQ are comparable to measurements obtained using QICK at the University of Milano Bicocca.The comparison is reported for the corresponding qubit characterization experiments.

VI. CONCLUSIONS AND FUTURE WORK

FIREQ provides precisely timed RF control and frequency-multiplexed readout with high temporal resolution, low BRAM usage, and reduced overhead in long calibration sweeps. Future work targets larger-scale and multi-board capabilities.

  • 9.3 GHz maximum frequency, 107 ps pulse-duration resolution, and 1.7 ns event-timing resolution characterize FIREQ’s RF pulse generation.
  • Low BRAM utilization is maintained alongside full-rate I/Q generation and acquisition in comparison with representative open-source RFSoC frameworks.
  • Approximately 1–1.5% relative software and communication overhead is achieved for longer experiments in calibration sweeps comprising millions of repeated shots.
  • Larger qubit counts, flux-bias channels, and synchronized multi-board operation remain targets for future extensions.

Appendix A: Parallel envelope generation with interpolation

Parallel envelope generation matches the RF DAC rate by producing multiple samples per generator cycle, but replicated memory banks reduce effective envelope capacity.

  • N=16 samples are generated in parallel per clock cycle, requiring an approximately 581 MHz generator clock for a 9.3 GSps RF DAC.
  • N replicated memory banks are required because each bank stores the same reference-envelope data rather than partitioning it across lanes.
  • For N=16, conventional 16 kSample envelope capacity becomes 1 kSample for interpolated reference envelopes.
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