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High-Performance Low-Power Adiabatic Systolic Array Design in Advanced FinFET Nodes

Jun Yin, Liangtao Dai, Yimin Gao, Mircea R. Stan

arXiv:2608.30058v1cs.AR

TL;DR

Adiabatic logic has been limited by the slow transitions traditionally needed for charge recovery, creating a challenge for high-performance hardware. The paper develops a PFAL-based AL MAC systolic array and resonant 4-phase power-clock system in 16 nm FinFET technology. Simulations report lower power at 1 GHz, including 42% and 36% reductions at the core and system levels.

  • Problem

    Adiabatic logic requires transition times longer than the circuit time-constant for lower power, historically constraining it to low clock frequencies.

  • Method

    The paper builds a PFAL-based AL MAC systolic array with digital interfaces and a resonant 4-phase sinewave PCK generator co-designed for the array.

  • Results

    42% and 36% power reductions are achieved at 1 GHz for the AL MAC systolic array at the core and system levels, respectively, versus digital counterparts.

  • Takeaways & Limitations

    Advanced FinFET nodes allow adiabatic circuits to maintain charge-recovery behavior at GHz frequencies while reducing power in the evaluated MAC systolic array.

Abstract

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Adiabatic logic has traditionally been recognized as a low-power solution but constrained to low clock speeds to preserve adiabatic behavior. For advanced FinFET nodes, however, clock frequencies have plateaued due to power/thermal concerns (dark silicon) even as the intrinsic device speeds have continued to scale. This convergence opens an opportunity for adiabatic logic to maintain adiabatic behavior even at GHz clocks. We demonstrate an adiabatic logic (AL) design methodology through a MAC systolic array implemented in commercial 16 nm FinFET technology with a resonant 4-phase power clock (PCK) generator, including digital-to-AL and AL-to-digital interfaces. Simulations show that the AL MAC systolic array at 1 GHz achieves power reductions of up to 42% and 36% at the core and system levels, respectively, compared to digital counterparts. Scaling to more advanced nodes should provide even better power/performance metrics.

I. INTRODUCTION

AI workloads require energy-efficient matrix-multiplication hardware at sustained clock frequencies, while conventional systolic arrays face rising power and adiabatic logic has historically been limited to low speeds. This work proposes a 16 nm FinFET AL MAC systolic array with a resonant 4-phase power clock and interfaces to sustain 1 GHz operation with reduced power.

  • Motivation: AI workloads increase demand for efficient hardware that accelerates matrix multiplication at sustained clock frequencies.Matrix multiplication is central to modern computing, image processing, and signal processing.
  • Motivation: Conventional digital systolic arrays exploit data reuse but face sharply increasing CV 2f power as frequency rises.Their regular two-dimensional structure makes them important for AI accelerators, but the power trend limits efficiency.
  • Motivation: Advanced FinFET nodes create an opportunity for adiabatic circuits to preserve charge-recovery behavior at approximately 1 GHz.Intrinsic RC time-constants have reached the picosecond range while clock frequencies have plateaued because of power and thermal concerns.
  • Contributions: The paper develops PFAL-based AL gates, MAC blocks, and dual-rail digital-to-AL and AL-to-digital conversion circuits.The methodology is demonstrated in an AL MAC systolic array integrated with digital FIFOs and converters.
  • Contributions: A resonant 4-phase AC PCK generator using coupled 2-phase LC oscillators and shunt NFETs supplies synchronized sinusoidal clocks at low input power.The generator is co-designed to efficiently drive the AL array.

II. BACKGROUND

A traditional MAC unit pipelines multiplication and accumulation through registered arithmetic stages. Its multiplier uses partial-product generation and carry-save compression to reduce carry-propagation delay before accumulation.

  • Traditional MAC structure: A traditional MAC unit performs multiplication in the first stage and accumulation in the second.Intermediate registers balance delays between the stages for high clock frequencies.
  • Traditional MAC structure: The multiplier generates partial products with bitwise AND operations and compresses them using parallel carry-save adders.The CSA structure reduces intermediate results to two rows while avoiding carry propagation delays.
  • Traditional MAC structure: Pipelined registers support efficient shift-and-add operations and timing balance across the multiplier and accumulator.This organization supports operation at high clock frequencies.

B. Adiabatic logic with FinFET

Adiabatic logic reduces power by recovering charge, but traditionally required slow transitions; advanced FinFET nodes and GHz-level clocks create an opportunity for high-performance AL. The paper develops resonant sinewave power-clock generation and co-designs it with a 4-phase AL systolic array.

  • Adiabatic logic recovers and reuses charge stored on transistor capacitances instead of dissipating it as heat.
  • AL power savings require transition times exceeding 4RC/α, while modern FinFET nodes provide picosecond-range RC time-constants that can support GHz operation.
  • Sinewave AC power clocks are favored over trapezoidal clocks because they can reduce overall power and are easier to use efficiently in the proposed AL scheme.
  • The design estimates AL loads as CLoad1 = CLoad2 = 162 fF and RLoad1 = RLoad2 = 7.5 kΩ for a 2×2 array with approximately 2550 AL buffers.
  • SVT cross-coupled inverters with thick-oxide shunt NFETs achieve 62.5% peak clock efficiency at 7 kΩ and remain above 60% at 7.5 kΩ.

A. AL Complex Digital Computing Logic

The AL computing datapath builds multipliers and adders from PFAL-based, dual-rail circuits synchronized to a 4-phase power clock. Its pipeline uses AL delay elements and resettable buffers to support accumulation.

  • AL multiplier: The AL multiplier uses dual-rail complementary signals and buffered AL full-adder inputs to synchronize computation through the 4-phase PCK scheme.The design targets 4-bit operands and constructs a 4×4 AL carry-save-adder array for shift-and-add multiplication.
  • AL accumulator: The AL KSA implements 8-bit accumulation using AL black cells, pre-cells, gray cells, XOR gates, and buffers.Black cells provide parallel-prefix carry logic, while gray cells complete final carry computation.
  • Pipeline support: The AL delay element provides pipeline storage through four serial AL-buffer stages rather than a conventional flip-flop.Its first buffer includes reset functionality, while the remaining three are regular AL buffers.

B. AL MAC PE Design

The AL MAC processing element combines PFAL-based buffering, multiplication, accumulation, and delay elements, with converters connecting AL computation to digital interfaces. At 1 GHz, its cycle energy is substantially below a comparable digital PE.

  • PE construction: A 4-bit AL MAC PE integrates AL buffers, a 4-bit multiplier, an 8-bit KSA, and resettable AL delay elements.Each component is constructed from PFAL gates.
  • Energy comparison: 50% lower Ecyc is achieved by the AL PE than by the digital PE at 1 GHz.The AL PE’s minimum Ecyc across frequencies is lower than the digital PE’s at 0.8 V.
  • Digital interfaces: DALC and ALDC circuits connect the AL MAC core to digital FIFOs, memories, and registers.The basic converter changes rectangular digital signals into sinusoidal signals using a 4-phase PCK supply.

D. Architecture of AL MAC Systolic Array

The AL systolic-array architecture combines modified digital FIFOs, AL tiles, delay elements, and digital interfaces to stream matrix operands through a 2×2 grid. Four-phase timing requires inputs to remain stable across all clock phases.

  • Data movement: Modified digital FIFOs hold data for 4 cycles when driving DALC modules, unlike conventional FIFOs that output data each clock cycle.A resettable counter tracks the required hold cycles.
  • Data movement: The architecture uses four 4-bit input digital FIFOs for two row-wise and two column-wise data streams.The array’s dual-rail AL buses carry the matrix-multiplication data across the hierarchical grid.
  • Interface operation: The AL MAC systolic array produces input and output waveforms through digital interfaces.The architecture is designed to coordinate digital data streams with the AL timing scheme.
  • Array architecture: The 2×2 AL MAC systolic array contains four AL tiles with AL delay elements between adjacent tiles for pipelining.Tile types are differentiated by their DALC counts to improve area and energy efficiency.

V. SIMULATION RESULTS

Simulation integrates the resonant 4-phase clock generator with the AL array and digital FIFOs, then compares power and normalized cycle energy against digital designs. The AL system reduces power and maintains lower cycle energy as array size grows.

  • Simulation setup: The integrated 2×2 array uses a resonant 4-phase clock generator and digital FIFOs to provide functional operation at the simulated interface.Reset initializes the array to zero before data streaming begins.
  • Power results: 42% lower power is achieved by the AL systolic MAC core, which consumes 174.4 µW versus its digital counterpart.Pure AL PEs excluding converters consume 38.1 µW.
  • Power results: 36% lower power is achieved by the AL system at 1 GHz, consuming 537.1 µW versus 839.5 µW for the digital system.The AL system includes the AL array, digital peripherals, and a 4-phase clock generator consuming 102.7 µW.
  • Scaling results: Approximately 22% lower Ecyc is achieved by the AL MAC systolic array with peripherals at a 16×16 size.The 2×2 digital MAC systolic array with peripherals is the normalization baseline at 1 GHz and 0.8 V.
  • Projected comparison: The projected normalized AL design consumes 16.04 mW and provides 7.98 TOPS/W after normalization to 16 nm, 16×16 arrays, and INT4 throughput.The comparison uses technology and precision normalization assumptions described for the literature baselines.

C. Clock-Generator Non-Ideality Analysis

The analysis evaluates how finite inductor quality factor affects resonant four-phase power-clock generation and AL systolic-array operation at 1 GHz.

  • At an effective quality factor of approximately 14, the clock generator maintains stable four-phase generation and correct AL systolic-array operation.The test uses 4-finger devices in the cross-coupled inverter pairs.
  • At an effective quality factor of approximately 9.8, increasing the cross-coupled devices to 6 fingers keeps the generator functional.The larger devices provide stronger negative resistance.
  • The voltage/frequency characterization distinguishes functional operating points from failures and reports normalized average power relative to the 1 GHz, 0.8 V case.
  • Finite-Q degradation primarily reduces oscillation margin, while increased negative resistance can partially compensate for additional tank loss.

D. Voltage/Frequency Operating Region

The AL systolic array requires increasing power-clock amplitude as frequency rises, while lower amplitudes can substantially reduce power when correct operation is maintained. Area and energy-area analysis evaluates whether these gains persist after accounting for AL overhead.

  • D. Voltage/Frequency Operating Region: The voltage/frequency sweep isolates the intrinsic AL systolic-array limit from the resonant clock generator's startup limit.
  • D. Voltage/Frequency Operating Region: At 1 GHz, the AL systolic array operates correctly with a PCK amplitude of 0.5 V, whereas 2 GHz requires approximately 0.7 V.Below these limits, reduced device overdrive and signal swing prevent reliable charge recovery and logic evaluation within one clock period.
  • D. Voltage/Frequency Operating Region: At 1 GHz, reducing PCK amplitude from 0.8 V to 0.5 V lowers normalized average power from 1.0 to 0.165 while maintaining correct operation.Only functionally correct operating points are included in the energy comparison.
  • E. Core Area and Energy-Area Analysis: The AL MAC core has an estimated 1.35× active-area overhead over the static CMOS MAC core.The estimate uses a device-count model including required AL phase-alignment buffers.
  • E. Core Area and Energy-Area Analysis: At 1 GHz, the AL MAC core achieves a 42% power reduction and normalized energy per cycle of 0.58.
  • E. Core Area and Energy-Area Analysis: Even with estimated area overhead, the proposed AL MAC core achieves a 22% lower energy-area product than the static CMOS MAC core.

VI. CONCLUSIONS

The paper presents a complete AL MAC systolic-array methodology integrating PFAL building blocks, digital peripherals, and a resonant four-phase power-clock generator. In 16 nm FinFET technology, the design reduces power and energy-area product relative to digital counterparts, while projected scaling reaches 7.98 TOPS/W.

  • The methodology spans PFAL gate-level building blocks through system-level integration with digital peripherals.
  • The resonant four-phase power-clock generator drives the array at 1 GHz with over 60% efficiency and eliminates external tank capacitors.
  • In 16 nm FinFET technology, the AL MAC systolic array achieves 42% and 36% power reductions at the core and system levels, respectively.
  • After accounting for 1.35× area overhead from dual-rail AL gates, the design achieves a 22% lower energy-area product than its digital counterpart.
  • Scaled to a 16×16 array, the projected energy efficiency reaches 7.98 TOPS/W and surpasses state-of-the-art digital accelerators.
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