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Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks
Simon Richter, Darío Fernández Khatiboun, Maryam Sadeghi, Milad Zamani, Farshad Moradi
TL;DR
Digital SNNs repeatedly access synaptic-weight SRAM during time-stepped processing, making memory power a central design concern. The paper proposes activity-based allocation across non-uniform SRAM banks, supported by address mapping, neuron sorting, and automatic configuration exploration. It reports up to 61% memory-access-power reduction with 2.1× lower area overhead than a uniformly partitioned memory achieving comparable reduction.
Problem
Synaptic-weight SRAM access is a main contributor to power consumption in digital SNN implementations, while uniformly partitioning memory can impose area and power overheads.
Method
The paper allocates weights according to pre-synaptic firing activity across non-uniform SRAM banks and uses address mapping, neuron sorting, and automatic configuration exploration.
Results
61% memory-access-power reduction is reported with a 2.1× lower area overhead than a conventional design, while comparable reduction is achieved against uniformly partitioned memory.
Takeaways & Limitations
Across multiple networks and datasets, the architecture reduces synaptic-memory access power at lower area overhead than uniformly partitioned memory.
Abstract
from arXiv · showhide
Spiking Neural Networks (SNNs) naturally excel in processing temporally rich and sparse data. However, because of their time-stepped processing, memory access, specifically to synaptic weights stored in SRAM (static random-access memory), tends to dominate total power consumption. To address this issue, without incurring a large area overhead, we propose to leverage the greatly varying average firing rate of neurons in the network to efficiently allocate synaptic weights to an on-chip memory consisting of multiple non-uniformly sized memory banks. By assigning weights of frequently firing neurons to shallow, low-access cost memory and less actively accessed weights to deeper, high-density memories, the average power consumption of the synaptic weight memory is decreased without incurring a large area overhead. To benchmark our proposed architecture and find optimal configurations of memory arrangements, we perform an automatic exploration based on application requirements and hardware constraints. For memory designs synthesized in 28-nm CMOS technology, we show that our architecture can achieve a synaptic weight memory access power reduction of up to 61\% compared to a conventional design, with a 2.1$\times$ lower area overhead, as compared to a traditional uniformly partitioned memory bank that achieves a comparable reduction.
I. INTRODUCTION
SNN synaptic-weight SRAM access is a major power contributor, motivating a non-uniform memory that assigns weights according to neuron firing activity. The paper combines activity-based allocation, address mapping, neuron sorting, and automatic memory-configuration exploration to reduce access power with limited area overhead.
- SRAM access to synaptic weights is a main contributor to power consumption in recent digital SNN implementations.
- Non-uniform SRAM partitioning assigns frequently accessed weights to shallow, lower-access-cost banks and less frequently accessed weights to deeper, denser banks.The allocation uses the firing activity of pre-synaptic neurons.
- The architecture combines shallow low-access-cost memories with deeper high-density memories by leveraging variation in SNN neuron firing rates.
- An address-mapping and neuron-sorting scheme simplifies the access order to individual memory banks.
- The study investigates non-uniform firing distributions across neuromorphic networks and performs automatic exploration of memory arrangements under area and access-power objectives.The exploration seeks maximal access-power reduction at the smallest manageable area overhead.
- 61% access-power reduction is reported with a 2.1× lower area overhead than a conventional design.
II. NEUROMORPHIC ACCELERATORS
Neuromorphic accelerators use time-stepped processing in which synaptic weights are repeatedly accessed while neurons are updated. SNN hardware spans analog and digital designs, with digital architectures offering flexibility and scalability.
- SNN accelerators update neurons within predefined timesteps, during which synaptic weights are accessed sequentially.
- Neuromorphic accelerator designs range from analog to fully digital architectures.
- Digital designs have shown greater flexibility and scalability than analog alternatives.
III. PROPOSED MEMORY ARCHITECTURE
The proposed memory presents multiple non-uniform SRAM banks as one continuous address space and allocates weights using firing-activity-based sorting. This places frequently accessed weights in shallow banks while avoiding bank look-up logic.
- The synaptic-weight memory uses individually addressable SRAM banks of varying depths, combined into one continuous address space for the SNN controller.The shallowest banks occupy the lowest address ranges and have the lowest access power.
- Post-training profiling uses firing rates, network topology, and accelerator architecture to allocate neuron and synaptic-weight addresses.
- In fully connected layers, weights from the most actively firing pre-synaptic neurons are assigned to the shallowest memory banks.The pre-synaptic neuron ID forms the least significant bits of the weight address.
- Convolutional-layer assignment requires additional care because multiple neurons share kernel weights and receptive fields depend on output-neuron position.
B. Memory Control Logic
The control logic coordinates clock gating, bank selection, output selection, and address offsets for SRAM macros of different sizes. Together, these blocks support access to a continuous memory space assembled from individually addressable banks.
- B. Memory Control Logic: The architecture uses pre-compiled SRAM macros of varying sizes, labeled Bank 0 through Bank n, with peripheral control logic.
- B. Memory Control Logic: Clock-gating cells disable the clock to inactive memory banks without glitches.Each bank’s clock is controlled by its enable signal.
- B. Memory Control Logic: The bank-select decoder generates a one-hot enable signal for the bank selected from the input weight address and bank depths.
- B. Memory Control Logic: Output-select logic drives Q with data from the previously selected bank to account for SRAM read timing.
- B. Memory Control Logic: Address-offset control produces per-bank offsets so concatenated banks appear as one continuous address space to the SNN controller.
A. Benchmark Network Setup
The benchmarks cover four SNN applications using two fully connected and two convolutional networks, sized for either 32KB or 64KB synaptic memories. The traditional and non-uniform architectures use identical quantized networks and achieve the same accuracy.
- Datasets and architectures: Four datasets span image recognition, gesture recognition, and two keyword-spotting tasks.N-MNIST and DVSGesture use convolutional networks, while GSC and HD use fully connected SNNs.
- Training and sizing: The networks use LIF neurons, surrogate-gradient training, and 8-bit weight quantization.All networks were trained with snnTorch using backpropagation with surrogate gradient descent.
- Training and sizing: The two larger networks contain roughly 65,000 parameters and fit in 64KB memories, while the smaller networks fit in 32KB memories.Networks (2) and (3) target 64KB; networks (1) and (4) target 32KB.
- Accuracy comparison: Both memory architectures produce no difference in accuracy when running the same networks with the same quantization.The comparison uses identical network deployments across the traditional and proposed memories.
B. Memory Access Distribution
The study derives synaptic-weight access rates from recorded neuron firing activity and explores non-uniform memory organizations under hardware constraints. Accesses are strongly concentrated in a small subset of weights, especially for convolutional networks.
- Access profiling: Synaptic-weight access rates are derived from test-set firing activity and the accelerator’s memory access order after training.The resulting frequency distribution is summarized as the share of total accesses reaching the most frequently read weights.
- Access concentration: Roughly one-third of keyword-spotting memory accesses target only 10% of the most frequently accessed weights.This concentration occurs for the networks trained on the KWS tasks.
- Access concentration: 54.1% and 71.0% of accesses target the top 10% of weights in the N-MNIST and DVS convolutional networks, respectively.The convolutional networks exhibit greater access-rate imbalance than the fully connected KWS networks.
- Design-space exploration: An automated design-space exploration searches memory arrangements for optimal configurations under application and hardware constraints.The exploration assumes one 8-bit synaptic weight per addressable word to support single-weight loading for sparse spikes.
- Design-space exploration: SRAM macros are restricted to sizes from 1KB to 32KB, with the lower bound set by the absence of further access-power reduction.The upper bound is imposed by the available memory compiler.
- Design-space exploration: The exploration evaluates 202 assemblies for 32KB memories and 686 constrained combinations for 64KB memories.Synthesizable Verilog is automatically generated for each combination, including memory macros and control logic.
D. Synthesis Setup
The memory designs are evaluated through 28-nm CMOS synthesis and switching-activity-based read-power estimation. Results are reported relative to a conventional single-bank synaptic memory, across configurations matched to benchmark network sizes.
- Synthesis conditions: The uniform and non-uniform memory designs are synthesized in 28-nm CMOS at 100MHz, 25°C, 1V, and the Typical-Typical corner.Foundry-provided memory compiler tools generate the individual SRAM macros.
- Power evaluation: Read-access power is evaluated using a switching activity file generated for each benchmark network.The setup is intended to capture memory read activity during the benchmark workload.
- Normalization: Area and access-power results are expressed as percentage changes relative to a conventional single-SRAM-bank synaptic memory.The reported values cover selected well-performing non-uniform memories from the design-space exploration.
- Configuration mapping: Configurations A and B target 64KB memories for networks 2 and 3, while configurations C and D target 32KB memories for networks 1 and 4.Reported read-access power includes both dynamic and leakage power during inference.
V. DISCUSSION
The discussion reports substantial power-area benefits, low control overhead, broad benchmark behavior, and deployment flexibility for the non-uniform memory architecture. The reported comparisons are made against conventional or uniformly partitioned memories.
- Power/Area trade-off: Up to 63% memory-access-power reduction is achieved with an 18% area overhead versus a single 32KB synaptic memory.The non-uniform architecture is compared with both a conventional single bank and uniformly sized banks.
- Power/Area trade-off: Configuration D achieves greater access-power reduction than a uniform 8x4KB memory at a 2.1× lower area overhead.Uniform partitioning can obtain similar power reduction but incurs greater overhead because some banks are heavily underutilized.
- Control overhead: Control logic occupies less than 1% of total memory area across the selected non-uniform configurations.This overhead is reported across all selected configurations.
- Control overhead: Added control logic introduces no additional memory-access clock cycles because its delay is negligible relative to the SRAM macros’ timing constraints.The paper identifies this as suitable for real-time applications.
- Benchmark variation: The access-power-reduction difference across benchmarks is at most about 14%, indicating generalization across varying network sizes and topologies.Convolutional networks targeting N-MNIST and DVS perform better because their accesses are more concentrated in frequently accessed weights.
- Flexibility: Smaller networks can use shallower memory regions while unused macros are disabled for improved efficiency.This provides flexibility for deploying networks of varying sizes without requiring full memory occupancy.
VI. CONCLUSION
The proposed non-uniform memory architecture allocates synaptic weights across differently sized banks according to average neural firing activity. Across multiple networks and datasets, it reduces memory-access power while requiring lower area overhead than uniformly partitioned memory.
- Weights are allocated to memory banks of varying sizes based on average neural firing activities.The architecture applies non-uniform memory organization to SNN synaptic weights.
- The architecture includes an efficient address allocation scheme that eliminates the need for bank lookup logic.
- Memory-access power is reduced drastically compared to a single synaptic weight memory bank.
- The proposed design achieves significantly lower area overhead than a uniformly partitioned memory.