PaperlayerView exact revision on arXiv

Source-linked AI summary

Non-Blocking Fault Current Limiting Control of Half-Bridge MMCs for MTDC Transmission

Pengxiang Huang, Shahil Shah

arXiv:2609.00286v1eess.SY

TL;DR

MTDC protection requires faulted areas to be isolated while healthy terminals continue operating, but HB-MMCs can block before DCCBs clear DC faults. The paper develops AFCL controls with stability-oriented design and validates them in two MTDC configurations. Simulations show non-blocking fault ride-through, bounded converter currents, and smaller series CLRs than prior reports.

  • Problem

    HB-MMCs lack inherent DC fault-current suppression, which can cause converter blocking before DCCBs clear faults and interrupt operation in healthy MTDC areas.

  • Method

    The paper combines VAI-FCL and TB-FCL controls, adds VR-ACL for arm-overcurrent mitigation, and designs them under converter and network stability constraints.

  • Results

    Two representative MTDC case studies validate non-blocking DC fault ride-through; in one case, currents remain below the 3.81 kA blocking threshold and recover within approximately 150–200 ms.

  • Takeaways & Limitations

    The proposed AFCL strategy limits fault current while allowing DCCBs to isolate faults, with series CLRs significantly smaller than those reported in existing literature.

Abstract

from arXiv · show

A key protection requirement in multiterminal HVDC (MTDC) transmission systems is to selectively isolate faulted areas using DC circuit breakers (DCCBs) during DC faults while keeping the rest of the systems in operation. However, in MTDC systems using half-bridge modular multilevel converters (HB-MMCs), the lack of inherent fault current suppression capability in HB-MMCs can cause converter blocking before fault clearance by DCCBs. This work presents an active fault current limiting (AFCL) control strategy for HB-MMCs to mitigate DC fault currents, thus avoiding converter blocking and reducing the breaking capability required of DCCBs. In addition, a systematic approach is proposed to design the AFCL control strategy under converter and network stability constraints. The effectiveness of the proposed strategy is demonstrated through PSCAD on two typical MTDC systems during DC faults.

I. INTRODUCTION

HB-MMCs lack inherent DC fault-current suppression, so they may block before DCCBs clear faults, disrupting healthy MTDC terminals. The paper proposes coordinated AFCL controls and systematic design guidance to enable non-blocking ride-through with smaller passive CLRs.

  • HB submodules are lower-cost and lower-loss but cannot generate the negative voltage needed to limit DC fault current.
  • Passive current-limiting reactors reduce fault-current rise but add cost and space demands, while large reactors can reduce response speed and stability margins.
  • Bypassing all submodules immediately can force exponential fault-current decay, but delayed DCCB operation may cause severe arm overcurrent and valve protection.
  • The proposed AFCL strategy combines VAI-FCL, which limits fault-current rise, with TB-FCL, which caps the peak by temporarily bypassing selected submodules.
  • The strategy targets passive CLRs of 50 mH or less per MMC station, compared with 150–200 mH typically required by existing AFCL methods.
  • The fault-current model shows that equivalent duty ratio D governs the initial rise rate, whereas attenuation behavior can limit the current maximum.

A. Virtual Arm Impedance-Based FCL Control (VAI-FCL)

VAI-FCL adds a virtual arm impedance through circulating-current feed-forward control. Its derivative action responds to rapid fault-current changes while filtering and stability-oriented design limit interactions with existing controls.

  • VAI-FCL reduces the equivalent duty ratio by modifying the common-mode voltage reference through an additional circulating-current feed-forward loop.
  • The controller is equivalent to inserting a virtual series impedance into each arm inductor, with derivative behavior selected to limit fault-current rise.
  • A low-pass filter extracts the DC component, reduces interactions with circulating-current control, and suppresses high-frequency amplification from the derivative term.
  • With Lv = 0.2 and fc = 5 Hz, the virtual-impedance magnitude at 60 Hz reaches 6.26, potentially amplifying a small 60-Hz component and distorting arm current.
  • During steady state, VAI-FCL output is virtually zero, while rapid fault-current increases automatically introduce the virtual inductor without relying on fault detection.

B. Temporary SM Bypass-Based FCL Control (TB-FCL)

TB-FCL uses a hysteresis-based DC-current trigger to temporarily bypass submodules and limit fault-current peaks, while remaining inactive during normal operation.

  • TB-FCL operating principle: TB-FCL leverages exponential DC-current decay to directly limit the HB-MMC fault-current peak.The decay occurs when D satisfies 0 ≤ D < Req/(2√(Leq/Ceq)).
  • TB-FCL operating principle: The DC-bus current idc passes through a nonlinear hysteresis block with thresholds Imax and Imin, producing a binary switching signal.The signal is converted into the modulation factor D∆, which adjusts the number of inserted submodules per arm.
  • Normal operation: During startup and steady state, idc remains below Imax, so D∆ stays at 1 and TB-FCL does not affect normal MMC switching.This remains true even with power fluctuation, provided idc stays below Imax.
  • Fault operation: When idc exceeds Imax during a DC fault, the modulation factor switches to 1 − Kd, temporarily bypassing submodules to reduce the current.The supplied passage introduces this switching condition but truncates the example value for Kd.

C. Sequence of Events WO/ and W/ the AFCL Strategy

The AFCL protection sequence combines immediate VAI-FCL action with threshold-triggered TB-FCL operation after fault detection. The controls alternate until DCCBs isolate the faulted area and the DC current recovers.

  • Fault detection: A DC fault creates a traveling wave that propagates to the MMC DC bus, activating fault detection.The sequence begins at t0 and detection is activated at t1 to discriminate the fault.
  • VAI-FCL response: At t1 ∼ t2, VAI-FCL inserts virtual arm inductors into all six arms to limit the rate of rise of idc.The current initially increases because of MMC submodule discharge.
  • TB-FCL response: When idc reaches Imax at t2, TB-FCL activates to limit the peak value of idc.This adds the temporary-bypass action after the initial VAI-FCL response.
  • TB-FCL recovery: Between t2 and t3, bypassing many submodules causes idc to decrease; at Imin, TB-FCL deactivates and normal submodule insertion resumes.The control therefore returns the submodules to their normal insertion and bypass modes after the current falls.
  • Repeated limiting: If the DC fault persists, submodule discharge increases the fault current again, causing VAI-FCL to reinsert virtual reactors.VAI-FCL and TB-FCL then operate alternately and repetitively until fault clearance.
  • Fault isolation: After DCCBs isolate the faulted area at t5, idc begins decreasing and recovers toward its steady-state value.The figure caption identifies the sequence as MMC protection using both VAI-FCL and TB-FCL.

A. Design of VAI-FCL Control

The VAI-FCL adds a virtual-impedance effect through circulating-current control, requiring selection of Lv that preserves controller and system stability. Increasing Lv can improve limiting action but may introduce instability under control delay and grid-impedance interactions.

  • Controller stability-oriented design: The VAI-FCL is equivalent to adding a derivative term to the circulating-current control, so control delay and Lv selection affect loop stability.The control delay reduces phase margin, requiring stability-oriented selection of Lv.
  • Controller stability-oriented design: When Lv increases from 0.15 to 0.2, the circulating-current response contains a stable oscillation after MMC startup at t = 0.4 s.The compared selections are Lv = 0.15 (red) and Lv = 0.2 (blue).
  • Controller stability-oriented design: The Hurwitz criterion determines whether the circulating-current loop remains stable and provides the maximum stability-compatible value Lv,max.A smaller Lv has less impact on the circulating-current controller.
  • System stability-oriented design: With 200 µs control delay, the MMC DC-impedance phase stays between -90° and 90° below approximately 1.5 kHz, while negative damping appears from approximately 1.5 kHz to 3.75 kHz.The delayed impedance may interact unfavorably with the HVDC-grid impedance in that frequency range.
  • System stability-oriented design: At Lv = 0.15, grid and MMC impedances intersect near 1750 Hz with phase difference exceeding 180°, whereas Lv = 0.1 or 0.05 mitigates the unstable resonance condition.Reducing Lv decreases the negative damping but may reduce VAI-FCL current-limiting capability.

3) Iterative Design Process for Selecting Lv:

The proposed Lv design process combines controller and system stability checks with electromagnetic-transient simulation. The surrounding fault-current-limiting controls address SM bypass behavior and arm overcurrent, while VR-ACL design remains future work.

  • Iterative design process for selecting Lv: An iterative Lv design process evaluates circulating-current-loop and system stability using Hurwitz, impedance-based, and offline electromagnetic-transient criteria.Offline simulations are especially useful when vendor-supplied white-box or black-box models are available.
  • SM bypass and arm-overcurrent suppression: VAI-FCL adaptively determines the number of bypassed SMs from the severity of MMC SM-capacitor discharge and operates immediately after fault occurrence.The modulator gain remains at its steady-state value, which decreases the MMC AC output voltage.
  • SM bypass and arm-overcurrent suppression: VR-ACL feeds phase current through a virtual resistor into the AC-voltage reference, reducing the voltage difference between the MMC and AC grid during SM bypass.It is activated only when arm current exceeds 1.2 to 1.5 times its peak value and deactivated after DCCB opening is triggered.
  • SM bypass and arm-overcurrent suppression: The VR-ACL design and its impact on AFCL performance are identified as a separate research effort for future work.
  • SM bypass and arm-overcurrent suppression: TB-FCL remains inactive during steady-state operation, but its transient behavior during DC faults must be considered to ensure effective operation.Its design must account for the MMC transient response during a fault.
  • SM bypass and arm-overcurrent suppression: TB-FCL uses a fixed bypass amount determined by Kd; in this paper, Kd = 1 completely bypasses all SMs for the fastest DC-fault-current decay.Bypassing more SMs than VAI-FCL can further increase arm current, so TB-FCL is more suitable as backup protection.

2) Imax:

The validation uses PSCAD models of a bipolar six-terminal radial MTDC system with HB-MMCs, including a fault near a sending terminal. The AFCL design uses specified parameters and minimizes TB-FCL duration because bypassing all submodules removes VR-ACL arm-overcurrent suppression.

  • Imax: TB-FCL duration is determined by Imin and Imax and should be as short as possible because bypassing all submodules removes VR-ACL arm-overcurrent suppression.Under strong-grid conditions, TB-FCL produces more severe arm overcurrent than VAI-FCL.
  • Simulation Description: The study validates AFCL using a bipolar six-terminal radial MTDC system modeled with HB-MMCs and detailed EMT cable and line models.The radial system includes wind-integrating sending terminals and receiving stations connected by links ranging from 75 to 225 km.
  • Simulation Description: The radial topology can propagate a fault transient to multiple sending-end MMC stations because those stations are interconnected by short transmission lines.This makes fault-location proximity and interstation coupling important for the validation scenario.
  • Simulation Description: The six-terminal radial system applies a permanent positive-pole-to-ground fault on link 13 for validation.C-1, C-3, and C-5 represent wind-power sending stations, while C-2, C-4, and C-6 are receiving stations.
  • Simulation Description: The study specifies AFCL and system parameters in Tables I and II for the radial-system simulation.The cited passages identify the parameter tables but do not report their individual numerical entries.

2) Simulated Responses:

In the radial fault simulation, AFCL keeps MMC DC currents below the blocking threshold and supports recovery after DCCB interruption. VAI-FCL delays current rise, TB-FCL limits the peak, and VR-ACL prevents strong-grid arm overcurrent from causing blocking.

  • DC Responses: All six MMC DC currents remain below the 3.81 kA blocking threshold and recover to steady state within approximately 150–200 ms.The actual peak slightly exceeds 3.6 kA because of PWM and control delay, so Imax requires a margin below the blocking threshold.
  • DC Responses: iC1P takes 1.14 ms to reach 3.6 kA with VAI-FCL, whereas without VAI-FCL it would reach the 3.8 kA blocking threshold within tens of microseconds.TB-FCL activates when the upper hysteresis threshold is reached and bypasses submodules to limit the fault current peak.
  • DC Responses: After DCCB opening, LC-induced current oscillations can retrigger TB-FCL in C-1, while C-3 remains below 3.6 kA and avoids reactivation.The simulated strategy also suppresses DC current after fault clearance.
  • Arm Currents: The radial validation compares arm-current responses of C-4’s upper MMC with and without VR-ACL under a deliberately strong-grid condition.C-1, C-3, and C-5 are connected to weak wind-plant grids, whereas C-4 is modeled behind an ideal voltage source.
  • Arm Currents: With VR-ACL enabled, C-4 arm current stays far below the 2 pu valve-overcurrent blocking threshold; without it, the MMC can block despite DC-current limiting.VR-ACL activates approximately 5 ms after the fault when the maximum arm current exceeds 1.2 pu.

C. Case 2: Four-Terminal Meshed HVDC Grid

The second case validates AFCL in a four-terminal meshed HVDC grid, where parallel fault-current paths make limiting more challenging. All MMC currents remain below blocking thresholds, with 50 mH CLRs and mixed use of VAI-FCL and TB-FCL.

  • Case 2: Four-Terminal Meshed HVDC Grid: Meshed HVDC grids create multiple parallel fault-current paths, producing more complex distributions and higher currents than radial systems.These characteristics pose greater challenges for AFCL effectiveness.
  • Simulation Description: The series CLR is rated at 50 mH, substantially below values commonly reported for existing AFCL methods.The grid includes links of 100, 150, and 200 km.
  • Simulated Responses: All four MMC DC currents remain below the blocking threshold during the fault, demonstrating non-blocking fault ride-through in the meshed grid.C-1 and C-3 are limited to approximately 3.6 kA by TB-FCL, while C-2 and C-4 use VAI-FCL alone.
  • Conclusion: Across the two representative MTDC configurations, simulations validate non-blocking HB-MMC fault ride-through with smaller series CLRs than those reported in existing literature.This conclusion covers both the radial and meshed case studies.
Loading 2609.00286v1…