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VARA: A Voltage-Aware ReRAM-Based Accelerator for Energy-Efficient Computing

Peng Dang, Yintao He, Huawei Li

arXiv:2609.00421v1cs.AR

TL;DR

Existing ReRAM accelerators largely optimize weights while giving limited attention to activation distributions, despite activation voltages affecting crossbar and ADC energy. VARA combines threshold-based voltage-aware training with co-zero activation reordering to create skip-friendly zero regions. Across its evaluation, VARA reports 60.12% lower average total system energy and 2.68× higher average system energy efficiency than the baseline, with marginal accuracy loss.

  • Problem

    Existing ReRAM accelerators primarily optimize weights while paying limited attention to activation distributions, although activations influence computational energy consumption.

  • Method

    VARA combines voltage-aware training, which thresholds low-magnitude activations toward zero, with co-zero activation reordering of activations and corresponding weights.

  • Results

    60.12% average total system energy consumption reduction and 2.68× average system energy-efficiency improvement are reported relative to the baseline, with approximately 0.71% average accuracy loss.

  • Takeaways & Limitations

    VARA transforms element-wise activation sparsity into structured redundancy that can be exploited for crossbar-level computation skipping.

Abstract

from arXiv · show

ReRAM-based in-memory computing (IMC) architectures are widely regarded as a promising approach to alleviating the computational bottleneck of conventional architectures. Since ReRAM crossbars perform matrix-vector multiplication (MVM) in the analog domain, their computational energy consumption is highly dependent on weight and activation distributions. However, most existing ReRAM accelerators focus primarily on weight optimization while paying limited attention to the impact of activations on computational energy consumption, leaving the energy-saving potential of activation sparsity largely underexploited. In this paper, we propose a voltage-aware ReRAM-based accelerator (VARA), along with its accompanying design methodology. Specifically, we first introduce a voltage-aware training (VAT) algorithm that incorporates a preset threshold into the activation function to steer the activation distribution toward zero values, thereby enhancing activation sparsity. Building upon this, we further propose a co-zero activation reordering (CAR) scheme for crossbar-level computation skipping. CAR clusters activation dimensions based on their co-zero correlations and consistently reorders both the activation matrix and its corresponding weights. This process consolidates scattered zero activations into contiguous zero-valued regions to maximize the benefits of crossbar-level computation skipping. Extensive experimental results demonstrate that, with only marginal accuracy loss, VARA reduces the average total system energy consumption by 60.12\% and improves the average system energy efficiency by 2.68$\times$ compared to the baseline, outperforming existing state-of-the-art accelerators for sparse-activation optimization.

1 Introduction

ReRAM-based IMC can reduce DNN computation overhead by performing MVM directly in crossbars, but existing accelerators primarily optimize weights while underusing activation sparsity for energy reduction. VARA addresses this gap through voltage-aware training and co-zero activation reordering, achieving substantial system-level energy savings with marginal accuracy loss.

  • Motivation: ReRAM-based IMC integrates storage and computation, enabling analog MVM directly within crossbar arrays for resource-constrained DNN deployment.The motivation is reducing computational and storage overhead as DNN models grow in size and complexity.
  • Research gap: Existing approaches mainly optimize weight distributions and encoding schemes, while giving limited attention to activation distributions and their impact on system energy.This leaves the energy-saving potential of activation sparsity insufficiently addressed.
  • Motivation: Activation distributions affect crossbar and ADC power because activations are encoded as input voltages that determine bitline currents.All-one activations produce maximum current and power, whereas all-zero activations produce zero current and no effective MAC operations.
  • Proposed approach: VARA co-optimizes model training and deployment through VAT and CAR to exploit activation sparsity for energy-efficient ReRAM computation.VAT increases zero activations, while CAR reorganizes activations and weights to support crossbar-level skipping.
  • Results: 60.12% average total system energy reduction and 2.68× average system energy-efficiency improvement are reported relative to the baseline, with only marginal accuracy loss.The evaluation covers multiple networks and datasets.

2 Background and Motivation

ReRAM crossbar energy depends on activation voltages, conductances, and resulting bitline currents, making activation sparsity relevant to both crossbar and ADC consumption. VARA combines threshold-based activation regulation with co-zero dimension reordering so element-wise zeros become structured regions suitable for computation skipping.

  • ReRAM computation: ReRAM accelerators map weights to cell conductances and activations to wordline voltages, with currents accumulated on bitlines and digitized by ADCs.Complete MVM tasks are partitioned across multiple crossbars because of physical and peripheral limitations.
  • Activation-dependent power: Zero activations set corresponding wordline voltages to zero, eliminating associated memory-cell dynamic power and reducing crossbar dynamic energy.This creates a direct hardware-level benefit from increasing activation sparsity.
  • Activation-dependent power: ADC dynamic power is proportional to the square of bitline current for fixed hardware parameters, so activation optimization can reduce peripheral energy substantially.Bitline current is jointly determined by input voltages and weight conductances.
  • Computation skipping: Crossbar-level skipping is possible when an input vector is entirely zero, allowing the system to predict a zero output before performing computation.Hardware-aware training can help unlock this optimization opportunity.
  • VAT: VAT modifies activation thresholds to drive low-magnitude activations toward zero, increasing zero activation ratio and establishing sparsity for computation skipping.The approach uses threshold-adjusted activation functions such as VA-Step and VA-ReLU.
  • CAR: CAR reorders activation dimensions and corresponding weight mappings using co-zero correlations, consolidating scattered zeros into contiguous all-zero regions.This increases the probability of all-zero input vectors and crossbar-level skipping, unlike independent zero-rate sorting.

3 Methodology

VARA combines voltage-aware training with co-zero activation reordering to increase activation sparsity and convert it into crossbar-level computation skipping.

  • 3 Methodology: VARA integrates VAT and CAR into a pipeline spanning activation-sparsity optimization, hardware deployment, and computation skipping.VAT adjusts the activation threshold, while CAR uses offline reordering and online execution.
  • 3.2 Voltage-Aware Training: VAT introduces adjustable thresholds into Step and ReLU activations to map more low-magnitude outputs to zero.VA-Step shifts the binarization boundary to θ, while VA-ReLU extends the zero-output region to (−∞, θ].
  • 3.2.1 Voltage-Aware Training Algorithm for Step Functions: As θ increases, VA-Step produces a progressively larger proportion of zero-valued activation outputs.The threshold controls the ratio of activations mapped to 0 versus +1.
  • 3.2 Voltage-Aware Training: VAT uses a Sigmoid-based straight-through estimator to provide smooth, nonzero gradients near the threshold during training.For VA-ReLU, gradients propagate only when pre-activation exceeds θ, with the derivative set to 0 at the boundary.
  • 3.3 Clustering-Based Co-Zero Activation Reordering: CAR reorders activation dimensions and corresponding weights using a co-zero-based permutation, preserving computation while concentrating zeros into contiguous regions.The permutation is constructed in crossbar-capacity-sized blocks, selecting dimensions by zero rate and composite co-zero score.
  • 3.3 Clustering-Based Co-Zero Activation Reordering: CAR enables coarse-grained crossbar skipping by retaining only needed crossbars, eliminating redundant transfers, computations, and data conversions during inference.The reordered mapping increases the probability that crossbar input vectors are all zero while maintaining computational equivalence.

4.1 Experimental Setup

The experiments evaluate three quantized networks across three image-classification datasets and use customized ReRAM simulation to assess VARA hardware performance.

  • Experimental Setup: VGG11, ResNet18, and ResNet34 are trained and evaluated on CIFAR10, CIFAR100, and Tiny ImageNet, respectively.Training uses PyTorch, SGD with momentum, cosine annealing, 8-bit weight quantization, and VA-Step or VA-ReLU activations.
  • Hardware Setup: A customized simulator evaluates VARA using an Ag:Si ReRAM device model at the 22 nm technology node.The simulator is based on open-source simulators.
  • Experimental Setup: The study reports training hyperparameters and hardware simulation parameters in Tables 1 and 2.The supplied passages identify the tables but do not provide their parameter entries.
  • Hardware Setup: The sparse VAT-trained model serves as the deployment baseline before CAR reorders activation dimensions and corresponding weights for crossbar-level skipping.Matrix partitioning and mapping then follow crossbar size constraints.

4.2 Impact of VAT on Model Accuracy and Activation Sparsity

VAT increases activation sparsity through threshold selection while exposing different accuracy–sparsity trade-offs for VA-Step and VA-ReLU. Across six experiments, the selected thresholds achieve high average ZAR with limited average accuracy loss.

  • VA-Step: VA-Step reaches ZARs of 90.89%, 84.96%, and 88.73% for VGG11, ResNet18, and ResNet34 while improving baseline accuracy by 0.16%, 0.20%, and 0.47%.The selected thresholds are 0.9, 0.7, and 0.8, respectively.
  • VA-Step: For VA-Step, ZAR rises with threshold while accuracy generally peaks near θ=0.3 before declining at higher thresholds.Moderate suppression of low-magnitude activations is described as producing a regularization effect.
  • VA-ReLU: For VA-ReLU, ZAR also rises with threshold, but accuracy generally declines for VGG11 and ResNet18 and improves only marginally at θ=0.1 for ResNet34.The selected thresholds are 0.8, 0.7, and 0.5, respectively.
  • VA-ReLU: VA-ReLU reaches ZARs of 92.58%, 81.66%, and 82.53% while dropping baseline accuracy by approximately 1.24%, 2.39%, and 1.46%.Accuracy is more sensitive to threshold variation because sub-threshold activations, including informative ones, are truncated.
  • Overall Trade-off: 86.89% average ZAR is achieved across six experiments while average accuracy loss is limited to approximately 0.71%.The selected thresholds balance accuracy and sparsity rather than simply maximizing accuracy.

4.3 Evaluation of Structured Reshaping Effects on Activation Distributions

VAT creates zero clusters, while CAR reorders activation dimensions to consolidate them into contiguous all-zero regions. This substantially preserves crossbar-skipping opportunities as crossbar size grows.

  • Activation Reshaping: VAT maps many low-magnitude activations to zero and forms noticeable zero clusters, but nonzero activations remain scattered across input dimensions.This dispersion leaves many partitions with a small number of nonzero elements.
  • Metric Definition: The crossbar-level computation skipping ratio is the fraction of all-zero input vectors among all input vectors.Each all-zero input vector corresponds to one skippable crossbar computation.
  • Crossbar-Size Sensitivity: Without CAR, skipping ratios decrease rapidly as crossbar size grows from 16×16 to 256×256 despite VAT’s high ZAR.For VA-Step, VGG11 and ResNet18 approach zero at larger crossbar sizes.
  • CAR and Crossbar Skipping: CAR raises 256×256 crossbar-skipping ratios to approximately 38.4%, 29.0%, and 42.1% for VA-Step and 50.5%, 32.7%, and 33.3% for VA-ReLU.These values correspond to VGG11, ResNet18, and ResNet34, respectively.
  • Hardware Configuration: A 64×64 crossbar is adopted as the default configuration because it provides moderate partitioning granularity while retaining considerable skipping ratios.This choice follows the crossbar-size sensitivity analysis.

4.4 Circuit-Level Hardware Performance Evaluation of the VARA Architecture with VAT Only

VAT reduces circuit-level energy consumption by increasing zero input voltages, with VA-Step producing stronger savings than VA-ReLU. The reductions affect both ReRAM crossbars and ADCs.

  • VA-Step: VA-Step reduces crossbar energy by approximately 77.25%, 74.18%, and 75.76% and ADC energy by 67.71%, 65.30%, and 66.95% for VGG11, ResNet18, and ResNet34.These reductions are relative to the baseline at the optimal threshold.
  • VA-Step: Increasing the VA-Step threshold substantially reduces both crossbar and ADC energy consumption across all three models.The discrete {0, +1} output increases zero input voltages and lowers effective cell conduction and bitline current.
  • VA-ReLU: VA-ReLU reduces crossbar energy by approximately 69.52%, 50.79%, and 44.20% and ADC energy by 51.97%, 37.05%, and 30.45% for VGG11, ResNet18, and ResNet34.Its overall reductions are less pronounced than VA-Step’s.
  • Overall Energy Results: 65.28% average crossbar-energy reduction and 53.24% average ADC-energy reduction are achieved across six experiments.The reductions are attributed to increased zero input voltages that suppress ReRAM conduction and bitline currents.

4.5 System-Level Performance Evaluation of the VARA Architecture under Synergistic VAT and CAR Optimization

VARA combines VAT and CAR to reduce activation-driven energy use and enable crossbar-level computation skipping. Across six configurations, this synergy substantially lowers system energy consumption and improves energy efficiency.

  • VA-Step: 73.16%, 62.80%, and 69.57% energy reductions are achieved for VGG11, ResNet18, and ResNet34 with VA-Step, respectively.The corresponding energy efficiencies improve to approximately 3.73×, 2.69×, and 3.29× relative to baseline settings.
  • Mechanism: Increasing the threshold maps more low-magnitude activations to zero, reducing voltage activity and bitline current while creating more CAR computation-skipping opportunities.CAR groups dimensions with strong co-zero correlations so more crossbars receive all-zero inputs and can skip computation.
  • VA-ReLU: 63.68%, 47.08%, and 44.39% energy reductions are achieved for VGG11, ResNet18, and ResNet34 with VA-ReLU, respectively.Energy consumption decreases and efficiency improves as the threshold rises, with optimal thresholds producing the reported reductions.
  • 60.12% average total system energy reduction and 2.68× average energy-efficiency improvement are achieved across six VAT-and-CAR configurations.These results reflect the synergistic optimization of activation sparsity enhancement, structured reordering, and hardware computation skipping.

4.6 System-Level Energy Breakdown of the VARA Architecture

VARA’s system energy is dominated by ADCs and data movement rather than the indexing hardware added for CAR. VA-ReLU shifts more energy toward buffers and accumulation because it retains multi-bit continuous activations.

  • Evaluation setup: The energy breakdown is evaluated on ResNet34 under VA-Step and VA-ReLU to assess overhead from the IU supporting CAR.Figure 12 reports the energy shares of individual system modules for both configurations.
  • VA-Step: 61.5% of VA-Step energy is consumed by ADCs and 19.0% by buffers, while the IU contributes only 0.22%.ADCs and buffers together account for 80.5% of total energy, whereas the crossbar contributes 1.46%.
  • VA-ReLU: 51.8% of VA-ReLU energy is consumed by ADCs, with buffers and accumulation contributing 25.2% and 12.0%, respectively.Retaining multi-bit continuous activation values enlarges storage and transfer bit-width, increasing partial-sum data-movement overhead.
  • Indexing overhead: The IU energy share remains below 0.3% because it stores layer permutation indices rather than full activation matrices.Its storage depends on activation row dimension and the permutation sequence is read once before computation.

4.7 Related Work and Comparison

VARA differs from prior ReRAM sparsity schemes by jointly increasing activation zeros, structurally reordering them, and skipping computation at crossbar granularity. Comparisons report stronger system-level savings than representative alternatives.

  • Prior sparsity schemes: Prior schemes exploit value sparsity, bit sparsity, matrix reordering, or runtime skipping at different optimization stages and hardware granularities.Bit-level methods cannot readily create all-zero regions, while row/column compression does not actively increase zero-valued elements or provide global structured reordering.
  • Conductance-versus-voltage modulation: 76.05% crossbar-energy and 66.98% ADC-energy reductions are achieved by VARA with VA-Step in the cited comparison against SARA.SARA instead reduces current by mapping more weights to high-resistance states.
  • Conductance-versus-voltage modulation: VAT maps more activations to zero input voltage, while SARA maps more weights to high-resistance states to reduce bitline current.For nonzero input voltage, a high-resistance cell still produces finite read current, whereas zero voltage can eliminate the corresponding current.
  • Activation-sparsity comparison: 60.12% system-energy reduction exceeds RapPIM’s 44.82% reduction by 15.30 percentage points.VARA also reports 0.71% average accuracy loss and 2.68× energy-efficiency improvement across more complex datasets.
  • Activation-sparsity comparison: RapPIM prunes low-impact activation rows or columns at runtime, whereas VARA increases the zero ratio and structurally reorders activations for crossbar-level skipping.The comparison distinguishes row/column pruning from structured all-zero regions aligned with crossbar computation.

5 Conclusion

VARA exploits activation sparsity through voltage-aware training and co-zero reordering, converting scattered zeros into hardware-skippable regions. The resulting accelerator reduces energy consumption while improving energy efficiency with marginal accuracy degradation.

  • Contribution: VAT suppresses low-magnitude activations, while CAR reorders activations and corresponding weights to aggregate scattered zeros into contiguous all-zero regions.These regions enable crossbar computations corresponding to all-zero inputs to be skipped.
  • Conclusion: 60.12% average total system-energy reduction and 2.68× average energy-efficiency improvement are reported with marginal model-accuracy degradation.The reported results are compared to the baseline.
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