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FALCON: Fault-Tolerant Magnetic Tunnel Junction-Based In-Memory Stochastic Architecture for Reliability-Critical Edge AI Applications
Farzad Razi, Mehran Moghadam, Sercan Aygun, M. Hassan Najafi, Marc Riedel
TL;DR
FALCON addresses the reliability and energy costs of conventional in-memory computing under data-movement overhead, process variation, voltage scaling, and device noise. It combines deterministic stochastic bit-stream generation with reconfigurable MTJ-based in-memory arithmetic, maintaining correct operation under noise injection up to 30% and demonstrating 7.63 µJ energy cost for a 256 × 256 morphological closing.
Problem
Conventional von Neumann and binary in-memory architectures face high data-movement overhead and reduced robustness under process variation, voltage fluctuations, and device noise.
Method
FALCON integrates deterministic MTJ-based stochastic bit-stream generation, stochastic-computing arithmetic, and reconfigurable logic-in-memory structures directly within memory arrays.
Results
FALCON maintains correct functionality under process variation, aggressive voltage scaling, and noise injection up to 30%, while a 256 × 256 morphological closing costs 7.63 µJ in situ.
Takeaways & Limitations
The results support FALCON as a reliability-enhanced, energy-efficient in-memory framework for reliability-critical edge AI applications.
Abstract
from arXiv · showhide
As modern data-centric applications such as neural inference and sensor-edge analytics expand, they increasingly encounter the von Neumann memory wall, suffering from excessive data movement overhead and stringent energy constraints. In-Memory Computing (IMC) utilizing emerging non-volatile technologies, such as Magnetic Tunnel Junctions (MTJs), promises to mitigate these bottlenecks. However, conventional binary radix-based IMC architectures suffer from excessive vulnerability to process-induced variations, restricted operating margins, and thermal noise. To bridge the gap between energy efficiency and computational reliability, this work proposes FALCON, a fault-tolerant, MTJ-based in-memory arithmetic architecture integrated with Stochastic Computing (SC). By encoding numerical values into uniform bit-streams, SC naturally absorbs localized soft errors and enables the execution of an essential suite of arithmetic operations using highly compact logic primitives directly within the memory arrays. FALCON integrates a deterministic bit mapping mechanism with reconfigurable logic-in-memory (LIM) structures, eliminating the need to transfer data to external processors or area- and power-hungry random number generators. Experimental results using 14 nm FinFET technology validate the correct functionality of FALCON even under aggressive voltage scaling, severe process variation, and noise injection levels up to 30%, making it a robust framework for reliability-critical edge AI applications. We investigate the proper functionality of FALCON on morphological closing as a realistic noise-tolerant image processing case study.
I. INTRODUCTION AND MOTIVATION
Reliability-critical edge applications face data-movement overhead and hardware nonidealities, motivating in-memory approaches that reduce transfers and improve computational robustness. FALCON addresses this need with a fault-tolerant MTJ-based stochastic IMC architecture using deterministic bit streams and in-memory arithmetic.
- Motivation: Modern edge and data-centric workloads require reliable, energy-efficient computation under noise, voltage fluctuations, and fabrication variation.Conventional von Neumann processors also incur high data-movement overhead.
- Motivation: IMC reduces data movement by embedding computation in or near memory, but MTJ-based designs remain vulnerable to process variation, limited margins, and thermal noise.These nonidealities can threaten computational correctness.
- FALCON proposal: FALCON proposes a fault-tolerant MTJ-based stochastic IMC framework supporting essential arithmetic operations comparable to a general-purpose processor’s ALU.The architecture is described as energy-efficient, lightweight, and resilient to faults and device nonidealities.
- FALCON proposal: FALCON integrates deterministic bit-stream generation, reconfigurable in-memory arithmetic, and bit-stream-to-binary conversion without external data transfer.Its contributions include multiplication, scaled addition, division, absolute subtraction, minimum, and maximum operations within memory.
II. FALCON ARCHITECTURE
FALCON embeds deterministic stochastic encoding, reconfigurable logic-in-memory computation, and decoding within MTJ memory arrays. Its arithmetic operations use compact logic primitives whose bit-stream averaging limits the numerical effect of individual errors.
- Architecture overview: FALCON combines deterministic bit-stream generation, SC arithmetic, and bit-stream-to-binary conversion entirely within MTJ-based memory arrays.The three layers form a lightweight stochastic engine without external logic transfers.
- Bit-stream generation: Deterministic low-discrepancy mapping replicates each binary bit X_i 2^i times at predefined positions in a 2^n-length stream.The mapping produces exact stochastic representations and controls inter-stream cross-correlation without random-number generators.
- Logic-in-memory computation: The LIM structure uses two MTJs and peripheral FinFETs to reconfigure AND, OR, XOR, and MUX primitives for stochastic arithmetic.Inputs are stochastic bit streams applied directly to the memory-array logic.
- Arithmetic operations: Multiplication uses AND, minimum and maximum use AND and OR on correlated streams, absolute subtraction uses XOR, and scaled operations use a 2:1 MUX.These operations are implemented through simple logic on equally weighted streams.
- Fault resilience: Individual noise- or timing-induced bit errors have negligible numerical impact because results are averaged across the full bit-stream length.Outputs can be reused for subsequent stochastic operations or converted back to binary in memory.
A. Performance Evaluations
FALCON’s simulations evaluate soft-error tolerance, circuit-level operation, process variation, and voltage scaling. Across these conditions, the architecture preserves arithmetic functionality, while longer streams improve accuracy and noise tolerance and lower voltage reduces power.
- Soft-error robustness: Increasing stochastic bit-stream length monotonically improves computation accuracy and noise tolerance across arithmetic operations under injected soft errors.Shorter streams suit latency-sensitive tasks, whereas longer streams provide higher noise margins.
- Circuit validation: 14 nm FinFET HSPICE simulations validate the expected two-phase LIM timing behavior for representative arithmetic operations.Inputs are programmed during preparation and sensed through resistance during evaluation.
- Process variation: Under ±3σ Monte Carlo variation with 10% parameter variation across FinFET and MTJ characteristics, every arithmetic operation remains functionally correct.Preparation delay, evaluation delay, and total power show measurable spread, but computational integrity is maintained.
- Voltage scaling: All operations remain accurate at 0.9 V, 0.8 V, and 0.7 V, while power consumption falls approximately 27% at 0.8 V and 51% at 0.7 V.Voltage-induced perturbations affect individual bits while preserving the stream’s statistical representation.
B. Case Study: Morphological Image Closing
FALCON applies its in-memory stochastic architecture to grayscale and binary morphological closing, maintaining robust behavior under severe device noise while reducing execution energy.
- Case Study: Morphological Image Closing: FALCON performs grayscale morphological closing entirely in memory using dilation followed by erosion on image data.The case study evaluates local maximum and minimum operations without transferring pixel arrays to an external processor.
- Noise Robustness: 10% to 30% noise injection leaves FALCON’s stochastic closing largely stable, whereas conventional binary closing collapses rapidly.The comparison uses a 3 × 3 grayscale closing on a sample image.
- Noise Robustness: At 30% device noise, conventional binary execution reaches an IoU of only 0.64 with the ideal mask, while FALCON recovers a clean, connected silhouette.The binary silhouette begins with 15% salt-and-pepper noise and undergoes 3×3 closing.
- System-Level Behavior: FALCON’s bit mapping and logic-in-memory execution maintain robust, accurate system-level behavior under extreme device-level variations.The architecture uses reconfigurable logic-in-memory structures for bit-wise OR and AND operations in the closing pipeline.
- Energy: 7.63 µJ is required for a 256 × 256 morphological closing executed in situ, yielding roughly 10× energy savings versus standard sliding-window von Neumann execution.The estimate is based on circuit-level extractions and eliminates off-chip data movement.
IV. COMPARISON WITH STATE OF THE ART
FALCON is compared with binary and stochastic in-memory architectures through its deterministic MTJ-based bit mapping and reconfigurable in-memory arithmetic. The comparison emphasizes its combination of arithmetic flexibility, intrinsic robustness, and reduced peripheral overhead.
- Binary IMC Architectures: Binary IMC architectures provide flexible bit-serial SIMD arithmetic but remain vulnerable to reliability limitations in emerging-device implementations.The comparison discusses DRAM-based designs including Ambit, ReDRAM, and SIMDRAM.
- SC-IMC Architectures: SC-IMC frameworks embed stochastic generation and arithmetic to improve fault tolerance, but ReRAM-based approaches retain random-operand, endurance, and energy challenges.The cited comparison includes SCRIMP, SC-CRAM, Stoch-IMC, and All-in-Memory SC on ReRAM.
- FALCON: FALCON uses deterministic MTJ read/write operations to control inter-stream cross-correlation without area-intensive random-number-generator circuitry or switching-probability calibration.This approach also avoids ReRAM endurance limitations and complex global accumulation networks.
- FALCON: FALCON executes division, absolute subtraction, and minimum/maximum operations entirely in situ at the microwatt scale.The comparison characterizes FALCON as trading some throughput for intrinsic robustness relative to binary IMC designs.
V. CONCLUSION
The paper presents FALCON as a fault-tolerant MTJ-based stochastic in-memory architecture combining deterministic bit-stream generation with reconfigurable logic-in-memory computation. Simulations and a morphological closing case study demonstrate reliable operation under device nonidealities and energy savings for reliability-critical edge AI.
- Conclusion: FALCON integrates deterministic stochastic bit-stream generation with reconfigurable logic-in-memory computation for fault-tolerant MTJ-based in-memory arithmetic.The architecture executes essential arithmetic operations inside memory arrays while minimizing data movement and peripheral overhead.
- Conclusion: Simulation results demonstrate reliable operation under substantial soft-error injection, process variation, and aggressive voltage scaling.
- Conclusion: A morphological image-closing case study confirms robust system-level behavior and significant energy savings for energy-constrained, reliability-critical edge-AI applications.