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Analog-DB: An Agent-First Analog Integrated Circuit Database, From Blocks to Systems

Danial Noori Zadeh, Mohamed B. Elamien

arXiv:2609.01286v1cs.AIcs.AReess.SP

TL;DR

Analog IC sharing lacks both releasable process-independent artifacts and the testbenches and structural information needed for reproducible reuse. Analog-db addresses this with a versioned, schema-governed database of process-neutral designs, bindings, contracts, and agent-queryable artifacts. Its corpus demonstrates kit-bound specification compliance, sizing-loop closure, and supervised agent use, while the evidence remains limited to small, supervised case studies and bounded annotation coverage.

  • Problem

    Foundry agreements restrict process-dependent artifacts, while published analog results rarely include the testbenches and structural information needed to reproduce or reuse them.

  • Method

    Analog-db packages process-neutral topologies, parameter spaces, behavioral contracts, reusable analyses, and per-process bindings in a schema-governed, queryable database.

  • Results

    68 circuits across sixteen classes are released, with tiered schematic-level verification; supervised agent studies reached datasheet compliance and found four hand-entry defects plus a missing common-mode feedback loop.

  • Takeaways & Limitations

    The representation makes released analog design knowledge re-runnable, re-sizeable, extendable, and usable by later designers or agents within the demonstrated scope.

  • Takeaways & Limitations

    Agent evidence consists of two author-supervised sessions using one coding agent and model, without a structural-artifact-denied comparison; annotation coverage is limited by the template library.

Abstract

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Sharing analog integrated circuit designs remains difficult: foundry non-disclosure agreements restrict the process details a design depends on, and the testbenches behind published results are rarely released. We present analog-db, an open-source, versioned database built on a shareable design representation. A domain-specific language captures each design as a process-neutral topology, reusable testbenches, and a machine-readable datasheet under one schema, so a design is shared in full and re-simulates on the process kits it is bound to. A parameterization scheme exposes functional sub-blocks and device sizes as named parameters that carry their matching constraints, making circuits composable and retargetable; a schema-governed contract and queryable catalog let AI design agents discover and reuse them directly. Across the regulator corpus, all 23 circuit-kit bindings on three open kits meet their own recorded specification bands (typical corner, matched devices, no layout) and 10 of 23 meet a common class band. Seventeen of the 23 imported sizings failed their testbenches and closed under a gm/ID sizing loop driven by the annotated sub-block roles, typically within one to three iterations. In a supervised case study, a coding agent working from the released artifacts sized the op-amp cores of a chopper instrumentation amplifier on an open 130nm kit, locating four hand-entry defects and a missing common-mode feedback loop that the sizing-only baseline did not repair. The database holds 68 circuits across sixteen classes, verifiable at schematic level under a tiered harness and tracked on a power/performance scoreboard, released at https://github.com/MacAnalog/spicexplorer-release.

A domain-specific language

Analog-db addresses representational, contractual, and machine-actionability barriers by packaging process-neutral circuit structure, reusable verification, and recorded acceptance criteria in a queryable corpus.

  • Motivation: Analog designs are difficult to share because netlists omit functional intent, analog verification procedures are rarely recorded, and foundry agreements restrict process-dependent artifacts.These barriers leave readers with performance figures without the complete structure or measurement procedure needed for reproduction and reuse.
  • Motivation: Open PDKs remove foundry entitlement requirements but do not describe circuit organization or the testbench that produced reported results.They provide a process against which designs can be simulated, while the representation layer remains absent.
  • A domain-specific language: A schema-governed catalog lets AI agents query entries and retrieve topology, datasheet, analyses, and parameters for simulation through the SpiceXplorer harness.The interface is intended to remain readable to human designers while supporting machine discovery and reuse.
  • A domain-specific language: The database captures each design as a process-neutral topology, reusable testbench, and machine-readable datasheet under one schema.This separates shareable design information from encumbered process details while preserving direct simulation through bound kits.
  • A domain-specific language: Functional sub-block annotations and named device parameters carrying matching constraints make circuits composable and retargetable.The released corpus contains 68 verifiable circuits across sixteen classes, including 65 with recorded design points.
  • Related work: Related released efforts provide subsets of reuse infrastructure, but the comparison identifies missing combinations of designs, testbenches, acceptance bands, hierarchy, and machine-readable contracts.AnalogGym, for example, supplies shared testbenches for some categories but lacks several reuse-oriented capabilities.

III. METHOD

The method defines a schema-governed analog design entry, exposes its requirements for reuse and machine actionability, and mechanically lowers bindings into verifiable process-specific simulation artifacts.

  • III. METHOD: The representation requirements are foundry neutrality, reproducibility, structural transparency, composability, and machine actionability.These requirements connect process-neutral release and carried-along verification to reuse across design hierarchies and software agents.
  • Sub-block detection: Sub-block detection labels a flattened design graph and searches for label-preserving matches against a functional template library.Supply-rail and private-net constraints validate matches, after which covered devices receive structural roles and annotated hierarchical views are rendered.
  • Formal model: Each released entry contains a process-neutral topology T, parameter space Θ, behavioral contract C, and per-process bindings B.Bindings supply kit-device mappings, concrete sizing values with search bounds, and corner selections.
  • Artifact generation: Lowering maps an entry’s analyses and bindings into ready-to-run SPICE decks, one per bound kit and analysis.Retargeting keeps the topology, parameters, and contract fixed while remapping devices and corners and clamping sizes to target geometry rules.
  • Verification artifacts: Design points record concrete kit-specific simulation outcomes with measured metrics and pass/fail verdicts, while validated design points pass every spec-bounded metric.Accession identifiers provide stable, append-only names, and derived artifacts are mechanically regenerated and checked for drift.

2) Separating Topology from Process:

Analog-db separates process-neutral circuit structure from process-specific bindings, while encoding reusable testbenches, datasheet contracts, and explicit parameter-matching constraints. This makes designs shareable, retargetable, and mechanically verifiable across supported kits.

  • Process-neutral representation: The abstract netlist uses generic device tokens and named geometry symbols, while per-kit bindings supply foundry-specific devices, corners, and geometry rules.Readers with a bound kit can lower the topology into a simulable circuit; others can still read, cite, and retarget it.
  • Functional structure: Labeled subgraph matching recovers functional organization from flattened graphs and generates annotated schematic and hierarchical views.Detected roles make implicit structures such as functional blocks explicit in the released record.
  • Scope boundary: The template library is device-level and does not include a common-mode-feedback family at the archived revision.Common-mode feedback is represented through released entries rather than recognized as an inline template structure.
  • Parameterization: Parameterization combines one symbolic variable per geometry field with tie groups and ratio declarations that preserve matching and designed current relationships.Per-kit bindings assign defaults and search bands to the remaining free representatives.
  • Verification contract: Each reported metric is linked to an analysis, waveform extraction, and specification band, making the measurement procedure part of the design contract.Declared corners are evaluated through class-owned testbench templates and canonical metric definitions.

5) Hierarchical Composition:

Hierarchical composition builds systems from version-pinned database entries, then lowers composites into the same netlists, bindings, datasheets, and verification flow as leaf circuits. The catalog and file contract support agent discovery and reuse without requiring a service.

  • Hierarchical Composition: A composition manifest names each child block, pins its topology revision by content hash, and wires its ports into a composite circuit.Child per-kit sizings provide geometry, while the composite may expose internal nets or replace child-local bias elements.
  • Hierarchical Composition: Generation flattens a manifest into an ordinary netlist and sizing binding, keeping composition closed over database entries.The resulting composite has the same entry form as a leaf circuit.
  • Hierarchical Composition: A composite binds only kits shared by every child, and unavailable child bindings remain unavailable until that child gains the binding.The composite carries its own datasheet and passes through the same lowering and verification process.
  • Agent interface: The file contract and generated catalog let agents discover entries, compare recorded design points, reuse or resize candidates, and record new scoreboard outcomes without credentials or a running server.Each loop pass leaves a new design point for later comparison, while a protocol wrapper is deferred as future work.
  • Artifact Generation and Verification: T0–T4 verification progresses from schema validity and reproducible artifacts to runnable decks, simulation, and datasheet-band validation.An entry is validated only when every specification-bounded metric passes; schematic graph-isomorphism is checked separately.
  • Hierarchical Composition: Figure 2 illustrates composition with a chopper instrumentation amplifier whose system entry combines two op-amp cores and annotated functional groupings.Detected differential pairs and a diode-referenced mirror coexist with designer annotations for bias, common-mode feedback, and cascode loads.
  • Artifact Generation and Verification: The scoreboard records Pareto fronts over power, area, and class headline metrics rather than naming a single scalar best.Its area measure excludes spacing, routing, wells, capacitors, and resistors, so it ranks device budgets rather than die cost.

IV. EXPERIMENTS

The experiments evaluate analog-db’s coverage, reproducibility, cross-PDK portability, agent-assisted design, and optimization behavior. Results show a populated but unevenly verified corpus, reproducible archived measurements, successful regulator portability under entry-specific contracts, and agent-assisted closure of sizing and implementation failures.

  • Coverage and Provenance (RQ1): 68 verifiable circuits span sixteen classes, with 65 holding recorded design points, 43 validated on at least one kit, and 14 validated on all three.The corpus excludes three incomplete entries and 13 provenance-only reference circuits.
  • Coverage and Provenance (RQ1): Parameterization exposes 3819 generated symbols, including 1333 free symbols after 444 tie groups, 255 ratio-bound symbols, and 365 frozen symbols.Structural role detection covers 807 of 1574 devices, organized into 321 block instances; the remainder is recorded as a template-library limitation.
  • Reproducibility (RQ2): Every benchmark-table value was re-simulated from the archived database, and an independent verifier reproduced all recorded metrics for sixteen regulator baselines bit for bit.These checks apply to the archived revision and typical corner.
  • Cross-PDK Portability (RQ3): 23 regulator circuit-kit bindings pass their own complete datasheets, while 10 of 23 meet the common class-level reference band.The two verdicts distinguish entry-specific contract conformance from performance against a shared class band.
  • Agent Case Studies (RQ4): The supervised agent studies sized bound-kit entries and composed sized op-amp cores into a closed instrumentation-amplifier system, while supervision remained interactive rather than autonomous.The study protocol included author-set objectives, review of diagnoses and edits, and acceptance or rejection against datasheet verdicts.
  • Agent Case Studies (RQ4): 17 of 23 imported regulator sizings failed initially, but the annotated gm/ID loop closed each failure, typically within one to three sizing iterations after mechanism identification.The loop re-simulates the baseline, localizes failures using sub-block roles and targeted probes, re-sizes by role, and re-judges the full datasheet.
  • Agent Case Studies (RQ4): Approximately 0.40 Vpp of zero-input output ripple was reduced below 0.1 µVpp in the composed system.The reported value is a single-corner measurement using an idealized common-mode servo and windowed transient extraction on open kits.
  • Agent Case Studies (RQ4): The hand seed outperformed the best optimizer trial on gain, power, and searched-device gate area: 25.713 vs. 25.611 dB, 263.4 vs. 283.9 µW, and 96.8 vs. 127.2 µm2.The hand seed was not evaluated as an optimizer trial, and the system row represents a later sizing measurement.

E. Scoreboard Coverage and Optimization Support (RQ5)

The scoreboard expands evaluation beyond one released sizing by retaining validated design points and distinguishing points that satisfy entry-specific specifications from those that also meet a common class band. It covers broad amplifier and regulator design spaces while preserving bench conditions and provenance for regeneration.

  • 457 design points populate the archived scoreboard, with 127 of 159 circuit-kit cells carrying at least two alternatives.Per-cell Pareto marking distinguishes real design alternatives, while datasheet-missing sizings remain as search starting points.
  • 39 of 327 recorded amplifier design points are validated, spanning 0.6 µW to 7.7 mW, 40–160 dB DC gain, and 33 kHz–528 MHz unity-gain frequency.The validated points span more than four decades of power and two and a half decades of active gate area.
  • The scoreboard retains bench provenance, including 19 hollow amplifier points evaluated on earlier lighter-load benches rather than the archived uniform 10 pF bench.Both figures are generated from released catalog and scoreboard artifacts and can be regenerated from the archived revision.
  • 34 of 71 recorded regulator design points are validated across power, area, supply rejection, dropout, and load regulation.The regulator view projects onto regulation metrics because only one regulator datasheet declares a loop-gain bound at this revision.
  • 10 of 34 regulator points also fall within the class-level reference band, while the remaining plotted points pass their own datasheets but lie outside that common band.All plotted points pass their evaluated datasheets at the typical corner under each entry’s recorded operating conditions.

V. DISCUSSION

The discussion argues that a schema-governed representation can carry reproducibility, portability, and machine actionability across reusable analog designs, while identifying limits in annotation coverage, corpus balance, agent evaluation, modeling, verification, and layout maturity.

  • A schema-governed object containing topology, parameters, contracts, and bindings carries reproducibility, portability, and machine actionability in the released representation.The representation is intended to shift these properties from author-specific release practice into the shared design object.
  • A loop phase margin certifies only the loop it measures: 021_yan_az sustained a 1.84 Vpp internal oscillation despite an outer-loop margin of +69°.The corpus therefore uses a zero-input transient as the deciding stability check for this case.
  • Structural annotation covers 51% of corpus devices, but only 38% of amp_029 and 25% of its CMFB-closed composite amp_030 receive assigned roles.The archived template library has no common-mode-feedback template, making library growth the first stated direction.
  • Amplifiers and OTAs comprise 33 of 68 circuits, while data-converter, sampler, and trim classes each contain one entry.Generality beyond amplifier-like blocks is therefore less exercised than depth on amplifiers.
  • The agent evidence consists of two author-supervised sessions using one coding agent and model, without a comparison arm denying access to structural artifacts.Recorded simulator costs also count different quantities across the two disciplines.
  • Reported figures use nominal schematics with perfectly matched devices, so mismatch-sensitive rejection, offset, and residual-ripple results are upper bounds.No released entry includes layout or extracted parasitics, and no result has yet been correlated against silicon.
  • All archived design points use the typical corner, leaving multi-corner PVT evaluation and optimization for future work.Clocked-circuit verification also falls back to windowed transient analysis because the open-source simulator lacks a periodic steady-state alternative.
  • The case study found four hand-entry defects and a missing common-mode feedback loop that the sizing-only baseline did not repair.The agent assembled op-amp cores into a closed-loop system with an idealized common-mode servo.

APPENDIX A BENCHMARK RESULTS

The appendix re-simulates released benchmark entries under defined, class-specific measurement procedures and reports failures, repairs, and corrected stability evaluations. Results expose both circuit defects and measurement errors while distinguishing per-entry specifications from common class bands.

  • All tabulated benchmark values are re-simulated from the archived database rather than transcribed from source publications.
  • Amplifier Benchmark: Six high-gain gf180mcu amplifier cells required corrected phase-margin benches after self-referenced sweeps overstated stability.The repair moves the sweep start below the dominant pole while retaining unwrapped phase.
  • Amplifier Benchmark: Corrected benches agree with an independent loop-gain bench on 13 of 14 comparable entries, resolving discrepancies of up to 89°.Transient tests found limit cycles in entries assigned negative corrected margins and settling in the others.
  • LDO Benchmark: 10 of 23 regulator bindings meet the common phase-margin class band, compared with 3 of 23 under the prior output-impedance proxy.The phase-margin band replaced the proxy without changing the corpus, shifting the failures toward quiescent current.
  • LDO Benchmark: A resistive tie and compensation retune made regulator 005 datasheet-compliant on both gf180mcu and ihp-sg13g2.The repair achieved 340 mV dropout on gf180mcu within its 400 mV specification and was recorded with the entry.

APPENDIX B DOMAIN-SPECIFIC LANGUAGE

The appendix specifies the concrete syntax and schema decisions of the representation through a running two-stage Miller OTA example and a hierarchical composite amplifier.

  • The representation’s concrete syntax and schema decisions are illustrated with amp_022_fer_two_stage and the hierarchical amp_030_miller_cmfb_composite.Every artifact conforms to a versioned schema.

A. Expressing Parametrization

Parametrization separates process-neutral structural relationships from per-PDK sizing choices, exposing named device parameters, matching constraints, ratios, bounds, and freezes.

  • The abstract parameter artifact contains generated device-to-symbol mappings and authored ties that declare structural matching and multiplier ratios.Matched groups can tie width, length, and multiplier across devices, while ratios preserve fixed relationships.
  • Per-PDK sizing bindings supply technology-specific defaults and bounds, while freeze: true withholds a parameter from search without deleting its record.The sizing artifact is separate from the process-neutral abstract parameterization.
  • A recorded design point stores concrete parameter values and metrics under a design_id hashing the circuit, PDK, and sizing.The scoreboard example records both sizing parameters and measured typical-corner metrics.

B. Expressing Metrics and Testbenches

Class-owned metric vocabularies and reusable testbench templates standardize analyses, while each circuit’s datasheet binds measurements and acceptance specifications into the verification contract.

  • The class registry owns canonical metric names and testbench templates, so identical metrics use the same measurement conventions across circuits.Circuit analysis files instantiate class templates at stated operating conditions.
  • Each datasheet declares the analysis, extraction, and specification defining how every canonical metric is measured and judged.The verification harness and scoreboard evaluate against this same datasheet artifact.

C. Expressing PDKs and Simulators

PDK knowledge is centralized in technology-specific registries, while circuit bindings reference generic device mappings, corners, and sizing files to support kit retargeting and tiered verification.

  • Registry and simulator representation: Each technology stores PDK knowledge in one registry, while corner libraries remain external and are referenced by file name and section.The database can clone and verify through kit-free tiers; simulation tiers require PDK presence, and released PDKs use ngspice.
  • Circuit bindings: Each circuit binding maps generic device kinds to process-kit devices and names its corner selections.The binding specifies device models and corners such as tt, ss, ff, sf, and fs.
  • Retargeting: Retargeting a circuit to an additional process kit requires the kit mapping files plus sizing.yaml.The process-specific files provide device maps, corner definitions, and simulator-related configuration.

D. Expressing Hierarchy and Sub-blocks

Composite circuits are authored as manifests that assemble version-pinned database blocks, connect their ports, expose internal nets, and apply composite-level overrides and bias ownership.

  • Composition manifests: A composite manifest instantiates existing blocks at exact topology revisions and wires their ports.Each revision is represented by a content hash checked by the compose validator.
  • Composite-level adjustments: Composite authors may tap internal nets, omit block-local bias elements, and override block parameters.The example exposes an internal bias net, transfers bias ownership to the composite, and overrides a servo resistance value.
  • CMFB closure: The condensed amp_030_miller_cmfb_composite closes amp_029 with a behavioral common-mode-feedback servo block.The manifest connects the servo to amplifier outputs and composite-owned reference and bias nets.

APPENDIX C ARTIFACT AVAILABILITY

The released artifacts document reproducibility conditions, benchmark conventions, exclusions, and known limitations across amplifier, regulator, and chopper results.

  • Artifact availability: The database is publicly released in the analog-db/ component of spicexplorer-release, with results tied to archived release v1.1.2.The repository is available at github.com/MacAnalog/spicexplorer-release.
  • Benchmark conditions: Amplifier benchmarks in IHP 130nm, GF180MCU, and SKY130 re-simulate released sizings under uniform conditions.The tables specify CL=10 pF, a unity-gain buffer, 1 Hz–1 MHz noise, and THD procedures.
  • Chopper comparison: Adding CMFB to the chopper core improves both common-mode-path columns by 43.4 dB on ihp-sg13g2 for 0.8 dB of differential gain.The chopper was characterized with its output chopper held static, leaving the common-mode path unchanged.
  • Measurement caveats: CMRR and PSRR figures are systematic upper bounds because mismatch is excluded, and readings at or above 180 dB are solver-floor bounds.Fully differential rows measure the common-mode path with differential gain folded in.
  • Regulator results: 10 of 23 regulator bindings meet the common class band, while 19 of 23 meet the Vout/regulation/PSRR/dropout core.Failures concentrate in Iq, with 10 of 23 failing, and load regulation, with 2 of 23 failing.
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