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Performance Characterization of SPEC CPU 2026 on AMD EPYC 9755 Processor

Kunal Kashyap, Rajiv Ramanathan, Shayantika Bhattacharya

arXiv:2609.01527v1cs.ARcs.PF

TL;DR

SPEC CPU 2026 lacked systematic microarchitectural characterization, particularly on AMD Zen, despite its relevance to datacenter processors. The paper applies multi-lens profiling and scale analysis on AMD EPYC Zen 5, comparing isolated and full-system behavior. It finds three workload clusters and shows that SMT contention, bandwidth saturation, and L3 capacity interference can emerge at scale.

  • Problem

    SPEC CPU 2026 had no systematic microarchitectural characterization, and prior SPEC CPU studies predominantly examined Intel platforms rather than AMD Zen architectures.

  • Method

    The study profiles SPECrate and SPECspeed on AMD EPYC Zen 5 using four complementary lenses and compares single-instance with full-system behavior.

  • Results

    The suite exhibits three behavioral clusters: branch-predictor-throughput-limited frontend workloads, SMT-contentended compute workloads, and memory-bandwidth-bound workloads with poor L3 filtering.

  • Takeaways & Limitations

    Scale analysis is essential because full-system utilization reveals bottlenecks invisible in single-instance characterization, including SMT dispatch contention and L3 capacity interference.

  • Takeaways & Limitations

    The frontend-stall shift is reported only as a preliminary qualitative observation because rigorous frontend decomposition was beyond the study’s scope.

Abstract

from arXiv · show

SPEC CPU 2026 is the first major update to the industry-standard CPU benchmark suite since 2017. This paper presents the first microarchitecture based performance characterization of the new suite, conducted on AMD EPYC "Zen 5", also the first SPEC CPU characterization study on this microarchitecture. Using a multi-lens methodology spanning pipeline efficiency, control flow behavior, cache hierarchy pressure, and instruction mix, we analyze both SPECrate and SPECspeed suites. We introduce scale analysis, comparing single-copy to full-system behavior to expose system-level bottlenecks invisible to conventional characterization. Our analysis reveals substantial behavioral diversity across the suite, and the multi-lens analysis identifies three distinct behavioral clusters: frontend control-flow-dominated workloads that stress branch predictor throughput rather than accuracy, high-efficiency compute workloads that suffer SMT contention at scale, and memory bandwidth-bound workloads with poor L3 filtering even at single-copy. Scale-dependent effects, including SMT dispatch contention causing throughput reduction and L3 capacity interference, emerge only at full system utilization. This work establishes an empirical foundation for architectural research and workload-driven design decisions targeting next-generation datacenter processors.

1. Introduction

The paper addresses the lack of systematic microarchitectural characterization for SPEC CPU 2026 and AMD Zen architectures, using scale analysis to expose server-level bottlenecks. It contributes a multi-lens workload taxonomy and parallelism analysis for the updated suite.

  • Research gaps: SPEC CPU 2026 lacks systematic microarchitectural characterization, while prior SPEC CPU studies focused predominantly on Intel platforms.The paper also notes that no SPEC CPU suite had been characterized on AMD Zen microarchitectures.
  • Research gaps: Scale analysis compares single-instance with full-system behavior to expose cache interference, SMT dispatch contention, and memory bandwidth saturation.These bottlenecks can emerge only when the full system is utilized.
  • Contributions: The study applies four lenses—pipeline efficiency, control flow, cache hierarchy pressure, and instruction mix—to characterize SPEC CPU 2026.It analyzes both SPECrate and SPECspeed workloads.
  • Contributions: The paper identifies three behavioral clusters based on dominant bottleneck type and their optimization implications.The clusters distinguish frontend, compute, and memory-oriented behavior.
  • Contributions: Parallelism analysis of SPECspeed 2026 evaluates its expanded multithreaded coverage and reveals scaling diversity across application domains.The analysis complements the workload taxonomy with system-scale parallelism behavior.

2. Background and Related Work

SPEC CPU 2026 expands benchmark coverage and microarchitectural diversity relative to CPU 2017, while this work fills the remaining gap in systematic characterization on AMD Zen 5. The background describes the EPYC architecture and prior benchmark studies motivating the analysis.

  • SPEC CPU 2026 Overview: SPEC CPU 2026 contains 52 applications across rate and speed suites targeting throughput-oriented and latency-oriented workloads.Reference workloads are the largest inputs and are used for official timing and scoring.
  • SPEC CPU 2026 Overview: Compared with CPU 2017, the suite adds cryptography, neuroscience, and graph analytics domains and expands multithreaded integer coverage.SPECspeed Integer includes 9 of 13 multithreaded benchmarks, compared with one in CPU 2017.
  • Zen 5 Architecture: 5th Gen AMD EPYC uses a hybrid multidie design that separates CPU cores from I/O functions through multiple CCDs and a central I/O die.This allows core and analog I/O circuitry to use different process technologies.
  • Zen 5 Architecture: Zen 5 redesigns the frontend and execution engine, with an 8-wide dispatch/retire path and native 512-bit AVX-512 execution.Each CCD integrates eight cores sharing a 32 MB L3 cache.
  • Zen 5 Architecture: The memory hierarchy combines a 48 KB L1 data cache, private 1 MB L2 caches, and up to 614 GB/s of socket memory bandwidth.The socket integrates 12 DDR5-6400 controllers.
  • Related Work: Prior SPEC CPU studies examined hot routines, event behavior, suite evolution, instruction mix, branches, caches, and memory footprints, but systematic characterization on Zen 5 remained absent.The paper positions its study as addressing this architecture-specific gap.

3. Methodology

The methodology profiles reference workloads on an AMD EPYC Zen 5 system using controlled rate and speed scales, GCC-based compilation, AMD uProf counters, and Top-Down Microarchitectural Analysis. These measurements support steady-state comparison of pipeline, cache, memory, and scaling behavior.

  • Experimental Setup: All benchmarks use GCC 15.2.0 with -O3, -march=znver5, and -flto to target the Zen 5 ISA with performance-oriented compilation.The configuration includes AVX-512 and VNNI extensions without profile-guided optimization.
  • Experimental Setup: Reference workloads are used for both rate and speed suites because they are the largest inputs and support official SPEC scoring.The study collects data across both suite types.
  • Experimental Setup: Rate experiments use 1-copy and 512-copy configurations, while speed experiments use 1-thread and 512-thread configurations.Single-copy or single-thread runs establish isolated baselines; full-scale runs expose scalability and contention.
  • Experimental Setup: The experiments run on an AMD EPYC 9005 Series system featuring Zen 5 cores.Table 1 summarizes the complete hardware and software environment.
  • Performance Measurement Framework: AMD uProf collects approximately 100 performance metrics per sample at 2-second intervals, including pipeline, instruction, cache, and bandwidth measures.The AMDuProfPcm executable provides system-wide time-series sampling.
  • Performance Measurement Framework: Top-Down Microarchitectural Analysis classifies pipeline slots as frontend bound, backend bound, pipeline stalls, or retiring, with uProf also exposing SMT contention.SMT contention represents unused dispatch slots when the other thread is selected.

4. Microarchitectural Characterization of SPEC CPU®2026

The characterization combines four complementary lenses to explain how SPEC CPU 2026 workloads use pipeline, control-flow, memory, and execution resources. Cross-referencing these measurements identifies workload clusters and outliers for the paper’s synthetic analysis.

  • Top-Down Microarchitectural Analysis: Top-Down Microarchitectural Analysis asks where pipeline slots spend time and how efficiently each core is utilized.It provides the pipeline-efficiency perspective for comparing workloads.
  • Control Flow Characteristics: Control-flow analysis examines variation in control-flow complexity and branch behavior across workloads.This lens supports identification of branch-related workload behavior.
  • Cache and Memory Subsystem Behavior: Cache and memory analysis identifies where workloads apply pressure within the memory hierarchy.The lens distinguishes hierarchy-level pressure patterns across benchmarks.
  • Instruction Mix and SIMD Utilization: Instruction-mix and SIMD analysis uses computational composition and vectorization behavior to characterize workload execution.This lens complements pipeline, control-flow, and memory measurements.
  • Cross-lens synthesis: AMD uProf data are organized around similar workload clusters and outliers, with cross-references building toward the synthetic analysis in Section 5.The analysis links observations across all four lenses.

4.1. Top-Down Microarchitectural Analysis

TMA analysis exposes diverse bottlenecks across rate and speed benchmarks, with scale-dependent memory saturation and SMT contention emerging at full utilization. The workloads span frontend instruction-supply limits, efficient computation constrained by SMT sharing, and severe backend-memory pressure.

  • SPECrate at 512-copy: 765.roms_r and 749.fotonik3d_r show severe memory saturation at 512-copy, with Retiring collapsed to 1%.These workloads, together with 782.lbm_r, 722.palm_r, and 772.marian_r, are among the suite’s most memory-constrained benchmarks.
  • SPECrate at 512-copy: At 512-copy, SMT dispatch contention averages 19.3% across the suite and particularly affects high-efficiency workloads.The highest contention occurs in 750.sealcrypto_r, 707.ntest_r, and 736.ocio_r.
  • SPECrate at 512-copy: 512-copy IPC ranges from 0.42 for 765.roms_r to 2.71 for 750.sealcrypto_r, reflecting throughput degradation under SMT and memory pressure.Higher Retiring generally corresponds to higher IPC, although the relationship is not linear.
  • Single-copy behavior: At 1-copy, frontend-dominated workloads include 727.cppcheck_r and 709.cactus_r, while backend-memory workloads include 749.fotonik3d_r and 765.roms_r.Integer workloads show greater frontend pressure, whereas floating-point workloads cluster toward backend-memory constraints.
  • Scale analysis: Scaling from 1-copy to 512-copy raises BE Memory from 45.3% to 90.3% for 765.roms_r and from 54.0% to 87.5% for 749.fotonik3d_r.SMT contention is absent at 1-copy but averages 19.3% at 512-copy as memory bandwidth saturates.
  • Measurement scope: The 512-thread speed TMA accounting averages only 95.3% in barrier-heavy HPC codes because blocking synchronization falls outside the framework.By comparison, 512-copy rate and 1-thread speed benchmarks provide near-complete accounting.
  • SPECspeed behavior: SPECspeed workloads range from 1.26 IPC for 823.llvm_s to 4.59 for 811.tealeaf_s, while 800.pot3d_s reaches only 1.46 IPC with 75.7% Backend Memory.The speed suite includes both high-retiring parallel workloads and memory- or frontend-constrained workloads.
  • Parallelism: SPECspeed parallelism is diverse: 820.cloverleaf and 811.tealeaf_s exceed 80% utilization, while 829.abc_s and several others remain below 1%.The suite expands multi-threaded coverage but retains largely serial workloads where parallelization is difficult or representative inputs are unavailable.

4.2. Control Flow Characteristics

Control-flow behavior differs across benchmark domains: integer workloads have higher branch density, while specific workloads exhibit either high branch misprediction or frontend pressure from frequent branches. The cppcheck case shows that predictor throughput, rather than prediction accuracy, can constrain instruction supply.

  • Misprediction: 731.astcenc_r, 777.zstd_r, 737.gmsh_r, 729.abc_r, and 706.stockfish_r have the highest rate-suite misprediction rates.Adaptive texture compression and data compression contribute inherently irregular control flow in astcenc and zstd.
  • Frontend pressure: 727.cppcheck_r has nearly one branch every 3–4 instructions and only 0.32% misprediction, yet remains frontend-bound.Its regular, frequent branches consume predictor throughput even when prediction accuracy is near-perfect.
  • Workload contrast: 721.gcc_r has branch density comparable to cppcheck but higher misprediction, producing Backend Bound rather than Frontend Bound behavior.The contrast is attributed to gcc’s irregular data-dependent branching versus cppcheck’s regular control flow.
  • Branch density: Integer benchmarks average 176 BrKI versus 91 BrKI for floating-point benchmarks, consistent with greater control-flow intensity.The highest-density workloads include cppcheck, gcc, ns3, llvm, and gem5.
  • SPECspeed control flow: Speed benchmarks show similar branch characteristics, with graph500_s, cppcheck_s, and llvm_s having the highest branch density.The highest speed-suite misprediction rates occur in neutron_s, xz_s, and namd_s.

4.3. Cache and Memory Subsystem Behavior

SPEC CPU 2026 workloads show diverse cache-filtering and memory-bandwidth behavior. Rate workloads can saturate system bandwidth at scale, while speed workloads follow a different shared-memory scaling regime.

  • High L1D MPKI does not uniformly produce high L3 MPKI, revealing substantial variation in cache-filtering effectiveness.Cactus and marian show strong L2/L3 locality, whereas roms, fotonik3d, lbm_r, and pot3d_s sustain L3 misses.
  • 870-931 GB/s: several rate benchmarks approach or exceed the approximately 614 GB/s per-socket theoretical bandwidth at 512 copies.The highest consumers are roms_r, palm_r, fotonik3d_r, femflow_r, and lbm_r; all workloads exceeding 850 GB/s are floating-point benchmarks.
  • Integer workloads generally benefit from effective cache filtering and rarely saturate memory bandwidth, producing more balanced TMA profiles at scale.
  • 378 GB/s versus 931 GB/s: 865.roms_s at 512 threads remains below 765.roms_r at 512 copies because shared-memory execution reduces redundant DRAM traffic.Some speed workloads even draw lower bandwidth at 512 threads than at one thread.

4.4. Instruction Mix and SIMD Utilization

Instruction mix exposes broad SIMD diversity across floating-point and integer workloads. Zen 5’s AVX-512 benefits extend to integer algorithms, but several floating-point workloads remain scalar-dominated.

  • 765.roms_r, 766.femflow_r, 772.marian_r, and 749.fotonik3d_r have the highest AVX-512 utilization among floating-point benchmarks.765.roms_r achieves 10.4 GFLOPs through vectorized stencil computations.
  • 61.6% AVX-512 utilization: 750.sealcrypto_r uses wide-integer arithmetic, while 706.stockfish_r reaches 39.8% for SIMD bitboard operations.
  • Several FP-intensive workloads, including 782.lbm_r and 709.cactus_r, are predominantly scalar or 128-bit despite their floating-point focus.
  • 817.flac_s has the highest AVX-512 utilization among speed integer benchmarks, while 829.abc_s, 827.cppcheck_s, and 807.ntest_s show substantial AVX-256 use.The wider operations support audio encoding, string/pattern matching, and analysis tasks.
  • 782.lbm_r achieves 8.6 GFLOPs with 0% AVX-512, operating entirely in scalar/128-bit mode.The passage identifies this as a vectorization opportunity not exploited by the compiler.
  • Integer workloads actively use SIMD across vector widths for string matching, bitwise operations, and memory operations.

5. Synthesis and Design Implications

Combining four characterization lenses yields three workload clusters with distinct bottlenecks and remedies. Full-system behavior adds SMT dispatch contention and shared-L3 interference that single-copy analysis misses.

  • Workload Clustering and Taxonomy: Control-flow-dominated integer workloads stress branch-predictor throughput rather than accuracy.They combine high frontend bound, exceptionally high branch density, and low misprediction rates.
  • Workload Clustering and Taxonomy: High-efficiency compute workloads use Zen 5’s dispatch width effectively at one copy but experience the highest SMT resource sharing at 512 copies.Dispatch efficiency, rather than vector width, unifies vector-intensive and scalar-dominated members of this cluster.
  • Workload Clustering and Taxonomy: Memory-bandwidth-bound floating-point workloads dominate backend-memory pressure, saturate bandwidth, and scale directly with memory-subsystem throughput.
  • Workload Clustering and Taxonomy: 43.0% to 13.2% Retiring: 772.marian_r collapses at 512 copies as L3 MPKI increases 10.3x under shared 32 MB L3 capacity interference.Its moderate bandwidth consumption distinguishes capacity contention from bandwidth saturation.
  • Implications for Architects and Software Developers: 772.marian_r suggests L3 partitioning, whereas 765.roms_r requires memory-subsystem improvements because their memory bottlenecks differ.
  • Implications for Architects and Software Developers: 19.3% average throughput reduction: the most dispatch-efficient workloads suffer SMT contention only at 512-copy full-system utilization.Memory-bandwidth-bound workloads instead show poor L3 filtering already at single copy, indicating structural low reuse rather than contention.
  • Implications for Architects and Software Developers: Keeping inference working sets within one CCD’s 32 MB L3 avoids the pipeline inefficiency observed when 512 instances compete for shared capacity.

6. Conclusion

The study characterizes SPEC CPU 2026 on Zen 5 across multiple microarchitectural lenses and scales. It finds wide behavioral diversity, scale-dependent contention and interference, and divergent parallel scaling, while motivating further studies.

  • The paper provides the first microarchitecture-based characterization of SPEC CPU 2026 on AMD EPYC Zen 5 and compares single-copy with full-system behavior.
  • 3.3x IPC range: SPEC CPU 2026 spans substantial behavioral diversity across benchmarks.
  • The suite contains three clusters: branch-throughput-limited frontend workloads, dispatch-efficient workloads with scale-induced SMT contention, and memory-bandwidth-bound workloads with poor single-copy L3 filtering.
  • 772.marian shows scale-dependent L3 capacity interference, with Retiring collapse despite moderate bandwidth, unlike bandwidth-saturated workloads.
  • 19% average effective-throughput reduction occurs from SMT dispatch contention at 512 copies for the most dispatch-efficient benchmarks.
  • SPECspeed scaling ranges from near-perfect thread utilization to essentially serial execution across applications.
  • Future work should examine power efficiency, noisy-neighbor effects, compiler sensitivity, and memory technology sensitivity.
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