Agent-Native Metamorphic Communication Fabric

II. RELATED WORK AND POSITIONING

• Earlier data-driven and foundation-model workflows expand offline algorithm search, but their principal artifacts are normally fixed before deployment and cannot anticipate every future service and channel combination.The related-work discussion contrasts trained models and design-time coding agents with runtime selection among inspectable, executable candidates.Source: §I · p. 1, §II · p. 2

I. INTRODUCTION

• The proposed runtime loop observes state, forms and verifies explicit candidates, then deploys only after safety gates pass, with monitoring and fallback.The agent may combine a language-model proposer, deterministic optimizer, registered library, and digital-twin evaluator without putting an LLM in the real-time data path.Source: §I · p. 1
• The framework defines Level 1 parameter selection with protocol, waveform, and algorithm topology fixed; Level 2 receiver-solution selection with protocol, waveform, and objective fixed; and Level 3 waveform/multiple-access selection with service, regulatory, and safety constraints fixed.“Metamorphic” denotes controlled change of communication form under explicit invariants, not unconstrained mutation.Source: §I · pp. 1–2
• The paper’s experiments cover three levels: parameter agents, two-timescale receiver adaptation, and waveform adaptation across representative regimes and continuous sweeps.The introduction distinguishes generated-baseband evidence from analytical BLER, latency, complexity, and power abstractions for Level 3.Source: §I · p. 2
• The current agent is bounded to choosing and configuring human-registered tools, not inventing a coding theorem, emitting production code, or reconfiguring an SDR or FPGA.The stated contribution is a falsifiable minimum viable loop that makes the changing object, decision evidence, and safety boundary explicit.Source: §I · p. 2

II. RELATED WORK AND POSITIONING

• Executable-evaluation workflows treat generated artifacts as candidates, using domain execution and hard validation as the basis for trust.Examples use physical diagnostics, numerical and hardware evidence, or synthesis, simulation, and error compensation.Source: §II · p. 3, Figure 2 · p. 3

III. AGENT-NATIVE METAMORPHIC ARCHITECTURE

• At each decision epoch, the observer forms a state describing service intent, channel and mobility, spectrum and load, hardware capabilities, and energy and thermal budgets.Uncertainty is handled with conservative gates and fallback rather than an assumption of perfect context.Source: §III · p. 3
• Each candidate yields a metric vector covering throughput, effective spectral efficiency, reliability loss, latency, energy, power, complexity, and spectral containment.Feasibility gates may include reliability, EVM, residual, divergence, spectral, resource, and hysteresis constraints; selection occurs only among feasible actions.Source: §III · pp. 3–4
• If no action is feasible, the agent retains or returns to a registered minimum-risk baseline, preventing utility weighting from trading away hard reliability or spectral constraints.The available actions expand with adaptation level, from parameters to receiver-solver choices and waveform or multiple-access choices.Source: §III · p. 4
• The selected action is serialized as a versioned deployment manifest with implementation hash, interface, resource envelope, activation epoch, and verified fallback.This representation is intended to prevent deployment through an incompatible binary, bitstream, numerology, or endpoint interface.Source: §III · p. 4
• The levels form a governance hierarchy: Level 2 combines slow default-solver selection with a fast per-block guard, while Level 3 requires endpoint agreement, versioning, activation control, hysteresis, and rollback.Larger change surfaces require stronger evidence and slower deployment.Source: §III · p. 4

A. Transactional Hardware Execution Model

• Deployment proceeds through prepare checks, shadow evaluation without transmit authority, atomic commit at an agreed boundary, and monitoring that can trigger rollback.Prepare checks include the manifest, interface, memory, execution budget, endpoint capability, and fallback availability.Source: A. Transactional Hardware Execution… · pp. 4–5
• Offline design artifacts are retained in a typed runtime library, where their suitability is re-evaluated as task, channel, spectrum, load, and hardware budgets change.The agent extends rather than discards offline design.Source: Figure 4 · p. 5
• CPU/GPU/SDR, FPGA, and ASIC implementations may use different mechanisms, but the real-time path should not execute arbitrary newly generated code.The agent selects pre-characterized artifacts whose timing, fixed-point behavior, memory layout, and RF interface have been characterized.Source: A. Transactional Hardware Execution… · p. 5

B. Role of Foundation Models

• A foundation model may propose, retrieve, generate, or diagnose candidates, but it cannot bypass the typed registry or deployment gates.The reported experiments use deterministic enumeration and task-weighted selection for reproducibility; an LLM proposer is compatible but not required.Source: B. Role of Foundation Models · p. 5

IV. EVALUATION METHODOLOGY

• The experiments use frozen seeds and machine-readable artifacts; Level-1 evaluations average four runs, each with 500 coded blocks and 1200 PAPR blocks.The reported results are simulation evidence, not hardware measurements; Level-1 results use the stated evaluation setup.Source: §IV · p. 5

A. State, Robust Gates, and Hardware Mapping

• A Level-1 controller aggregates channel, queue, deadline, and hardware state, then ranks only candidates whose confidence-adjusted metrics pass reliability and hardware gates.Estimator variation and model mismatch set operating margins; an empty feasible set returns the baseline.Source: A. State, Robust Gates, and Hardware… · p. 6
• The controller writes and verifies a complete inactive configuration bank before an atomic frame-boundary switch, while multi-precision selection requires synthesized widths or prebuilt kernels.Changes to MCS, pilot pattern, or cyclic prefix require dual-endpoint signaling; frequent adaptation should account for signaling and transition costs.Source: A. State, Robust Gates, and Hardware… · pp. 6–7

V. LEVEL 1: PARAMETER ADAPTATION

• Level-1 agents convert reliability margin into rate or energy efficiency, while tracking trades measurable rate, latency, and energy for lower BER.The precision agent retains link performance by choosing the lowest approved precision that passes the BER gate; the computation graph remains fixed.Source: A. State, Robust Gates, and Hardware… · pp. 6–7

VI. LEVEL 2: RECEIVER ALGORITHM ADAPTATION

• Direct MMSE, weighted Jacobi, and diagonal-PCG solve the same system but differ in numerical path, convergence region, approximation error, and hardware cost.Jacobi is suited to spectral radius below one and near-diagonal dominance; diagonal-PCG can cover an intermediate region where Jacobi is unsafe.Source: §VI · p. 7

A. Two-Timescale Guard and Solver Hardware

• A slow controller selects the nominal solver, while per-block guards monitor conditioning and convergence and can dispatch the same buffered matrix and vector to direct MMSE after a failed check.The energy and latency results are analytical hardware-proxy predictions, not hardware measurements; the proxy omits common channel-estimation and front-end operations.Source: A. Two-Timescale Guard and Solver… · p. 7
• The policy uses three Jacobi iterations in favorable channels, PCG-5 in intermediate channels after low-order Jacobi diverges, and direct MMSE in harsh channels despite PCG-5 passing the loose gate, owing to lower BER, EVM, and residual.Source: A. Two-Timescale Guard and Solver… · p. 7
• In the intermediate scenario, 9.29% of blocks upgrade from PCG to direct MMSE, reducing BER from 2.364×10−2 to 2.116×10−2 after guarded execution.In favorable channels, 1.57% of blocks upgrade from Jacobi to PCG; harsh-scenario blocks remain on direct MMSE.Source: A. Two-Timescale Guard and Solver… · p. 7
• At 0–6 dB the agent uses direct MMSE, at 9–15 dB PCG-3, and at 18–24 dB Jacobi-3; modeled solver-power reductions are 39.7% and 67.1% for PCG-3 and Jacobi-3, respectively.The sweep uses a BER gate of 0.04 and requires at least 95% of direct MMSE's effective spectral efficiency; powers are analytical compute powers at 10 million vectors/s.Source: A. Two-Timescale Guard and Solver… · p. 8

VII. LEVEL 3: WAVEFORM AND MULTIPLE-ACCESS ADAPTATION

• Level 3 changes the physical signal representation while retaining the service contract, regulatory limits, capability exchange, and fallback behavior.The scenario state includes SNR, normalized Doppler, spectrum contiguity, offered load, RF/baseband budgets, and task gates.Source: §VII · p. 8
• The procedure receives scenario statistics, a candidate library, and task weights, and returns a deployable waveform chain or a minimum-risk fallback.The provided outline describes its input and output but does not supply comparative outcome values.Source: §VII · pp. 8–9
• The outlined adaptation checks stability and conditioning, selects a solver path, and falls back to direct MMSE when residual, EVM, convergence, or deadline gates fail.The procedure also records the selected solver, iteration count, residual trajectory, cycles, stalls, saturation, and fallback reason.Source: §VII · pp. 8–9

• A Level-3 action specifies an executable chain and manifest, not merely a waveform name.The manifest includes numerology, resource map, filter or codebook coefficients, matching receiver, state policy, and RF profile; both endpoints acknowledge its hash and activation epoch before changing representation.Source: A. Waveform Manifest and Coordinated… · p. 9
• Switching accounts for pipeline drain, loading, reacquisition, RF settling, and state movement, amortized over expected residence time.A switch is suppressed unless predicted utility improvement exceeds its transition cost; hysteresis helps prevent repeated waveform oscillation near changing estimates.Source: A. Waveform Manifest and Coordinated… · p. 9
• Level-3 implementation is bounded by available hardware: SDRs and FPGAs trade resident resources against reconfiguration delay, while ASICs are limited to fabricated engines.Analog and mixed-signal controls expose calibrated ranges, and RF settling plus EVM/ACLR revalidation precede a successful commit.Source: A. Waveform Manifest and Coordinated… · p. 9
• Only candidates in the feasible set enter the task-weighted decision; candidates failing hard gates are removed first.The gates include delay, power, and complexity limits.Source: A. Waveform Manifest and Coordinated… · p. 9

B. Interpretation of the Selected Waveform Chains

• Continuous sweeps select CP-OFDM at normalized Doppler 0–0.05, SC-FDMA near 0.08, and OTFS from approximately 0.10 to 0.40.Filtered OFDM is selected at spectrum contiguity 0.30–0.90; CP-OFDM remains feasible up to normalized load 1.10, while SCMA-over-OFDM is selected from 1.15 to 1.50.Source: B. Interpretation of the Selected… · pp. 10–11
• CP-OFDM remains selected for continuous-spectrum broadband downlink at 2.320 bit/s/Hz goodput SE, while SC-FDMA serves the PA-limited terminal uplink.For the uplink, SC-FDMA yields 25.24 nJ/bit while keeping BLER at 3.78 × 10−3 under the present PA model.Source: B. Interpretation of the Selected… · pp. 9–10, Table VIII · p. 11
• At normalized Doppler ν = 0.30, OTFS remains feasible when OFDM-derived candidates lose reliability and latency gates, reaching 1.976 bit/s/Hz at BLER 7.92 × 10−3.Its processing-complexity factor is 2.75, making the selection a context-dependent compute–mobility trade-off.Source: B. Interpretation of the Selected… · p. 10, Table VIII · p. 11
• At spectrum contiguity cf = 0.42 with a 22-dB ACLR gate, filtered OFDM is the only spectrally feasible chain, reaching 22.66-dB leakage proxy and 1.889 bit/s/Hz goodput SE.Its 257-tap Kaiser-window FIR makes filter delay and multiply cost explicit in the candidate manifest.Source: B. Interpretation of the Selected… · p. 10, Table VIII · p. 11
• At offered load ρL = 1.38, SCMA-over-OFDM is the only feasible candidate, reaching 2.645 bit/s/Hz aggregate goodput SE, BLER 1.06 × 10−2, and 9.92-ms P95 latency.Its complexity factor is 4.20 and becomes decisive when the connectivity requirement is relaxed.Source: B. Interpretation of the Selected… · p. 10, Table VIII · p. 11
• The switching boundaries are empirical properties of current channel distributions, power model, task weights, and hard gates, not standards constants.Changing the PA model, BLER abstraction, bandwidth, candidate implementation, or service weights can move them.Source: B. Interpretation of the Selected… · p. 11

A. Two Paradigm Transitions

• The paper distinguishes algorithm-production change from runtime change: an offline-selected implementation becomes a versioned object an agent may parameterize, replace, or reconfigure after executable verification.The experiments focus on the runtime transition.Source: A. Two Paradigm Transitions · p. 11
• The three autonomy levels progress from changing values in a fixed graph, to changing the numerical solver for a fixed receiver objective, to changing the transmitted representation or multiple-access chain.A higher level is not inherently better; preserving direct MMSE or CP-OFDM can be the safest feasible action.Source: A. Two Paradigm Transitions · pp. 11–12

B. Safety and Implementation

• Four safeguards bound adaptation: registered typed actions, hard gates before utility, endpoint agreement on Level-3 artifacts, and post-deployment monitoring with hysteresis and fallback.Lowering artifacts to code or hardware requires verification of that mapping too.Source: B. Safety and Implementation · p. 12
• A non-real-time intelligence plane may use LLMs, search, simulation, and traces, while a deterministic real-time controller executes bounded estimation, gate evaluation, scheduling, and watchdog logic.No token generation is required at symbol, sample, or channel-block rates; the link can retain its last-known-good artifact if agent services are unavailable.Source: B. Safety and Implementation · p. 12
• Hardware admission checks artifact-level evidence before performance utility, including execution time, memory and timing bounds, RF calibration, and verified rollback.A higher simulated rate cannot admit a candidate that may miss deadlines, overflow memory, violate a spectral mask, or lack rollback.Source: B. Safety and Implementation · p. 12
• The Level-3 procedure observes channel and operating state, evaluates executable candidates, removes those failing reliability, spectral, power, or complexity gates, then maximizes weighted utility among survivors.If none survives, it minimizes violated gates and risk, while charging transition costs.Source: B. Safety and Implementation · p. 13
• After commit at an agreed epoch, monitoring can trigger local fallback on fast violations; repeated fallbacks invalidate the manifest for that context and return evidence to offline generation.The switching procedure pre-stages kernels, coefficients, state policy, RF profile, and fallback, then monitors and rolls back on violation.Source: B. Safety and Implementation · p. 13

C. Evidence Limitations

• Level 1 uses coded baseband Monte Carlo and engineering models; Level 2 uses analytical energy and latency proxies, and Level 3 retains analytical BLER, latency, complexity, PA, and power models.The Level-2 setup also uses correlated Rayleigh block fading, linear detection, and hard QAM decisions; the experiments expose working regions but do not certify a radio implementation.Source: C. Evidence Limitations · p. 13
• Next steps include adding LDPC/Polar coding and soft outputs, using synthesis- or measurement-backed power models, and validating switching, negotiation, and rollback on an SDR hardware-in-the-loop platform.The plans also include calibrating synchronization, EVM, and spectral masks and generating dual-endpoint implementations; foundation-model proposers may expand the candidate library while executable gates retain deployment authority.Source: C. Evidence Limitations · p. 13

IX. CONCLUSION

• The fabric treats algorithms as explicit, versioned, verifiable runtime objects, with modification scale matched to a validation and deployment boundary.Level-1 experiments demonstrated parameter adaptation, Level 2 condition-dependent solver switching, and Level 3 waveform and multiple-access switching regions.Source: §IX · p. 13

APPENDIX A EXECUTION BUDGETS AND REPRODUCIBILITY

• The reproducibility settings specify seeds and evaluation budgets for all three levels, including four repetitions per Level-1 candidate and 700 common-random-number channel blocks per formal Level-2 scenario.The appendix also lists frozen result artifacts and executable entry points.Source: Appendix A · p. 13

APPENDIX B COMPLETE LEVEL-1 CANDIDATE EVIDENCE

• Level 1 selects the highest-utility candidate among those passing reliability and complexity gates, so a cheaper or higher-rate candidate is ineligible if reliability fails.Table IX reports all Level-1 candidates, with rate in MB/s, latency in ms, and energy in nJ/bit.Source: Appendix B · p. 13, Table IX · p. 14

APPENDIX C COMPLETE LEVEL-2 SOLVER EVIDENCE

• Level 2 removes infeasible candidates before applying scenario weights to the remaining quality–cost tradeoff; direct solution is not automatically selected whenever feasible.The table retains the 24 common-random-number evaluations used by the slow-timescale policy, with r95, divergence rate, energy, and latency defined in its caption.Source: Appendix C · p. 13, Table X · p. 14

APPENDIX D COMPLETE LEVEL-3 WAVEFORM EVIDENCE

• Level 3 evaluates each executable waveform tool in every formal scene, and failed high-mobility or overloaded orthogonal links should be read as failure indicators, not hardware predictions.A row is infeasible if it violates a reliability, ACLR, latency, power, or complexity gate.Source: Appendix D · p. 14