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A Time-Encoded Analog Photonic Interposer for Energy-EfficientIntegration of Analog Vision Sensors and Analog Accelerators
Subhradip Chakraborty, Zihan Yin, Xuming Chen, Chengwei Zhou, Gourav Datta, Akhilesh Jaiswal
TL;DR
Electrical links and prior photonic interposers do not provide a suitable way to transport analog activations across separated chiplets while preserving analog information. The paper converts analog amplitudes into timing intervals for WDM photonic transmission and reconstructs them at the receiver without an explicit high-precision ADC/DAC pipeline. The analog vision evaluation reports a 2.04× EDP improvement over electrical interconnects for long-distance communication.
Problem
Electrical interposers often require ADC/DAC conversion, while prior photonic interposers support digital data transfer and are unsuitable for analog signals.
Source: §1 · p. 1Method
The interposer uses analog-to-time conversion to send amplitudes as timing intervals over WDM optical channels and reconstruct analog voltages at the receiver.
Source: §1 · p. 1Results
2.04× EDP improvement over electrical interconnects for long-distance communication is reported for the analog vision pipeline.
Source: §1 · p. 2Takeaways & Limitations
The link embeds implicit 6-bit quantization while using a single wavelength per processing element independent of bit precision.
Source: §5 · p. 6
Abstract
from arXiv · showhide
This work introduces a time-encoded analog photonic interposer that enables long-distance, high-fidelity transport of analog signals between spatially separated chiplets. Unlike prior silicon-photonic links limited to digital data, the interposer preserves analog information by converting amplitudes into timing intervals using an analog-to-time converter (ATC), transmitting them over a wavelength-division-multiplexed photonic link, and reconstructing values at the receiver without an explicit high-precision ADC/DAC data-converter pipeline. The link instead embeds an implicit 6-bit time-domain quantization and uses a single wavelength per processing element independent of bit precision. Evaluated in a fully analog vision pipeline with an in-pixel computing (IPC) sensor, it achieves a 2.04x energy--delay product (EDP) improvement over an 8-bit digital electrical baseline on the 560x560 Visual Wake Words dataset, with the advantage widening with link length even against a precision-matched 6-bit baseline. The pipeline holds 89.87% and 86.15% accuracy on ResNet18 and MobileNetV2 for VWW and generalizes across CIFAR-10 and ModelNet40 within 2% of the digital baseline.
1 Introduction
Electrical links and prior photonic interposers leave a gap in transporting analog activations across chiplets while preserving analog information. The paper proposes a time-encoded photonic interposer and demonstrates it in an analog vision pipeline.
1 Introduction
- Electrical interposers often require ADC/DAC conversion, while prior optical interposers support digital transfer and are unsuitable for analog signals.Electrical signaling also faces resistive loss, capacitive loading, and bandwidth limits as communication distance grows.Source: §1 · p. 1
- The interposer maps analog voltages to timing intervals for WDM optical transmission, then reconstructs analog voltages without an explicit high-precision ADC/DAC pipeline.Time-domain encoding maps information to timing rather than amplitude to address MRR limitations.Source: §1 · p. 1
- 2.04× EDP improvement over electrical interconnects for long-distance communication is reported for the analog sensor-to-processor path.The evaluated pipeline uses an IPC front-end and analog accelerator on the 560×560 VWW dataset.Source: §1 · p. 2
2 Computing Preliminaries
The preliminaries describe IGZO gain cells as compact analog buffers for stored activations and explain MRR tuning and the motivation for time-domain encoding.
2.1 IGZO Based Gain Cell
- IGZO devices provide high resistance and low leakage for long retention, supporting dense analog memory that buffers activations during photonic transmission.The design uses this behavior for the 560×560 VWW configuration.Source: §2.1 · p. 2
2.2 Micro Ring Resonator (MRR) & Thermal Calibration
- Resonance shifts from mismatch, process variation, and thermal drift require closed-loop calibration using drop-port photodiode sensing and DAC-driven thermal tuning.Figure 3 depicts the MRR, thermal calibration circuit, and through-port transmission spectrum.Source: §2.2 · p. 2, Figure 3 · p. 2
- PN bias tunes MRR through-port power, but shrinking high-bias margins make direct analog transmission difficult; two-level time encoding preserves margin and avoids high-voltage interfacing.Figure 4 reports measured through-port output response against different PN voltages.Source: §2.2 · p. 2, Figure 4 · p. 2
3 Proposed Architecture
The proposed architecture couples an in-pixel computing sensor to an analog accelerator through a time-encoded photonic interposer. It transports first-layer analog activations between chiplets without a conventional high-precision ADC/DAC pipeline.
3.1 Overview
- The IPC front-end, photonic interposer, and analog accelerator form a sensor-to-processor pipeline that transfers first-layer analog activations without a conventional ADC/DAC pipeline.The IPC computes the first convolution, while the accelerator executes the remaining layers.Source: §3.1 · pp. 2–3
3.2 In-Pixel Computing Sensor
- The IPC pixel array computes the first convolution in analog form; two exposure cycles and CDS subtraction produce signed outputs.Cu–Cu bonded pixels multiply fixed weights, and column outputs accumulate before the activations are forwarded to the ATC.Source: §3.2 · p. 3
3.3 Analog Photonic Interposer
- The IPC sends first-layer analog outputs serially through the optical interposer using an ATC to represent voltage as a timing signal.An optical link is used because an electrical link would add latency and offset that corrupt the timing.Source: §3.3.1 · p. 3
3.3.1 Transmitter Design.
- A 6-bit ramp and comparator encode each input voltage as a timing edge that drives the microring modulator for optical transmission.When the ramp exceeds the IPC voltage, the comparator output switches and, after an inverter, drives the MRR control voltage.Source: §3.3.1 · p. 3
3.3.2 Receiver Design.
- At each accelerator PE, the optical receiver uses photodetection and thresholding to enable a ramp that stops and samples an analog value when the signal ends.The link has implicit 6-bit time-domain quantization and uses one wavelength per PE independent of precision.Source: §3.3.2 · p. 3, §3.3.3 · p. 3
3.4 Mapping of a neural network
- The weight-stationary accelerator streams activations over one wavelength per PE and accumulates products locally; wavelength count scales with K×K kernel size, not precision.For the second layer, PE assignments map to kernel coefficients and wavelengths; deeper-layer activations are generated and processed within the accelerator.Source: §3.4 · pp. 3–4, Figure 7 · p. 4
4 Results and Discussion
The photonic link shows energy–delay advantages over electrical baselines, including a widening advantage over a precision-matched 6-bit link as distance grows. Across the evaluated workloads, the analog pipeline keeps accuracy degradation below 2%.
4.1.1 Design Analysis.
- A 1,000-sample Monte Carlo analysis found minimal RX-voltage deviation for a 450 mV input; the link uses up to nine wavelengths within the MRR free spectral range.The text identifies process variation, device mismatch, and thermal drift as reasons calibration is needed to preserve recovered pulse timing.Source: §4.1.1 · pp. 4–5
- The 6-bit ATC takes 64 cycles (64 ns), setting the per-wavelength rate at 15.6 MS/s and the nine-wavelength aggregate at approximately 140 MS/s; thermal calibration adds about 1 pJ per value.That calibration overhead is about 15% of link energy, and between frames clock gating reduces idle power to the calibration overhead.Source: §4.1.1 · p. 5
4.1 Hardware Performance
- For the K=5 configuration at L=10 mm, total energy is 1.16 µJ, dominated by the interconnect; interconnect latency is about 64.5 ns versus a 10 µs IPC compute cycle.In rolling-shutter mode, interconnect latency is pipelined with P2M latency; its advantage appears only beyond 30 mm, where the electrical link begins to dominate latency.Source: §4.1.2 · p. 5
4.1.2 Energy and Latency.
- 2.04× EDP improvement at L=10 mm in global-shutter mode over the 8-bit electrical baseline; versus a 6-bit baseline, the advantage grows from 1.31× at 10 mm to 10.07× at 25 mm.The 6-bit comparison excludes serializer/deserializer overhead for a practical bit-parallel electrical link.Source: §4.1.2 · pp. 5–6, Table 1 · p. 6, Table 2 · p. 6
4.2.1 Non-Linearity and Noise Modeling.
- Injected hardware non-idealities include IPC-array and interposer (TX/RX) non-linearity; total front-end noise, including transmission offsets, is approximately 14.41%, while deeper layers assume 0.6% noise, consistent with.Source: §4.2.1 · p. 6
4.2.2 Accuracy Analysis.
- The full IPC + interposer system keeps worst-case accuracy degradation below 2% across VWW, CIFAR-10, and ModelNet40 for ResNet-18 and MobileNetV2.On VWW, the reported degradations are 1.77% and 1.01%; the comparison uses a 224×224 digital baseline input to match activations after the stride-2 first layer.Source: §4.2.2 · p. 6, Table 3 · p. 6
5 Conclusion
The paper presents a time-encoded analog photonic interposer that transports analog signals between chiplets without an explicit high-precision ADC/DAC pipeline. In an analog vision pipeline, it improves EDP over an 8-bit digital electrical link while keeping accuracy within 2% across three workloads.
5 Conclusion
- The interposer converts analog amplitudes into timing intervals for WDM transmission, embedding implicit 6-bit quantization without an explicit high-precision ADC/DAC pipeline.It uses a single wavelength per processing element independent of bit precision.Source: §5 · p. 6
- The analog vision pipeline improves EDP by 2.04× over an 8-bit digital electrical link, with the advantage widening with link length even against a precision-matched 6-bit baseline.Accuracy remains within 2% of the digital baseline across VWW, CIFAR-10, and ModelNet40 for ResNet18 and MobileNetV2.Source: §5 · p. 6