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Confidence-Gated Admission for Hardware Prefetching: When the Gate Matters More Than the Predictor

Youssef Majdane, Simone Jarno Casartelli, Enrico Lopedoto

arXiv:2609.04040v2cs.ARcs.PF

TL;DR

Learned-prefetcher evaluations can confound prediction with admission when gated learned predictors are compared against always-on classical units. The paper applies the same gate to an MLP and stride predictor, and reports that proxy improvements in its SPEC CPU2017 study do not translate to endpoint gains.

  • Problem

    Comparisons between gated learned prefetchers and always-on classical predictors confound prediction quality with admission policy.

    Source: §I · p. 1

  • Method

    The paper uses matched controls, applying the same admission gate to a learned MLP and a classical stride predictor.

    Source: §I · p. 1, E. Matched Classical Controls · p. 3

  • Results

    A 35% prefetch reduction yielded only 0.07% fewer DRAM reads in the twenty-program ChampSim study.

    Source: §X · p. 8

  • Takeaways & Limitations

    Proxy improvements such as fewer prefetches and higher accuracy must not substitute for endpoint validation.

    Source: §I · p. 1, §X · p. 8

    The local simulator models latencies rather than real silicon, so its results reflect modeled behavior.

    Source: §IX · p. 7

Abstract

from arXiv · show

Learned cache prefetchers are typically evaluated against classical predictors that always issue requests, confounding the prediction model with the admission policy. We disentangle these variables with matched controls: the same admission gate is applied to both a 257-parameter online MLP and a classical stride predictor. The neural advantage vanishes; the MLP is indistinguishable from gated stride on random traffic and slower on most regular streams. The gate itself is architecturally useful independent of the predictor: on twenty SPEC CPU2017 programs in native ChampSim, it removes 35% of prefetches and improves accuracy from 11% to 15%, but DRAM reads change by only 0.07% demonstrating that proxy metrics do not predict endpoint behavior. We prove gate-closed execution reproduces the no-prefetch baseline exactly. The gate matters more than the predictor, and better proxies do not imply better endpoints.

I. Introduction

Classical prefetchers handle regular streams well, while learned systems target irregular patterns. Because evaluations often compare gated learned predictors with always-on classical units, the paper uses matched controls to separate prediction from admission.

A. Classical Hardware Prefetching

  • Classical prefetchers perform well on sequential, strided, and within-stream gather traffic, but can be fragile when their assumptions break.The toolbox includes next-line, stride, signature-path, best-offset, and Bingo prefetchers.Source: §I · p. 1, A. Classical Hardware Prefetching · p. 2

B. Learned Prefetching

  • Neural prefetchers have explored online reinforcement learning, address segmentation, irregular-pattern learning, and hardware-practical inference.Examples include Pythia, TransFetch, Hashemi et al., DART, and Pathfinder.Source: §I · p. 1, B. Learned Prefetching · p. 2

I. Introduction

  • The paper identifies a confound: comparing gated learned predictors with always-on classical units mixes prediction quality with admission policy.Its matched-control design applies the same gates to an MLP and a stride predictor.Source: §I · p. 1

C. LLM Inference Memory Optimization

  • LLM inference motivates the study because its memory traffic combines sequential KV-cache appends with far attention gathers.The introduction also points to retrieval agents alternating context scans and scattered lookups, and embeddings accessed through sparse indices.Source: §I · p. 1, C. LLM Inference Memory Optimization · p. 2

B. Learned Prefetching

  • The paper’s methodological distinction is applying matched admission policies to learned and classical predictors before attributing performance differences to the model.It also introduces and verifies a safety property, then finds that the property belongs to the gate rather than the network.Source: §I · p. 1, B. Learned Prefetching · p. 2

D. Safety and Confidence in Prefetching

The paper situates its confidence gate within predict-then-verify approaches and evaluates a delta-predicting MLP in a deterministic scalar-core simulator. The MLP has 257 parameters and predicts from a six-dimensional feature vector.

D. Safety and Confidence in Prefetching

  • The median-error gate is presented as a prefetching instance of predict-then-verify, with the gate’s value independent of the predictor behind it.The paper contrasts this with SPIBB, learned index structures with B-tree fallback, and PPF, whose confidence gate on SPP yields 3.78% IPC improvement.Source: D. Safety and Confidence in Prefetching · p. 2

A. Simulator Model

  • The simulator uses a deterministic in-order scalar core with latency-accounting, a default 32-line L1, and 40-cycle miss stalls.The matched-control falsification uses a timed 8-way configuration; prefetch insertion is modeled at zero cycle cost.Source: A. Simulator Model · p. 2

B. Delta Encoding and MLP Predictor

  • The predictor estimates the next address delta from a six-dimensional feature vector using a 6–32–1 ReLU MLP with 257 parameters.It trains from a replay buffer of up to 64 samples every 16 samples, with targets and predictions clamped to ±16 words.Source: B. Delta Encoding and MLP Predictor · p. 2

C. Confidence Gate

The confidence gate uses recent prediction errors to decide whether the MLP’s proposed delta should trigger a prefetch. Its median-error mechanism stays closed on unlearnable streams, but its hardware cost limits it to simulation-level use.

C. Confidence Gate

  • The gate evaluates a window of recent absolute prediction errors to decide whether the current prediction is trustworthy enough to act on.The decision path accepts the MLP’s proposed delta as a prefetch or falls back to no-op.Source: C. Confidence Gate · p. 2, Figure 1 · p. 3
  • The per-access algorithm updates the replay buffer and error window, then either prefetches at the predicted address or issues no-op.The listed configuration uses a replay buffer of at most 64 samples and a gate window W=48.Source: C. Confidence Gate · p. 3
  • On unlearnable streams, high median error keeps the gate closed; on learnable streams, error drops and the gate opens.When traffic changes phase, the error window adapts within W accesses.Source: C. Confidence Gate · p. 3
  • The confidence gate requires a running median over a 48-entry error window, making it practical only as a simulation-level instrument.The paper identifies a sorted insertion buffer or approximate median network as typical hardware implementations, and cites the MLP’s ≈26 μs NumPy inference latency.Source: C. Confidence Gate · p. 3

D. Regularity Gate

The regularity gate admits based on dominant-delta support, while matched controls apply the same admission policy to an MLP and stride predictor. The safety theorem states that suppressing every prefetch reproduces baseline execution exactly.

D. Regularity Gate

  • After eight deltas, the regularity gate admits only when R_t ≥ 0.35 for W_r=16.The window and threshold were selected on development seeds 0–9; confirmatory results use disjoint seeds 10–39.Source: D. Regularity Gate · p. 3
  • An exact incremental regularity-gate implementation uses 2,153 state bits, or 269.1 bytes, while comparator and update logic are not costed.The accounting covers a 16-entry signed 64-bit FIFO and a 16-entry associative histogram.Source: D. Regularity Gate · p. 3

E. Matched Classical Controls

  • The matched-control design gives the MLP and stride predictor the same stream, gate parameters, and adaptation while closed, isolating the prediction model as the differing variable.This removes the admission confound when comparing their performance.Source: E. Matched Classical Controls · p. 3

A. Gate-Closed Safety (Theorem 1)

  • If the confidence gate suppresses every prefetch, gated and baseline executions have identical cycles for the same workload and seed.The proof proceeds by induction: without prefetch insertions, cache state and hit/miss outcomes remain in lock-step.Source: A. Gate-Closed Safety (Theorem 1) · p. 3

B. Scope and Limits

Gate-closed execution exactly reproduces the no-prefetch baseline, but this safety guarantee does not promise the performance of classical prefetchers. The evaluation spans synthetic, ML/agent, and real-algorithm workloads using paired-seed comparisons.

B. Scope and Limits

  • Gate-closed execution equals the no-prefetch baseline, but the theorem guarantees neither optimal classical-prefetch performance nor useful prefetching when the gate stays closed.The theorem is structural; its empirical question is whether the gate closes on unlearnable streams.Source: B. Scope and Limits · pp. 3–4

A. Workloads

  • The workload set includes deterministic synthetic streams, ML/agent patterns, and element-by-element traces from real algorithms.Synthetic cases include predictable, noisy, and phase-switching traffic; ML/agent cases include KV-cache appends, embedding lookups, and retrieval patterns.Source: A. Workloads · p. 4

B. Statistical Methodology

  • Configurations are compared across independent seeds using speedup, L1 hit rate, and paired Wilcoxon tests; matched controls also use paired cycle ratios and Holm-corrected sign tests.Synthetic workloads use 30 seeds; ML/agent patterns and real traces use 8.Source: B. Statistical Methodology · p. 4

C. Machine Configuration Sweep

The NN matches baseline on random traffic across the tested machine settings, while stride falls below baseline; the gate can also suppress useful prefetching on learnable traffic. The native ChampSim evaluation protocol and workload selection define a separate validation scope.

C. Machine Configuration Sweep

  • Across tested L1 capacities, line sizes, and DRAM latencies, NN matches baseline on random while stride falls below baseline in every configuration.The sweep covers L1 capacities of 16–64 lines, line sizes of 4–16 words, and DRAM latencies of 20–80 cycles.Source: C. Machine Configuration Sweep · p. 4

D. ChampSim Evaluation Protocol

  • Native ChampSim tests the regularity gate on stride across twenty SPEC CPU2017 programs, using one highest-weight SimPoint per program and a nine-program holdout.The confidence gate is evaluated only in the local simulator; the native study uses one ChampSim configuration and compares gated with raw stride.Source: D. ChampSim Evaluation Protocol · p. 4

A. Gate-Closed Safety on Unlearnable Streams

  • On random_read, the gated NN achieves 1.000× while stride achieves 0.98×; on mixed_rw, the NN achieves 1.003× while stride reaches 8.69×.The random_read comparison is reported over 30 seeds; the mixed_rw result illustrates the gate’s conservatism.Source: Table I · p. 4, A. Gate-Closed Safety on Unlearnable… · p. 4

B. Phase Switching Recovery

With matched admission, the broad neural advantage disappears: the MLP is indistinguishable from gated stride on random traffic and slower on most workloads. Phase switching, workload comparisons, and ablations show where gating and model design affect outcomes.

B. Phase Switching Recovery

  • On phased_switch, the NN reaches 1.10× versus stride’s 1.09× overall, with the NN matching baseline hit rate in noisy phases while stride falls below it.The reported aggregate edge is small but significant (Wilcoxon p < 0.001).Source: B. Phase Switching Recovery · p. 5

C. ML/Agent Patterns

  • On real_matmul and real_mergesort, the ±16-word clamp prevents representing a 32-word row stride, so the gate suppresses unreliable prefetches.The passage identifies classical mechanisms as the right tool for dense, large-stride, regular compute.Source: C. ML/Agent Patterns · p. 5

D. Feature Ablation and Gate Design

  • Removing the absolute address raises strided-read speedup from 8.3× to 17.0×; median error gating and ±16-word training-delta clamping improve gather-heavy streams without regression on random or smooth streams.Reported gains include embedding 1.00→1.64×, KV-cache 1.00→1.33×, and agent-RAG 1.84→1.95×.Source: D. Feature Ablation and Gate Design · p. 5, Table III · p. 5

E. Matched-Control Falsification

  • With the same regularity gate, the MLP is statistically indistinguishable from stride on random traffic and significantly slower on six of eight workloads.Its sole reported win is KV-cache append (B = 1.101); matched admission attributes performance differences to the predictor rather than the admission decision.Source: E. Matched-Control Falsification · p. 5

VII. Results: Native ChampSim Validation

The native ChampSim study confirms exact equivalence between the gate-disabled module and official stride, then finds that gated stride reduces prefetches and improves accuracy with almost no change in DRAM reads. Across programs, its performance direction is more consistent than raw stride’s, but it does not improve aggregate IPC over raw stride.

A. Correctness Invariant

  • The gate-disabled module matches official ChampSim ip_stride on every recorded output field across all twenty programs, with a paired IPC ratio of exactly 1 and twenty ties.This establishes that the gate comparison is not an accidental reimplementation artifact.Source: A. Correctness Invariant · p. 5

B. Gate Performance

  • 35.1% fewer accepted L1D prefetches and 4.4 percentage points higher accuracy accompany only 0.07% fewer DRAM reads across twenty programs.The gate retains 90.3% of useful prefetches; gated stride achieves 1.040× no-prefetch IPC (p=0.004), versus 1.044× for raw stride (p=0.096).Source: Table V · p. 6, B. Gate Performance · p. 6

C. Per-Program Analysis

  • Against the no-prefetch baseline, gated stride yields 1.040× (p=0.004; 14 wins, 2 losses, 4 ties), versus raw stride’s 1.044× (p=0.096; 13 wins, 5 losses, 2 ties).GCC and MCF lose 4.37% and 2.92%, respectively; across twenty programs, the gate has seven wins, eleven losses, and two ties (exact sign-test p=0.481, not significant).Source: C. Per-Program Analysis · p. 6

D. Interpretation: Proxy ≠Endpoint

The results distinguish admission effects from predictor effects and show that improved prefetch proxies do not establish better endpoint outcomes. The gate can improve consistency, but its benefits vary by workload and do not make the MLP competitive with stride on most learnable streams.

D. Interpretation: Proxy ≠Endpoint

  • A 35% reduction in issued prefetches yields only 0.07% fewer DRAM reads, and improved accuracy does not establish lower off-chip traffic or higher performance.Most suppressed prefetches either do not descend the hierarchy or return later as demand reads.Source: D. Interpretation: Proxy ≠Endpoint · p. 6

A. The Gate Matters More Than the Predictor

  • With matched admission, the MLP's apparent safety advantage on random traffic vanishes, while it remains slower than stride on most learnable streams.The gate suppresses a third of prefetches and improves accuracy, but its proxy-metric gains do not reliably translate to endpoint gains.Source: A. The Gate Matters More Than the… · p. 6

B. The Dense-Compute Limitation

  • The MLP's ±16-word replay buffer cannot represent a 32-word stride, so a stride-aware bypass is proposed for stable large strides.Classical prefetchers recognize the fixed stride, while the gate suppresses the MLP's unreliable predictions.Source: B. The Dense-Compute Limitation · pp. 6–7

C. When Admission Control Helps vs. Hurts

  • Gated stride wins against no-prefetch on 14 of 20 programs (p=0.004), versus 13 for raw stride (p=0.096), but its aggregate IPC cost is 0.42%.Admission control is not universally beneficial: at ideal lookahead D=1 it slows agent RAG by 1.30% and one deterministic merge-sort trace by 5.95%.Source: C. When Admission Control Helps vs.… · p. 7

D. Implications for LLM Inference Prefetching

Mixed-phase LLM inference is a promising target because a gate could distinguish predictable KV-cache appends from irregular attention gathers, but the local result is not validated on native LLM traces. The paper also identifies simulator, workload, model, and measurement boundaries on how broadly to interpret its findings.

D. Implications for LLM Inference Prefetching

  • Mixed-phase LLM inference combines sequential KV-cache appends with irregular attention gathers; locally, gated NN reaches 1.33× on appends and 1.000× on random traffic.The proposed gate opens on predictable appends and closes on irregular gathers to avoid pollution without sacrificing sequential benefit.Source: D. Implications for LLM Inference… · p. 7
  • SPEC CPU2017 lacks the motivating mixed-phase structure, so the gate's benefit did not materialize as endpoint improvement there; native or RTL-level LLM-trace validation remains needed.The paper identifies real LLM inference traces as the critical next validation step.Source: D. Implications for LLM Inference… · p. 7

IX. Threats to Validity

  • Local results reflect modeled latencies in a deterministic scalar simulator, not real silicon; testing machine parameters and external ChampSim validation mitigate but do not remove this abstraction boundary.The study uses speedup and L1 hit rate as local proxies, and does not capture energy, bandwidth waste, or multi-tenant interference.Source: §IX · p. 7
  • The native study covers one highest-weight SimPoint per program, one ChampSim configuration, and no multicore interference; it does not externally replicate the MLP-versus-stride matched control.The authors caution against extrapolating the local matched-control finding to the native setting without that validation.Source: §IX · p. 7
  • The matched-control result concerns a 257-parameter online delta-regressor and gates only stride, leaving larger pretrained models and other gated classical predictors untested.Whether larger models change the MLP-versus-gated-stride comparison remains open.Source: §IX · p. 7
  • The authors report no Bonferroni correction for local comparisons, while ChampSim callback counts can differ by up to 0.105% because requests remain in flight at phase changes.They state primary local p-values survive Bonferroni correction and treat exact raw/official endpoint equivalence as the hard invariant.Source: §IX · p. 7

X. Conclusion

The conclusion argues that matched controls attribute the neural advantage on random traffic to admission policy, while the gate’s prefetch reduction barely changes DRAM reads. It presents improved gating and validation on LLM inference traces as next steps.

X. Conclusion

  • The neural advantage on random traffic is an admission-policy effect, so future evaluations should use matched controls before attributing performance to the model.The conclusion frames matched controls as isolating prediction from admission.Source: §X · pp. 7–8
  • A 35% prefetch reduction (60% median) yields only 0.07% fewer DRAM reads in the twenty-program ChampSim study.The conclusion cautions that proxy improvements must not substitute for endpoint validation.Source: §X · p. 8
  • 14/20 programs beat no-prefetch (p=0.004) versus 13/20 for raw stride (p=0.096), but the direct comparison is not significant (IPC ratio 0.996, p=0.481).The authors describe the win/loss split as suggestive of improved consistency, not an independently established effect.Source: §X · p. 8
  • The proposed path forward is a better gate for dense large-stride patterns and workload phases, validated on LLM inference traces with RTL-level energy characterization.Source: §X · p. 8
  • The local pure-NumPy MLP achieves statistically identical hit rates to the scikit-learn reference, and native metadata records revision and artifact hashes.The code, data, and verification scripts are publicly available.Source: Reproducibility Statement · p. 8
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