Source-linked AI summary
Hardware-conscious Software Training for Deep Neural Network Inference Accelerator Chips to Recover Accuracy Degradation due to Hardware Variabilities
Shuchao Gao, Takashi Ohsawa
TL;DR
DNN inference accelerators can lose accuracy because manufacturing-induced hardware variations affect their computations. The paper proposes HCST, which trains software using circuit parameters and chip-specific imperfections, and verifies with HSPICE that it recovers accuracy degradation caused by those variations.
Problem
Manufacturing-induced hardware variations lower DNN inference-accelerator accuracy relative to software, motivating training that accounts for those imperfections.
Method
HCST trains a hardware emulator with circuit parameters, op-amp gains, and chip-specific offset voltages before deploying updated conductances to the synapse array.
Results
HSPICE verifies that HCST is effective for recovering accuracy degradation caused by hardware variations in DNN inference accelerators.
Takeaways & Limitations
HCST enables software training that accounts for hardware variations while avoiding memory-device endurance, nonlinearity, and asymmetry constraints during updates.
Abstract
from arXiv · showhide
Deep neural network (DNN) has been widely applied in various industries. Specialized chips are being discussed for the purpose of achieving lower power consumption with higher throughput. Hardware variations introduced during the process of chip manufacturing are the main reason for affecting the inference accuracies. In this paper, we propose hardware-conscious software training (HCST) method which enables high inference accuracies even under the influence of hardware variations.
1. Introduction
Offline-trained DNN inference accelerators lose accuracy relative to software because of unavoidable hardware variability. HCST incorporates those variations during software training to compensate for degradation without the endurance, nonlinearity, and asymmetry constraints of memory-device updates.
- Offline-trained DNN inference accelerators have lower accuracy than corresponding software models because of inevitable hardware variability.
- HCST incorporates hardware variations such as op-amp offset voltages into software training to compensate for accuracy degradation.
- Unlike on-chip and in-situ training, the proposed software training leaves memory devices free from endurance, nonlinearity, and asymmetry constraints during resistance updates.
2. Hardware-conscious software training (HCST)
HCST trains a hardware emulator using circuit parameters and chip-specific op-amp imperfections. The resulting individual training accounts for measured or assigned offset-voltage variations across chips.
- HCST uses voltage, current, and conductance parameters together with op-amp finite open-loop gains and offset voltages.
- Each chip receives individual training because its op-amp offset voltages are set to fluctuated values measured from that chip.
- The crossbar represents each weight with a pair of ReRAM devices, and subtracts converted bit-line currents to realize positive or negative weights.
- The accelerator circuits include IV-converters, subtractors, ReLU, and voltage followers whose op-amps have offset voltages and finite gains, except ReLU.
- HCST assigns op-amp offset voltages chip by chip using variation estimates and completes training in a hardware emulator before deployment.
3. Training program including hardware variations
The hardware emulator models op-amp gain and offset effects during forward and backward propagation, then deploys the updated conductances to the synapse array subject to ReRAM restrictions.
- The hardware emulator includes each op-amp’s gain and offset voltage in both forward and backward propagation.Backward-path unit errors are derived according to the chain rule in the neuron circuits.
- Updated conductances are deployed to both synapse-array conductances according to their sign.
- ReRAM conductances are constrained by device restrictions during deployment.
- ReRAM without electroforming can serve as a zero-conductance device.
4. Application to IRIS dataset
On the IRIS dataset, the hardware emulator matches the HSPICE baseline without offset voltages, while experiments compare offline training and HCST across ten chips with hardware variations.
- 97.33% is the baseline accuracy for the 4 × 5 × 3 network trained in the hardware emulator without offset voltages.This matches the HSPICE result for the IRIS dataset.
- Accuracy is evaluated across 10 chips for baseline, offline training, and HCST under hardware variations.The comparison is shown for both the hardware emulator and HSPICE.
5. Conclusion
HSPICE verification found that hardware-conscious software training (HCST) recovers accuracy degradation caused by hardware variabilities in DNN inference accelerators.
- HSPICE verified that HCST is effective for recovering accuracy degradation due to hardware variabilities in DNN inference accelerators.