TETRIS-Q: Tiling-based Effective Transient-fault Reduction on Interleaved Superconducting Qubits

Motivation

• Radiation-induced faults can create spatio-temporally correlated defects that are sufficient to induce QEC failure.The paper highlights this as an under-discussed challenge for superconducting quantum computers.Source: §I · p. 1

Approach

• TETRIS-Q subdivides a planar-mesh qubit topology into periodic, parametrizable, adjacent tiles for modular barrier placement and QEC interleaving.The method is designed to extend across quantum chips of different sizes.Source: §I · p. 1
• Substrate-level phonon barriers are modelled with permeability factors that partly limit radiation-induced quasiparticle dispersion to defined chip regions.The simulations investigate how barrier placement and permeability affect QEC resilience.Source: §I · p. 1
• QEC interleaving increases the physical distance between virtually close qubits while maintaining the same total number of embedded logical qubits.This provides a software-level complement to substrate barrier placement.Source: §I · p. 2

Research aims

• Combining barriers and interleaving reduces simulated radiation-induced faults below the intrinsic noise floor while optimizing barrier implementation cost.The study frames this as a joint reliability-and-cost optimization problem.Source: §I · p. 2

Research questions

• The study asks how barriers affect radiation tolerance, which barrier sizes and positions preserve QEC operativity, whether barriers improve QEC thresholds, and how interleaving contributes.A final question concerns the reliability gains from using barriers and interleaving together.Source: §I · p. 2

Radiation events

• Radiation events are a comparatively recent and less populated reliability concern for superconducting quantum computers.The background contrasts this literature with the larger body of radiation-reliability work for traditional electronics.Source: A. Radiation events in quantum devices · p. 2
• Without substrate barriers, quasiparticles can disperse throughout the quantum chip and cause correlated faults.The figure presents this as the unconfined-dispersion case.Source: Figure 1 · p. 2
• Radiation-induced events can produce whole-chip correlated errors with reported frequencies ranging from once per hour to multiple times per minute.The passage also indicates that these effects persist transiently, though the supplied text does not provide the full duration range.Source: A. Radiation events in quantum devices · p. 2

Quantum error correction

• QEC detects and corrects errors through indirect joint-parity measurements using data and stabilizer qubits.The paper uses this QEC structure as the algorithm-level context for radiation hardening.Source: B. Quantum Error Correction… · p. 2

Cross-layer hardening

• The cross-layer approach combines substrate barriers, which limit correlated radiation faults, with interleaving, which increases physical distance between virtually close qubits.These mechanisms address the same radiation problem at hardware and QEC-organization levels.Source: B. Quantum Error Correction… · p. 3

Quantum error correction

• The rotated surface code is selected because its planar degree-≤4 connectivity suits current hardware and supports efficient graphlike-error decoding.Minimum weight perfect matching is cited as an example of an efficient decoder.Source: B. Quantum Error Correction… · p. 3

Phonon barriers

• Substrate-level phonon barriers are hardware-level structures intended to limit radiation byproduct spreading and simultaneous correlated qubit faults.The study evaluates placement and enclosure size rather than a specific physical barrier implementation.Source: D. Main contribution · p. 3
• Barrier permeability controls quasiparticle passage, with bp = 1 representing no flux reduction and bp = 0 representing an ideal barrier.The paper models lower permeability as requiring greater implementation width and cost.Source: D. Main contribution · p. 3

Tiling cost

• The barrier cost is multiplied by the total length of traces required to tile the full quantum-chip topology.This links local barrier implementation cost to the global tiling pattern.Source: D. Main contribution · p. 3

Tiling strategy

• Tiling groups spatially close qubits into exclusive regions where quasiparticles can propagate more readily within a tile than across adjacent tiles.A size-1 tile encloses one contiguous qubit region, and tiling can use variable tile sizes across the chip topology.Source: D. Main contribution · pp. 3–4

Simulation model

• The model uses square-lattice connectivity for a superconducting quantum chip containing 1741 qubits.The total qubit count is not required for every simulation because many experiments use only a portion of the chip.Source: §III · p. 4

• The SI1000 model appends randomized Pauli noise after each quantum gate, triggered during syndrome sampling with probability p.Source: A. Intrinsic noise model · p. 4
• Radiation events are modeled as spatio-temporally correlated reductions in qubit coherence time τ1.Source: B. Radiation fault model · p. 4
• Correlated radiation faults are represented by injecting Y-ERROR operators during circuit execution according to a given probability.Source: B. Radiation fault model · p. 4
• The radiation-induced fault probability combines a time-dependent factor based on τrad(t) with a distance-dependent substrate-dissipation factor.Source: B. Radiation fault model · p. 4
• Faults are injected only within the radiation event’s duration window Δtrad.Source: B. Radiation fault model · p. 4

Tiling strategy

• TETRIS-Q starts from a square master tile and discovers remaining non-overlapping tiles by breadth-first search.Source: A. Tiling strategy · p. 4
• Adjacent tiles share at least one side, while outer graph portions may contain exceptional vertex assignments.Source: A. Tiling strategy · pp. 4–5

Barriers

• Barrier-tracing cost depends on tile size, shape, and placement; 4-qubit and 9-qubit tiles incur 47% and 61% costs, respectively.Source: Figure 4 · p. 5, B. Barriers · p. 5
• Each hypergraph vertex represents a tile, and hypergraph edges represent barriers shared with physically adjacent tiles.Source: B. Barriers · p. 5
• Barrier permeability bp controls damping, with bp = 1 meaning that barriers provide no damping.Source: B. Barriers · p. 5
• Barrier fabrication cost scales linearly with total barrier perimeter, computed after subtracting overlapping perimeter portions.Source: B. Barriers · p. 5

Interleaving

• Quantum circuit interleaving maps suitable quantum circuits onto a shared grid of qubits as a software-hardware co-design approach.Source: C. Interleaving · p. 5

Evaluation

• Figure 5 measures distance-9 rotated surface-code average logical error rate against qubits per tile and barrier permeability for different tiling positions.Source: Figure 5 · p. 6

Interleaving

• Independent QEC codes can be interleaved rather than assigned to non-overlapping chip regions, increasing physical separation between virtually close code qubits.Source: C. Interleaving · p. 6
• The hypergraph preserves spatial qubit ordering within tiles and supports shifting multiple circuit mappings among tile positions.Source: C. Interleaving · p. 6

• 4- and 9-qubit tiles require lower permeability to keep logical error rates below 1%, but comparable code-distance and tile-size combinations perform similarly at bp = 0.5.Source: A. Effect of barriers over time · p. 7
• Lower barrier permeability and smaller phonon barrier tiles reduce radiation-induced logical error peaks.Source: A. Effect of barriers over time · p. 7

• Less than 50% of QEC-code qubits must be enclosed by centered tiles for observable effects, regardless of barrier permeability.Source: B. Effect of tiling size and position · p. 8
• Non-centered tiling is more effective because each growing tile contains at most about 25% of the rotated surface code’s qubits.Source: B. Effect of tiling size and position · p. 8
• 10^-3 average logical error rate is reached with single-qubit tiles and bp = 0.01 in both centered and non-centered configurations.Source: B. Effect of tiling size and position · p. 8
• More than 75% implementation-cost reduction is achieved using non-centered tiles of at most 25 qubits at bp = 0.1 while reaching below 10^-2 average logical error rate.Source: B. Effect of tiling size and position · p. 8
• More than 87% cost reduction is possible with non-centered tiles of up to 225 qubits while approaching 10^-3 average logical error rate.Source: B. Effect of tiling size and position · p. 8
• Tiles containing up to 25% of a QEC code’s qubits are comparatively effective to single-qubit phonon barrier tiles.Source: B. Effect of tiling size and position · p. 8

• 10^-4 intrinsic noise intensity intersects the code-distance curves at 2.1×10^-1 with fully permeable barriers, bp = 1.Source: C. Effect of barrier permeability with… · p. 8
• A one-order-of-magnitude higher intrinsic noise rate yields crossing points between 1.8 × 10^-1 and 2.4 × 10^-1 at bp = 0.5.Source: C. Effect of barrier permeability with… · p. 9
• Phonon barrier tiling can preserve QEC codes’ characteristic efficiency threshold against intrinsic noise and guarantee radiation-fault tolerance.Source: C. Effect of barrier permeability with… · p. 9
• 48% implementation-cost reduction is obtained with 4-qubit tiles at bp = 0.01 while performing comparatively well against the single-qubit configuration.Source: C. Effect of barrier permeability with… · p. 9
• More than 60% cost saving is achieved with 9-qubit tiles and one-order-of-magnitude higher permeability for code distances 7, 9, and 11.Source: C. Effect of barrier permeability with… · p. 9
• A QEC code’s distance limits the efficacy of lower-permeability phonon barriers, regardless of intrinsic noise intensity.Source: C. Effect of barrier permeability with… · p. 9

• Positive interference between phonon barrier tiles and QEC interleaving further mitigates radiation-induced faults.Source: D. Effect of barriers and interleaving · p. 9
• More than 10% peak logical error-rate reduction and up to 40% earlier inflection occur with interleaving on 16-qubit tiles.Source: D. Effect of barriers and interleaving · p. 9
• The smallest 4-qubit tiling advances the second inflection point by about 20% versus 16-qubit tiling and about 40% versus non-interleaved 4-qubit tiling.Source: D. Effect of barriers and interleaving · pp. 9–10
• The best measured average logical error rate is 6.51×10^-4 with 14-qubit tiles and 8 interleaved codes.Source: E. Optimising barrier and interleaving… · p. 10
• Combining interleaving, larger-distance codes, and phonon barriers can reduce barrier cost while retaining comparable radiation-induced fault tolerance.Source: E. Optimising barrier and interleaving… · p. 10

• Substrate barriers group physical qubits into tiles and reduce radiation-deposited energy spreading without additional QEC-code overhead.Source: §VI · p. 10
• Lower barrier permeability reduces peak logical error rates toward the QEC code’s characteristic noise floor.Source: §VI · p. 10
• Tile sizes up to one quarter of a QEC code’s qubits can provide appreciable error-rate reduction, while tile positioning strongly affects barrier efficacy.Source: §VI · p. 10
• Barrier benefits correlate with lower intrinsic noise, but increasing QEC code distance does not improve the barriers’ intrinsic noise-error threshold.Source: §VI · p. 10
• Phonon barriers and interleaving show positive interference, limiting radiation-induced effects below the considered rotated surface codes’ thresholds.Source: §VI · p. 10
• Future analyses should investigate alternative tiling, hardware hardening, radiation-aware decoding, other QEC codes, lattice surgery, and super-stabiliser methods.Source: §VI · p. 10