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TETRIS-Q: Tiling-based Effective Transient-fault Reduction on Interleaved Superconducting Qubits

Marzio Vallero, Gioele Casagranda, Flavio Vella, Paolo Rech

arXiv:2609.05226v1quant-phcs.AR

TL;DR

Radiation-induced faults create correlated defects that remain insufficiently addressed by QEC in superconducting quantum devices. The paper combines substrate-level phonon barriers with QEC interleaving through the TETRIS-Q tiling algorithm and simulates varied configurations. It reports large logical-error reductions, shorter observable transients, and barrier-tracing cost reductions, while interleaving improves average logical error rates with or without barriers.

  • Problem

    Radiation-induced faults can create correlated qubit defects that jeopardize QEC effectiveness in superconducting quantum devices.

  • Method

    TETRIS-Q tiles the qubit topology to combine modular substrate-level phonon barriers with interleaving of independent QEC codes.

  • Results

    Up to 11% average logical error-rate reduction is achieved by interleaving 9 surface codes, while the best combined configuration reaches 6.51×10^-4 with 14-qubit tiles and 8 interleaved codes.

  • Takeaways & Limitations

    Tiles containing up to 25% of a QEC code’s qubits can achieve average logical error rates below 10^-2 at bp = 0.1 with more than 75% barrier-cost reduction.

Abstract

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The struggle of the hour in quantum computing research is achieving effective suppression of the error mechanisms induced by the interaction of external radiation with superconducting quantum devices. Despite the rapid advancements in quantum error correction (QEC) of recent years, radiation-induced faults are yet to be fully addressed. These events are known to be the cause of simultaneous correlated defects in qubits that lie onto a single substrate, ultimately jeopardising QEC code effectiveness. In this paper, we propose to selectively combine substrate-level phonon barriers and QEC interleaving via a planar-mesh tiling algorithm, TETRIS-Q, reaching efficient and effective suppression of radiation events. Our cross-layer solution comes at no extra cost in terms of QEC code execution or decoding time. We model and simulate radiation-induced transient faults over a plethora of barrier and QEC interleaving configurations. Through more than 51 million quantum circuit simulations, we show peak logical error reductions of more than $99.8 \%$, together with an $80\%$ reduction of the observable transient duration with permeable barriers. We find that sparser tiling can reach comparable performance to single qubit tiling, prompting cost reductions of upwards of $87 \%$ in barrier tracing. By leveraging independent QEC code interleaving, we measure up to one order of magnitude average logical error rate reductions without the use of permeable barriers, and up to three orders of magnitude with the joint usage of barriers.

I. INTRODUCTION

The paper addresses radiation-induced correlated faults, which remain insufficiently handled by QEC, by combining substrate barriers and QEC interleaving through TETRIS-Q. It investigates how these configurations can suppress faults while controlling implementation cost and preserving QEC operation.

  • Motivation: Radiation-induced faults can create spatio-temporally correlated defects that are sufficient to induce QEC failure.The paper highlights this as an under-discussed challenge for superconducting quantum computers.
  • Approach: TETRIS-Q subdivides a planar-mesh qubit topology into periodic, parametrizable, adjacent tiles for modular barrier placement and QEC interleaving.The method is designed to extend across quantum chips of different sizes.
  • Approach: Substrate-level phonon barriers are modelled with permeability factors that partly limit radiation-induced quasiparticle dispersion to defined chip regions.The simulations investigate how barrier placement and permeability affect QEC resilience.
  • Approach: QEC interleaving increases the physical distance between virtually close qubits while maintaining the same total number of embedded logical qubits.This provides a software-level complement to substrate barrier placement.
  • Research aims: Combining barriers and interleaving reduces simulated radiation-induced faults below the intrinsic noise floor while optimizing barrier implementation cost.The study frames this as a joint reliability-and-cost optimization problem.
  • Research questions: The study asks how barriers affect radiation tolerance, which barrier sizes and positions preserve QEC operativity, whether barriers improve QEC thresholds, and how interleaving contributes.A final question concerns the reliability gains from using barriers and interleaving together.

II. BACKGROUND

Radiation events can disperse quasiparticles across superconducting chips, producing correlated faults that challenge QEC. Substrate barriers are introduced as a way to confine this dispersion and reduce the affected region.

  • Radiation events: Radiation events are a comparatively recent and less populated reliability concern for superconducting quantum computers.The background contrasts this literature with the larger body of radiation-reliability work for traditional electronics.
  • Radiation events: Without substrate barriers, quasiparticles can disperse throughout the quantum chip and cause correlated faults.The figure presents this as the unconfined-dispersion case.
  • Radiation events: Radiation-induced events can produce whole-chip correlated errors with reported frequencies ranging from once per hour to multiple times per minute.The passage also indicates that these effects persist transiently, though the supplied text does not provide the full duration range.

B. Quantum Error Correction (Algorithm-level)

The paper combines algorithm-level QEC with substrate-level barriers to reduce spatially correlated radiation faults. Rotated surface codes provide the principal QEC setting, while tiling determines barrier placement, enclosure size, and implementation cost.

  • Quantum error correction: QEC detects and corrects errors through indirect joint-parity measurements using data and stabilizer qubits.The paper uses this QEC structure as the algorithm-level context for radiation hardening.
  • Cross-layer hardening: The cross-layer approach combines substrate barriers, which limit correlated radiation faults, with interleaving, which increases physical distance between virtually close qubits.These mechanisms address the same radiation problem at hardware and QEC-organization levels.
  • Quantum error correction: The rotated surface code is selected because its planar degree-≤4 connectivity suits current hardware and supports efficient graphlike-error decoding.Minimum weight perfect matching is cited as an example of an efficient decoder.
  • Phonon barriers: Substrate-level phonon barriers are hardware-level structures intended to limit radiation byproduct spreading and simultaneous correlated qubit faults.The study evaluates placement and enclosure size rather than a specific physical barrier implementation.
  • Phonon barriers: Barrier permeability controls quasiparticle passage, with bp = 1 representing no flux reduction and bp = 0 representing an ideal barrier.The paper models lower permeability as requiring greater implementation width and cost.
  • Tiling cost: The barrier cost is multiplied by the total length of traces required to tile the full quantum-chip topology.This links local barrier implementation cost to the global tiling pattern.
  • Tiling strategy: Tiling groups spatially close qubits into exclusive regions where quasiparticles can propagate more readily within a tile than across adjacent tiles.A size-1 tile encloses one contiguous qubit region, and tiling can use variable tile sizes across the chip topology.

III. SETUP AND METHODOLOGY

The simulations use a generalized superconducting quantum-computer model with square-lattice connectivity and 1741 qubits, while many experiments operate on only part of the device.

  • Simulation model: The model uses square-lattice connectivity for a superconducting quantum chip containing 1741 qubits.The total qubit count is not required for every simulation because many experiments use only a portion of the chip.

A. Intrinsic noise model

The simulations combine a standard intrinsic Pauli-noise model with a radiation-fault model that injects correlated faults during a finite event window. Radiation-fault probability depends on event timing, qubit distance from the radiation locus, and the transient coherence-time reduction.

  • The SI1000 model appends randomized Pauli noise after each quantum gate, triggered during syndrome sampling with probability p.
  • Radiation events are modeled as spatio-temporally correlated reductions in qubit coherence time τ1.
  • Correlated radiation faults are represented by injecting Y-ERROR operators during circuit execution according to a given probability.
  • The radiation-induced fault probability combines a time-dependent factor based on τrad(t) with a distance-dependent substrate-dissipation factor.
  • Faults are injected only within the radiation event’s duration window Δtrad.

A. Tiling strategy

TETRIS-Q partitions a planar square-lattice qubit graph into equal-sized adjacent tiles and places barriers on tile perimeters. Tile geometry and placement determine both barrier-tracing cost and the simulated logical-error trade-off.

  • Tiling strategy: TETRIS-Q starts from a square master tile and discovers remaining non-overlapping tiles by breadth-first search.
  • Tiling strategy: Adjacent tiles share at least one side, while outer graph portions may contain exceptional vertex assignments.
  • Barriers: Barrier-tracing cost depends on tile size, shape, and placement; 4-qubit and 9-qubit tiles incur 47% and 61% costs, respectively.
  • Barriers: Each hypergraph vertex represents a tile, and hypergraph edges represent barriers shared with physically adjacent tiles.
  • Barriers: Barrier permeability bp controls damping, with bp = 1 meaning that barriers provide no damping.
  • Barriers: Barrier fabrication cost scales linearly with total barrier perimeter, computed after subtracting overlapping perimeter portions.

C. Interleaving

Quantum circuit interleaving maps independent QEC circuits across tile positions so that qubits close in hardware are separated within each code. The evaluation varies tile count and barrier permeability while measuring average logical error rate.

  • Interleaving: Quantum circuit interleaving maps suitable quantum circuits onto a shared grid of qubits as a software-hardware co-design approach.
  • Evaluation: Figure 5 measures distance-9 rotated surface-code average logical error rate against qubits per tile and barrier permeability for different tiling positions.
  • Interleaving: Independent QEC codes can be interleaved rather than assigned to non-overlapping chip regions, increasing physical separation between virtually close code qubits.
  • Interleaving: The hypergraph preserves spatial qubit ordering within tiles and supports shifting multiple circuit mappings among tile positions.

V. RESULTS

The results evaluate radiation-induced logical errors across code distances, barrier permeabilities, and tile sizes. Lower permeability and smaller tiles reduce error peaks and transient duration, with effectiveness improving as code distance increases.

  • 4- and 9-qubit tiles require lower permeability to keep logical error rates below 1%, but comparable code-distance and tile-size combinations perform similarly at bp = 0.5.
  • Lower barrier permeability and smaller phonon barrier tiles reduce radiation-induced logical error peaks.

B. Effect of tiling size and position

Tiling position and size strongly affect average logical error rates. Non-centered tiles are more effective, and sparse tiles can approach single-qubit performance while substantially reducing implementation cost.

  • Less than 50% of QEC-code qubits must be enclosed by centered tiles for observable effects, regardless of barrier permeability.
  • Non-centered tiling is more effective because each growing tile contains at most about 25% of the rotated surface code’s qubits.
  • 10^-3 average logical error rate is reached with single-qubit tiles and bp = 0.01 in both centered and non-centered configurations.
  • More than 75% implementation-cost reduction is achieved using non-centered tiles of at most 25 qubits at bp = 0.1 while reaching below 10^-2 average logical error rate.
  • More than 87% cost reduction is possible with non-centered tiles of up to 225 qubits while approaching 10^-3 average logical error rate.
  • Tiles containing up to 25% of a QEC code’s qubits are comparatively effective to single-qubit phonon barrier tiles.

C. Effect of barrier permeability with respect to noise

The analysis relates intrinsic noise, code distance, barrier permeability, and tile size to radiation-affected QEC thresholds. Barrier tiling can preserve intrinsic-noise efficiency thresholds, but lower-permeability barriers are constrained by code distance.

  • 10^-4 intrinsic noise intensity intersects the code-distance curves at 2.1×10^-1 with fully permeable barriers, bp = 1.
  • A one-order-of-magnitude higher intrinsic noise rate yields crossing points between 1.8 × 10^-1 and 2.4 × 10^-1 at bp = 0.5.
  • Phonon barrier tiling can preserve QEC codes’ characteristic efficiency threshold against intrinsic noise and guarantee radiation-fault tolerance.
  • 48% implementation-cost reduction is obtained with 4-qubit tiles at bp = 0.01 while performing comparatively well against the single-qubit configuration.
  • More than 60% cost saving is achieved with 9-qubit tiles and one-order-of-magnitude higher permeability for code distances 7, 9, and 11.
  • A QEC code’s distance limits the efficacy of lower-permeability phonon barriers, regardless of intrinsic noise intensity.

D. Effect of barriers and interleaving

The analysis shows that phonon-barrier tiling and QEC interleaving jointly reduce radiation-induced logical errors, while sparse, larger tiles can preserve performance at lower implementation cost.

  • Positive interference between phonon barrier tiles and QEC interleaving further mitigates radiation-induced faults.
  • More than 10% peak logical error-rate reduction and up to 40% earlier inflection occur with interleaving on 16-qubit tiles.
  • The smallest 4-qubit tiling advances the second inflection point by about 20% versus 16-qubit tiling and about 40% versus non-interleaved 4-qubit tiling.
  • The best measured average logical error rate is 6.51×10^-4 with 14-qubit tiles and 8 interleaved codes.
  • Combining interleaving, larger-distance codes, and phonon barriers can reduce barrier cost while retaining comparable radiation-induced fault tolerance.

VI. CONCLUSIONS AND FUTURE WORKS

The paper models substrate barriers and QEC configurations to reduce the spatial and temporal spread of radiation-induced faults. Its conclusions identify barrier permeability, tile geometry, code distance, intrinsic noise, and interleaving as key design factors, while calling for broader future investigation.

  • Substrate barriers group physical qubits into tiles and reduce radiation-deposited energy spreading without additional QEC-code overhead.
  • Lower barrier permeability reduces peak logical error rates toward the QEC code’s characteristic noise floor.
  • Tile sizes up to one quarter of a QEC code’s qubits can provide appreciable error-rate reduction, while tile positioning strongly affects barrier efficacy.
  • Barrier benefits correlate with lower intrinsic noise, but increasing QEC code distance does not improve the barriers’ intrinsic noise-error threshold.
  • Phonon barriers and interleaving show positive interference, limiting radiation-induced effects below the considered rotated surface codes’ thresholds.
  • Future analyses should investigate alternative tiling, hardware hardening, radiation-aware decoding, other QEC codes, lattice surgery, and super-stabiliser methods.
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