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Phase-aware Inverse Design for Silicon Photonic Logic Gates
Ary Portes, Narges Dalvand, Felipe M. F. Teixeira, Omar P Vilela Neto, Julian L. Pita Ruiz, Michael Menard, Jhonattan C. Ramirez
TL;DR
Consolidating a complete, ultra-compact architecture remains a bottleneck; this work frames a physically interpretable objective around gate-specific interference conditions. The phase-aware objective achieves higher reported XOR and NAND contrasts, while measured responses closely align with simulations across the C-band.
Problem
Consolidating a complete, ultra-compact architecture remains a fundamental bottleneck.
Source: §2 · pp. 2–3Method
A physically interpretable objective directly embeds each gate’s interference condition.
Source: §4 · p. 10Results
The phase-aware objective achieves XOR and NAND contrasts of 6.4 and 1.1 dB, versus 1.2 and 0.5 dB, and measured responses closely align with simulations across the C-band.
Source: §4 · pp. 7, 10Takeaways & Limitations
The stated contribution is a design principle that embeds gate-specific interference conditions in a physically interpretable objective.
Source: §4 · p. 10Destructive gates (XOR, NAND, and NOR) are more sensitive to phase perturbations because their OFF states rely on near-complete π cancellation.
Source: §4 · p. 11
Abstract
from arXiv · showhide
Inverse design has emerged as a powerful strategy for realizing compact photonic devices; however, its application to logic operations remains constrained by challenges in physical interpretability, architectural generality, and experimental validation. This work introduces an experimentally validated, unified, and physics-driven inverse design framework that implements all fundamental Boolean logic gates within a single silicon photonic architecture. Devices are fabricated within a 2 x 2 um^2 design region on a silicon-on-insulator platform, representing one of the smallest areas reported for photonic logic elements. By integrating amplitude, phase, and energy conservation into a composite figure of merit, the proposed approach enables direct control over constructive and destructive interference. Consequently, all logic functions, including XOR and three-input NAND/NOR operations, are achieved using a standardized configuration with two logical inputs and a bias port. Experimental results exhibit good agreement with numerical simulations across the C-band, confirming both the predictive accuracy and fabrication robustness of the method. Performance benchmarking reveals competitive contrast ratios compared to previous implementations, while providing a unified and scalable design strategy. These findings establish a physically interpretable and experimentally validated paradigm for inverse-designed photonic logic, advancing the development of compact, integrated optical computing systems.
2 Introduction
Photonic logic research has not yet consolidated a complete, ultra-compact, experimentally validated gate library in one invariant silicon-photonic architecture, and prior compact adjoint logic objectives constrain amplitude without directly addressing phase. This work proposes a unified inverse-design framework that combines amplitude, power-balance, and phase constraints, then experimentally validates a library of Boolean gates in a compact design region.
2 Introduction
- Prior compact adjoint logic objectives constrain amplitude but do not directly address the phase relationships between interfering optical fields.The paper identifies this as a limitation of earlier compact adjoint logic designs.Source: §2 · p. 3
- The work introduces an experimentally validated, unified inverse-design framework for realizing all fundamental Boolean gates in one compact photonic architecture.The framework uses a composite objective to control amplitude, power balance, and phase, regulating optical interference.Source: §2 · p. 3
- OR, AND, XOR, NAND, and NOR are designed in a common 2 × 2 µm2 region patterned in a 220 nm-thick silicon device layer.The gates share an architecture while their logic functions use constructive or destructive interference.Source: §2 · p. 3
- Across the C-band, the devices show spectrally robust responses, and measured transmission, logical thresholds, and contrast ratios agree quantitatively with simulations.The paper reports this agreement as evidence of robustness to fabrication imperfections.Source: §2 · p. 3
- The framework is presented as a scalable, physically grounded pathway from individual gates toward complex integrated photonic logic.The section frames the work as a unified design strategy for integrated photonic logic.Source: §2 · p. 3
3 Design Framework
The design framework keeps the silicon-photonic architecture fixed while using topology optimization to vary the design-region topology for each gate. A composite physics-informed objective combines transmission targets, power balance, and phase conditions so gate design becomes parameter selection within one objective.
3 Design Framework
- All five Boolean gates use one architectural template and fixed footprint; only the design-region topology varies with the optimization objective.The platform connects three input waveguides to one output waveguide.Source: §3 · p. 4
- Adjoint topology optimization iteratively guides a uniform design region toward a binary material distribution that fulfills the target logic.The method evaluates permittivity gradients using forward and adjoint simulations, and the optimized devices are fabricated on SOI.Source: §3 · p. 4
- The composite figure of merit combines output-transmission accuracy, inter-port power balance, and inter-port phase symmetry.Its transmission term compares each port's output-mode transmission with a target; the phase term selects an interference condition.Source: §3 · p. 5
- Gate design reduces to parameter selection within one objective, leaving the optimizer and adjoint machinery unchanged across all five gates.The gate-specific interference regime is set by target choices and the sign of the phase selector.Source: §3 · p. 6
- Coherent-superposition bounds set the achievable ON and OFF levels against which measured gate contrast ratios are interpreted.Equal-amplitude inputs in antiphase cancel the output, while energy conservation caps per-port efficiency.Source: §3 · p. 6
- OR and AND use constructive interference, while XOR cancels the dual-input state; NAND and NOR use a permanently switched-on bias port.For AND, a reduced target keeps single-input states below threshold; NAND and NOR differ only in the bias-to-input amplitude ratio that determines the OFF condition.Source: §3 · p. 6
4 Results and Discussion
Measurements closely track simulations across the C-band, while the phase-aware objective improves XOR and NAND contrast over the cited amplitude-based inverse design. The results connect gate behavior to engineered interference and show that one invariant design region supports the Boolean library.
4 Results and Discussion
- AND reaches T ≈0.32 for the dual-input state versus ≈0.08 for single-input states, yielding 6.0 dB contrast.The XOR gate transmits T ≈0.32 for single-input states and suppresses the dual-input state to T ≈0.074, yielding 6.4 dB contrast.Source: §4 · p. 7
- The three-input NAND and NOR gates use a permanent bias to maintain (0,0) ON; measured T00 is 0.44 for NAND and 0.33 for NOR, while NAND T01 and T10 are approximately 0.35 and above threshold.For NOR, a single logic input reduces the output, with T01 ≈ T10 ≈ 0.15.Source: §4 · p. 7
- Field distributions show constructive gates reinforcing output fields, XOR cancelling the dual-input output, and NAND/NOR combining logic inputs with a continuous bias field.The distributions follow the intended interference patterns rather than diffuse scattering, consistent with logical function encoded through engineered phase relationships.Source: §4 · pp. 8–9
- The framework encodes logic in device topology while identical-amplitude, identical-phase inputs can come from a single source via a splitter.Unlike approaches that enforce interference through input offsets, this objective explicitly incorporates phase, particularly for destructive gates.Source: §4 · p. 10
- XOR contrast is 6.4 dB versus 1.2 dB, and NAND contrast is 1.1 dB versus 0.5 dB, compared with the closest amplitude-based inverse design.The measured responses across the C-band closely align with simulations for each gate.Source: §4 · pp. 7, 10
- The framework monolithically integrates the entire logical operation within a single invariant 2 × 2 µm2 design region, eliminating the need for auxiliary routing and splitting components.Avoiding cascades of multiple photonic elements avoids cumulative insertion losses, making the gates substantially less lossy while maintaining a standardized physical footprint for the entire Boolean library.Source: §4 · pp. 10–11
- Residual simulation-to-measurement deviations are attributed to fabrication-driven changes in feature size, sidewall angle, and material index that alter optical path lengths and relative phase.The authors interpret these deviations as predictable under realistic fabrication tolerances rather than evidence of uncontrolled scattering.Source: §4 · pp. 11–12
- Destructive gates are more sensitive than constructive gates to phase perturbations, and their extinction ratios vary steeply with relative phase offset.The phase-sensitive gates have defined phase windows for logical operation, whereas constructive gates remain essentially flat; dimensional sweeps show most gates preserve function across the ±10 nm tolerance typical of advanced silicon photonics.Source: §4 · pp. 11–12
5 Conclusions
The conclusions report a five-gate silicon photonic logic library in a shared compact footprint, with experimental responses agreeing with simulations across the C-band. They attribute the framework’s interpretability to physics embedded in its objective and report robustness to fabrication variations.
5 Conclusions
- The framework incorporates interference physics into a composite objective, enabling control of both output amplitude and phase.Each gate’s interference condition is predetermined from energy conservation and coherent superposition, then validated against measured device response.Source: §5 · pp. 12–13
- All five gates were realized in identical 2 × 2 µm^2 design regions and showed quantitative agreement with simulations across the C-band (1520–1580 nm).The paper describes the 4 µm^2 footprint as one of the smallest reported for photonic logic elements.Source: §5 · p. 13
- At 1550 nm, measured contrast ratios were 6.4 dB for XOR, 6.0 dB for AND, 3.4 dB for NOR, and 1.1 dB for NAND.The narrower NAND contrast is attributed to energy conservation in multi-port coherent superposition, not an optimization limitation.Source: §5 · p. 13
- All five gates maintained logical functionality under uniform morphological dilation or erosion of up to ±20 nm, exceeding typical ±10 nm foundry tolerances.The designs used a 100 nm minimum feature size and spacing constraint for compatibility with standard DUV lithography.Source: §5 · p. 13
- The authors attribute minor simulation–measurement discrepancies to predictable nanoscale phase perturbations in phase-critical destructive gates.XOR, NAND, and NOR rely on near-complete π cancellation and are more sensitive to phase perturbations than constructive OR and AND gates.Source: §5 · p. 13
- The authors present the experimentally validated framework as a scalable, compact pathway toward optical computing and information co-processors.They conclude that universal logical operations can be encoded within a single invariant footprint with robust fabrication tolerances.Source: §5 · pp. 13–14
6 Methods
The methods describe inverse design and fabrication of silicon photonic logic gates, followed by optical characterization of the devices. The optimization workflow combines topology regularization, numerical optimization, and electromagnetic simulation.
Design Optimization
- The inverse-design workflow used a cone-shaped density filter with a 120 nm radius to enforce fabrication-compatible minimum features, progressive Heaviside projection for binary manufacturable topology, Adam at α = 0.01, and cloud-based FDTD simulations of forward and adjoint fields.Source: §6 · p. 14
Fabrication
- Devices were fabricated on an SOI platform using electron-beam lithography and a single-step anisotropic etch, with 100 nm minimum feature size and spacing.A silicon dioxide top cladding was deposited after pattern transfer.Source: §6 · p. 14
Characterization
- Optical characterization used an EXFO T100S-HP tunable laser as the source and an EXFO CTP10 optical power meter to measure transmitted power; simultaneous two-input measurements split laser output into two paths with independent polarization controllers.Source: §6 · p. 15
8 Author contributions
The author contributions assign conceptualization, simulations, fabrication layout, optical characterization, data analysis, supervision, and writing across the listed authors.
8 Author contributions
- JCR, OPV, and AP handled idealization and conceptualization.AP, FMT, and JCR developed simulations and the framework.Source: §8 · p. 16
- AP, FMT, JCR, JPR, and MM prepared the fabrication layout; ND, JPR, and MM performed optical characterization.Source: §8 · p. 16
- AP, JCR, ND, JPR, and MM conducted data analysis; JCR, MM, OPV, and JPR supervised the work.All authors contributed to writing the original draft and editing.Source: §8 · p. 16