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GPU-Accelerated Gate-Level Time-Based Power Analysis via Event-Density-Aware Partitioning and Kernel Fusion

Weihao Wang, Yikang Ouyang, Hongyuan Liu, Yuzhe Ma

arXiv:2609.05960v1cs.AR

TL;DR

Gate-level time-based power analysis provides fine temporal detail but is computationally intensive. This paper presents a GPU framework with state-indexed retrieval, event-density-aware partitioning, and fused power computation. It reports high accuracy and up to 37.63× end-to-end speedup over multi-threaded PrimeTime PX.

  • Problem

    Gate-level time-based power analysis provides high temporal resolution but is computationally intensive as designs and simulation traces grow.

    Source: §1 · p. 1

  • Method

    The GPU framework combines state-indexed power retrieval, event-density-aware per-gate cycle partitioning, and fused dynamic and leakage computation.

    Source: §1 · p. 2

  • Results

    1.94× to 37.63× end-to-end speedup over multi-threaded PrimeTime PX, with high accuracy.

    Source: §8 · p. 24

  • Takeaways & Limitations

    The framework demonstrates high-accuracy GPU acceleration for gate-level time-based power analysis, with end-to-end gains over a multi-threaded commercial baseline.

    Source: §8 · p. 24

Abstract

from arXiv · show

Power analysis is crucial in modern chip design flow. Particularly, time-based power analysis can provide fine-grained power consumption information to facilitate the diagnosis of power issues and guide power optimization accordingly. However, it may take tens of hours to conduct time-based power analysis on modern large-scale circuits, which greatly slows down the power optimization flow. In this paper, we present the first GPU-accelerated gate-level time-based power analysis framework. We propose a novel data structure to enable efficient state-dependent power retrieval. To accommodate the imbalanced event distribution across gates, we propose an event-density-aware partitioning strategy that allocates GPU threads based on gate event density. Finally, we fuse the power computation into a single kernel invocation to reduce redundant work in separate kernels. Experimental results show that our proposed framework achieves high accuracy while delivering up to 37.63x end-to-end speedup compared to multi-threaded Synopsys PrimeTime PX.

1 Introduction

The introduction motivates accelerating gate-level time-based power analysis because it is computationally intensive, then presents a GPU framework targeting state retrieval, skewed event workloads, and redundant kernel work.

1 Introduction

  • Gate-level time-based simulation offers high temporal resolution but is computationally intensive, and commercial runs can take several days.Long traces and increasing design complexity exacerbate the challenge.Source: §1 · pp. 1–2
  • ML approaches use RTL activity proxies rather than event-driven per-gate accumulation, while sampled simulation may miss short glitches and transient peaks.Commercial tools support complete, precise gate-level reports, but runtime becomes prohibitive for large designs.Source: §1 · p. 2
  • GPU acceleration must address iterative state-dependent power lookup, skewed per-gate event counts, and redundant gate-state reconstruction across separate kernels.Fixed partitioning can burden sparse gates or limit parallelism for dense gates; separate dynamic and leakage kernels repeat reconstruction and cycle traversal.Source: §1 · p. 2
  • The framework combines binary-indexed state-power retrieval, event-density-aware cycle partitioning, and fused dynamic/leakage computation, using gate- and cycle-level parallelism.The paper describes this as the first work exploring GPU acceleration for time-based power analysis.Source: §1 · p. 2
  • Up to 37.63× end-to-end speedup over multi-threaded PrimeTime PX, with high accuracy.The reported comparison is against the multi-threaded commercial tool.Source: §1 · p. 3

2 Preliminaries

The preliminaries define gate events and states, describe dynamic, leakage, and glitch power, and introduce separate naive GPU kernels for fine-grained time-based analysis.

2.1 Basic Concepts and Terminology

  • A gate event records a pin’s logic value and timestamp, while the gate state is the vector of pin values at a given time.The state changes when an event updates a pin value.Source: §2.1 · p. 3

2.2 Power Models

  • Dynamic power occurs at events and includes internal and switching power, whereas state-dependent leakage persists between events and changes when the gate state changes.Internal energy is obtained by interpolating a state-associated power LUT; switching power concerns charging or discharging the output load.Source: §2.2.1 · p. 3

2.2.2 Glitch Power.

  • Glitches arise from misaligned event timing, add dynamic power, and are reflected in the per-cycle waveform used to diagnose cycle-specific anomalies.The waveform can support fine-grained root-cause analysis of signal activity, input-state conditions, or transient events.Source: §2.2.2 · p. 3, §2.2.3 · p. 3

2.3 Power Analysis Modes

  • Time-based analysis processes every transition to report temporal variation and power components, while averaged mode reports coarser power over an interval.The standard flow supplies design and activity data plus STA slew information to event-driven computation.Source: §2.3 · p. 4

2.4 Time-Based Power Computation with a Naive GPU Implementation

  • Naive-D assigns one event per thread to compute dynamic-power contributions, while Naive-L assigns cycle windows to threads to compute leakage power.Naive-D reconstructs gate state, retrieves a state-dependent LUT, computes event energy, accumulates the waveform, and detects glitches; Naive-L merges pin-event streams and apportions leakage over overlapped cycle bins.Source: §2.4 · p. 4, §2.4.1 · pp. 4–5, §2.4.2 · pp. 5–6

2.4.3 Parallel Granularity of Naive Kernels.

  • Naive-D has fixed one-event-per-thread granularity, whereas Naive-L uses a tunable cycles-per-thread setting and the naive baseline uses one cycle per thread.Naive-L’s event-side merge and cycle-side waveform updates form its two workload components.Source: §2.4.3 · p. 6, §2.4.2 · p. 6

3 Characterization and Motivation

The characterization identifies costly state-dependent retrieval, skewed event counts across gates, and redundant work when dynamic and leakage kernels run separately.

3.1 Challenge #1: Inefficient State-Dependent Power Retrieval

  • Exhaustively matching state patterns requires separate retrieval procedures for leakage and internal power at each event, creating runtime overhead.The section motivates a more efficient data structure for state-dependent power retrieval.Source: §3.1 · p. 6

3.2 Challenge #2: Imbalanced Event Distribution Across Gates

  • Per-gate event counts are highly skewed: the 90th and 99th percentiles reach up to four orders of magnitude above the median on Rocket’s dhrystone benchmark.A globally fixed cycles-per-thread setting therefore cannot balance sparse and dense gates effectively; small settings can waste scheduling effort, while large settings limit parallelism for dense gates.Source: §3.2 · p. 7

3.3 Challenge #3: Redundant Work in Separate Kernels

  • Separate dynamic and leakage kernels duplicate gate-state reconstruction, and dynamic-kernel glitch detection repeats cycle-level event searches that leakage traversal already exposes.Both kernels reconstruct state at their assigned start times using per-pin binary searches; the section therefore motivates sharing state reconstruction and cycle-level information.Source: §3.3 · pp. 7–8

4 Multi-Level GPU Optimizations

The section introduces a sequence of GPU kernel optimizations, beginning with the separate naive dynamic- and leakage-power kernels.

4 Multi-Level GPU Optimizations

  • The optimization overview starts from Naive-D’s one-event-per-thread dynamic kernel and Naive-L’s one-cycle-per-thread leakage kernel.The figure presents incremental optimization timelines for illustration; detailed experimental results are deferred to Section 6.4.1.Source: §4 · p. 8

4.1 Efficient State-Dependent Power Retrieval with State-Indexed Power Lookup

State-Indexed Power Lookup (SIPL) replaces repeated state-pattern traversal with direct array indexing for supported gates, while retaining traversal for gates with more than 16 pins.

4.1 Efficient State-Dependent Power Retrieval with State-Indexed Power Lookup

  • SIPL encodes Liberty state patterns as binary indices over a fixed pin order and stores the corresponding power item at each indexed entry.Patterns with don’t-care pins populate multiple indices; runtime gate states use the same encoding to retrieve the power item directly.Source: §4.1 · pp. 8–9
  • SIPL is used for gates with at most 16 pins; gates above that threshold fall back to direct state-pattern traversal, used by 0.05% of gates in the experiments.The cutoff avoids retrieval arrays that can exceed memory capacity for very large pin counts.Source: §4.1 · p. 9
  • The paper reports that SIPL reduces GPU kernel execution time relative to the naive implementation in Fig. 5.The supplied passage does not specify the reduction magnitude.Source: §4.1 · p. 9

4.2 Adaptive Per-Gate Temporal Partitioning

The section adapts each gate’s temporal partitioning to its event density, aiming to distribute work more evenly across GPU threads. A parallelism floor addresses sparse gates, while denser gates receive finer-grained parallelism.

4.2.1 Event-Density-Aware Per-Gate Cycle Partitioning.

  • The scheme divides each gate’s cycles into contiguous thread windows sized so each thread is expected to process approximately the target event count.Each thread processes the gate’s events whose timestamps fall within its assigned window.Source: §4.2.1 · p. 9
  • A density floor limits window growth for sparse gates, where event-only sizing could leave cycle traversal and waveform updates under-parallelized.The method introduces a parallelism floor to stabilize granularity in the sparse regime.Source: §4.2.1 · pp. 9–10

4.2.2 Thread-Count Characterization.

  • Sparse gates are governed by the parallelism floor, while dense gates receive more threads as event processing dominates.The scheme reallocates parallelism by gate event density to avoid over-parallelizing sparse gates and improve utilization.Source: §4.2.2 · p. 11
  • The proposed partitioning achieves a 2 reduction in kernel execution time compared with B○.The passage does not specify a multiplier for the reported reduction.Source: §4.2.2 · p. 11

4.3 Kernel Fusion for Unified Power Computation

Kernel fusion shares gate state and cycle-level event information while computing leakage and dynamic power in one invocation. The fused design also performs event-level glitch detection and scales glitch energy when applicable.

4.3 Kernel Fusion for Unified Power Computation

  • The fused kernel computes leakage and dynamic power together, sharing gate state and cycle-level information to reduce redundant work.Separate kernels would otherwise reconstruct gate state; cycle-level event counts can also be reused for glitch detection.Source: §4.3 · p. 11

4.3.2 Dynamic Power (Line 8–Line 18).

  • At each event timestamp, the kernel retrieves state-dependent internal power, computes switching energy, and detects glitches from per-pin event counts within a clock cycle.When a pin has multiple events in the cycle, the event’s dynamic energy is scaled by the returned glitch ratio.Source: §4.3.2 · p. 12, Figure 7 · p. 12, §4.3.3 · p. 13

4.3.3 Glitch Power (Line 11–Line 15).

  • Kernel fusion achieves a 3 reduction in kernel execution time compared with C○.The passage does not specify a multiplier for the reported reduction.Source: §4.3.3 · p. 13

4.4 Thread Mapping and Two-Phase Power Results Reduction

The implementation maps gate cycle windows to GPU threads and reduces thread-local power results in two phases. Its per-gate buffers are sized to the block thread count to limit intermediate memory overhead.

4.4 Thread Mapping and Two-Phase Power Results Reduction

  • Each thread processes a continuous cycle window for its assigned gate, with thread allocation determined by that gate’s event density.The number of blocks per gate is derived from its thread allocation and the fixed threads-per-block count.Source: §4.4 · p. 13
  • Threads accumulate four power components in a per-gate buffer with one row per block thread, then a reduction kernel produces final per-gate results.The buffer columns represent leakage, internal, switching, and glitch power.Source: §4.4 · p. 13
  • Reusing per-gate buffers avoids private global-memory storage for every thread while enabling thread-safe accumulation.The design is described as balancing computational efficiency and GPU memory usage.Source: §4.4 · pp. 13–14

5 Framework Overview

The framework preprocesses design and activity inputs on the CPU, then processes event chunks through GPU power computation and reduction. CPU packing for the next chunk overlaps GPU computation for the current chunk.

5 Framework Overview

  • CPU preprocessing parses design, parasitic, constraint, Liberty, and activity files, derives timing information, and chunks events to fit limited GPU memory.The activity parser uses multiple threads.Source: §5 · p. 14
  • For each chunk, CPU packing of the next chunk overlaps GPU power computation for the current one before a reduction kernel runs.The design metadata and events are packed into contiguous buffers and transferred to GPU memory.Source: §5 · p. 14
  • After processing all chunks, the framework transfers results to the CPU and reports design- and gate-level power and the full-design waveform.Design-level component power is summed across gates; peak power is the maximum waveform value across cycles.Source: §5 · p. 14

6 Experimental Results

Across the evaluated designs, the framework closely matches PrimeTime PX in power accuracy while reducing end-to-end runtime. The experiments also examine runtime bottlenecks, memory use, optimization contributions, and parameter choices.

6.2.1 Precision.

  • Average errors were 0.12% for leakage, 0.06% for internal, 0.05% for switching, 0.11% for glitch, and 0.71% for peak power.PrimeTime PX power results served as the reference.Source: §6.2.1 · p. 15, Table 2 · p. 16

6.2.2 Fine-Grained Spatial and Temporal Comparison.

  • Kendall’s Tau was at least 0.994 for total-power rankings and 0.998 for glitch-power rankings; most gates and cell types fell in low-error ranges.Hotspot overlap@1% was high at both per-gate and standard-cell levels.Source: §6.2.2 · pp. 15–16, Figure 10 · p. 16, Figure 11 · p. 16
  • Cycle-level power traces closely matched PrimeTime PX across benchmarks, with low RMSE and NRMSE and high Pearson correlation.The trace comparison used Adder and GigaBOOM, with small value deviations but consistent trends.Source: §6.2.2 · pp. 16–17, Figure 12 · p. 17, Table 3 · p. 17
  • Across various design sizes and benchmarks, the framework achieved a 1.94× to 37.63× end-to-end speedup versus the multi-threaded PrimeTime PX baseline, with greater speedups on larger designs and longer benchmarks.Source: §6.2.3 · p. 17

6.3.1 Runtime Breakdown.

  • On GigaBOOM, power computation accounted for 76.3% of the 64-thread CPU runtime, while GPU computation and transfer together accounted for 11.9%; activity parsing then dominated at 68.0%.Across benchmarks, the GPU implementation achieved a 10.10× geometric-mean speedup over the 64-thread CPU implementation.Source: §6.3.1 · p. 18, Figure 13 · p. 18, §6.3.2 · p. 18

6.3.2 CPU/GPU Comparison.

  • Peak GPU memory ranged from 12.22 GB to 15.44 GB, with event storage accounting for 77.2%–97.5%; profiling identified low eligible-warp availability and long-latency dependencies as kernel constraints.Across GPUs, normalized runtime had geometric means of 1.60× on A30 and 0.56× on H100 relative to RTX 3090.Source: §6.3.3 · p. 19, Figure 15 · p. 19, §6.3.4 · p. 19

6.4.1 Incremental and Ablation Evaluation.

  • Incremental optimizations reduced geometric-mean runtime by 9.45% with SIPL, 43.67% with event-density-aware partitioning, and 63.12% with kernel fusion versus naive; removing partitioning caused the largest slowdown.The leave-one-out slowdown from removing partitioning was 147.4% in geometric mean and up to 275.9%.Source: §6.4.1 · pp. 20–21, Figure 17 · p. 20, Figure 18 · p. 20

6.5 Parameter Sensitivity Analysis.

  • Thresholds 8 and 16 reduced geometric-mean runtime by 2.9% versus threshold 4, while threshold 32 caused out-of-memory on one benchmark; the selected event target and parallelism floor were 8 and 512.An excessively small event target increases thread count and gate-state reconstruction overhead; a floor of 512 increased runtime by 0.7% versus 128.Source: §6.5.1 · pp. 22–23, Figure 22 · p. 22, §6.5.2 · p. 23

7 Related Work

Related work spans learned or sampled power estimation, practical analysis tools, and GPU acceleration for other EDA tasks. The paper positions complete gate-level time-based analysis on GPUs as underexplored.

Related academic power-analysis research

  • ML approaches estimate power from learned design representations, while simulation-based methods use sampling or limited temporal coverage and introduce approximations.The surveyed ML approaches do not guarantee per-gate, per-event time-based correctness or complete reporting of all power components, peak power, and waveforms.Source: §7 · pp. 23–24

Practical tools

  • OpenSTA supports static timing and averaged power, Trace2Power exports activity, and PrimeTime PX provides the closest baseline for complete gate-level time-based analysis.The cited practical tools differ in whether they compute a complete time-based power report.Source: §7 · p. 24

GPU acceleration for EDA

  • GPU EDA work covers tasks such as simulation, placement, routing, and STA, while cited power-related GPU tools target activity generation or averaged power rather than time-based analysis.The paper characterizes complete gate-level time-based power analysis on GPUs as underexplored.Source: §7 · p. 24

8 Conclusions

The paper presents a GPU-accelerated framework for gate-level time-based power analysis, combining state-indexed lookup, event-density-aware partitioning, and kernel fusion. It reports high accuracy and 1.94× to 37.63× end-to-end speedup over multi-threaded PrimeTime PX.

Conclusion

  • The framework combines state-indexed power lookup, event-density-aware per-gate cycle partitioning, and fused dynamic and leakage power computation.The paper identifies it as the first GPU-accelerated gate-level time-based power analysis framework, to the authors’ knowledge.Source: §8 · p. 24
  • The framework achieves high accuracy and 1.94× to 37.63× end-to-end speedup over multi-threaded PrimeTime PX.Source: §8 · p. 24
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