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Computation-Limited Signals in Practice: A Throughput Anomaly in Software-Defined O-RAN PHY Layers

Gabriel Alessi Posonski, Saulo Queiroz, João P. Vilela, Benjamin Koon Kei Ng, Chan-Tong Lam, Edmundo Monteiro

arXiv:2609.06666v1eess.SP

TL;DR

Conventional bit-rate models neglect PHY processing latency when it is amortized across multiple symbols, leaving first-symbol delivery time uncharacterized. The paper extends SC throughput analysis to bursts and evaluates measured PHY processing costs; it finds that a nominally faster mode can deliver lower effective throughput for some payload sizes.

  • Problem

    Conventional bit-rate models neglect modulation and demodulation latency amortized over multiple symbols, so they do not characterize the first symbol’s end-to-end delivery time.

    Source: §1 · p. 2

  • Method

    The paper extends the SC framework to parameterize burst length and analyzes published processing-latency measurements from established software PHY implementations.

    Source: §1 · p. 3, §7 · p. 10

  • Results

    Across eight payload intervals, the 48-Mbit/s mode outperforms the 54-Mbit/s mode; both use equal symbol counts, and 54-Mbit/s first-symbol latency is 0.257 µs greater.

    Source: §5.2 · p. 8

  • Takeaways & Limitations

    Link adaptation should account for PHY processing latency because choosing the highest feasible nominal rate can reduce useful throughput when modes require the same number of symbols.

    Source: §6 · p. 9

    The reported values describe throughput for the modeled PHY processing unit, not complete application throughput, and exclude protocol and medium-access overheads.

    Source: §6 · p. 9

Abstract

from arXiv · show

We formalize a performance anomaly in software-based wireless physical-layer (PHY) implementations, a key enabling technology for Open Radio Access Network (O-RAN) systems. For a fixed offered load, the number of PHY symbols required to transmit the load decreases as the nominal bit rate increases because each symbol conveys more bits. Shorter bursts, however, provide fewer opportunities to exploit pipelined modulation, transmission, and demodulation. Processing latency therefore represents a larger fraction of the total delivery time and may cause a nominally faster PHY configuration to deliver lower effective throughput. We call the operating condition in which computational latency governs effective throughput the computation-limited regime. Its most pronounced manifestation occurs when the offered load fits in a single symbol: intersymbol pipelining cannot be exploited, and modulation and demodulation latencies cannot be amortized. Their combined latency may exceed the symbol duration even when transmitter and receiver processing independently meet their real-time deadlines. Because PHY processing complexity often scales superlinearly with the resources allocated to each symbol, a higher-rate configuration may consequently deliver lower throughput than a slower one. We validate this anomaly using processing-latency measurements reported for established software-defined PHY implementations. The results show that PHY processing latency should be incorporated into link-adaptation algorithms for very-high-throughput services in future 6G wireless networks.

1 Introduction

For short bursts, processing latency can outweigh the nominal-rate advantage of a higher-rate PHY configuration. The paper identifies this as a practical computation-limited condition for software-based PHYs and O-RAN systems.

1 Introduction

  • PHY algorithms can scale superlinearly with symbol resources; for an OFDM FFT, increasing subcarriers raises complexity as O(N log2 N).Higher nominal rates can come from denser modulation, more spatial streams, or more sophisticated coding and detection.Source: §1 · pp. 2–3
  • As nominal bit rate rises, a fixed offered load needs fewer symbols, so processing latency is amortized over fewer symbols and occupies more of burst delivery time.The effect is compounded by higher processing costs for higher-rate configurations.Source: §1 · p. 2
  • A nominally higher-rate configuration can deliver lower effective PHY throughput than a slower one, reversing the ranking implied by conventional bit-rate metrics.The paper analyzes the limiting case of a single-symbol burst using published latency measurements from established real-time software PHY implementations.Source: §1 · p. 3
  • The paper extends the SC throughput model to parameterize burst length, evaluates multiple bit-rate configurations using legacy Wi-Fi PHY measurements, and derives an anomaly criterion and payload intervals for throughput inversions.SC analysis incorporates processing latency into conventional communication-performance metrics.Source: §1 · pp. 2–3

2 Background and Related Work

Spectro-computational analysis incorporates PHY processing time into communication metrics, complementing conventional channel-resource limits. The reviewed software PHY implementations motivate the use of Sora for quantitative comparisons.

2.1 Spectro-Computational Analysis

  • SC throughput accounts for the time to make the first decoded bits available after transmit processing, channel transmission, and receive processing.Its spectral-efficiency metric is obtained by dividing SC throughput by bandwidth.Source: §2.1 · p. 3
  • Equation (2) describes one-unit delivery latency; multi-unit opportunities can overlap pipeline stages, so the single-unit model motivates an extension for bursts.Increasing nominal rate or bandwidth may require enough extra processing to offset the expected communication gain [5].Source: §2.1 · p. 3

2.2 Software-Implemented Physical Layers

  • Sora provides detailed PHY-block costs for real-time IEEE 802.11a/b/g processing, while other implementations lack matched TX and RX times for the same unit and platform.The reported measurements from those other implementations therefore do not support a symmetric comparison; the paper uses Sora for its complete numerical application.Source: §2.2 · pp. 3–4

3 Expanded Spectro-Computational Throughput Model

The expanded SC model accounts for the number of symbols needed for a payload and separates first-symbol latency from the cadence of pipelined outputs. It also states modeling assumptions and excludes protocol overheads to isolate the PHY computational effect.

3 Expanded Spectro-Computational Throughput Model

  • Payload D and the mode-specific bits per full OFDM symbol Bm determine the length of a PHY burst, the consecutive symbols used for one opportunity.When D is not a multiple of Bm, the final symbol is padded; that padding uses processing and channel resources but is excluded from useful bits.Source: §3 · p. 4
  • The expanded SC throughput uses the complete burst-delivery time; for a single fully occupied symbol it reduces to the single-unit model, and for longer bursts the first-unit cost is amortized.With increasing symbol count, throughput approaches Bm/Tpipe,m.Source: §3 · p. 4
  • Mode comparisons require equal useful-bit payloads, while the model assumes approximately constant per-unit processing time and enough independence to overlap consecutive units.Preambles, contention, acknowledgments, retransmissions, and upper-layer headers are excluded, though they can be added for a specific protocol.Source: §3 · p. 4
  • The first symbol incurs TX, transmission, and RX latency, while subsequent decoded outputs arrive at the cadence of the slowest stage.The pipeline figure identifies that cadence as Tpipe = max{Tcomp,TX, Tsym, Tcomp,RX}; its block widths are schematic.Source: §3 · p. 4, Figure 1 · p. 5

4 Methodology and Data Selection

The quantitative analysis selects Sora because the other implementations lack matched processing data. For Sora, it reconstructs useful bits per symbol and processing costs across three modes using reported block costs.

4.1 Candidate Implementations

  • Sora is the only candidate used quantitatively because the other studies lack matched per-unit capacity, symbol duration, and separate transmit and receive processing times.Table 1 summarizes the three studies considered; imposing missing values could introduce platform-dependent assumptions.Source: §4.1 · p. 5, Table 1 · p. 6

4.2 Sora Modes and Processing-Time Reconstruction

  • The selected Sora modes are 24, 48, and 54 Mbit/s, yielding 96, 192, and 216 useful bits per symbol, respectively.All use 48 data subcarriers and a 4 µs symbol duration.Source: §4.2 · p. 5
  • The 54-Mbit/s scrambling/descrambling cost is reused for the other modes, and the 48-Mbit/s soft-demapping cost is set equal to the 54-Mbit/s value.The latter modes share 64-QAM and the same number of coded bits per symbol.Source: §4.2 · p. 5
  • Transmitter time sums scrambling, convolutional-encoding, and inverse-FFT costs; receiver time is the larger of the parallel Viterbi-decoder branch and the other receiver-block branch.Sora assigns Viterbi decoding to one core and the remaining receiver blocks to a second core.Source: §4.2 · p. 6
  • Processing times are calculated at 2.66 GHz, matching Sora’s evaluation platform.Source: §4.2 · p. 6

5 Numerical Results and Anomaly Identification

Expanded SC throughput reverses nominal-rate ordering when candidate modes use the same number of symbols, while a symbol-count reduction can restore the faster mode’s advantage. Processing latency dominates short bursts but is amortized over long ones.

5.1 Processing Times

  • All three modes meet the 4-µs per-stage real-time constraint with a dedicated Viterbi core, and the channel interval is the slowest pipeline stage at 4 µs.Table 3 reports the calculated processing times for the selected IEEE 802.11a/g modes.Source: §5.1 · p. 6, Table 3 · p. 7
  • For 54 Mbit/s, processing accounts for 54.1% of total time at S = 1 but 1.45% at S = 80.The 100%-stacked bars separate TX processing, RX processing, and symbol transmission.Source: Figure 2 · p. 7, §5.1 · p. 7
  • With receive blocks sequential on one core, estimated times are 2.940, 4.542, and 4.771 µs for 24, 48, and 54 Mbit/s; parallelization is required for real-time operation.Even after parallelization, receive time rises from 2.119 to 3.870 µs between 24 and 54 Mbit/s, mainly because of Viterbi decoding.Source: §5.1 · p. 7, Table 3 · p. 7

5.2 Expanded Throughput

  • At D = 192 bits, 48 Mbit/s reaches 22.723 Mbit/s versus 22.052 Mbit/s at 54 Mbit/s; at D = 216 bits, 54 Mbit/s wins by using one symbol instead of two.The same-symbol reversal recurs at 384 bits, while the symbol-count advantage recurs at 432 bits.Source: Figure 3 · p. 8, §5.2 · p. 8
  • Across eight payload intervals, 48 Mbit/s outperforms 54 Mbit/s when both use the same symbol count; its first-symbol latency is 0.257 µs lower.The intervals are 4–192, 220–384, 436–576, 652–768, 868–960, 1,084–1,152, 1,300–1,344, and 1,516–1,536 bits.Source: §5.2 · p. 8
  • At 11,200 bits, throughput is 23.784, 46.579, and 52.655 Mbit/s for the 24-, 48-, and 54-Mbit/s modes, respectively.At this opportunity size, initial latency is amortized over dozens of symbols.Source: §5.2 · p. 9

6 Discussion and Limitations

The anomaly matters for link adaptation and O-RAN policies that can account for processor load and measured latency as well as channel state. The numerical study is limited to modeled PHY-unit throughput and its measured implementation assumptions, so external generalization requires broader platform validation.

6 Discussion and Limitations

  • Selecting the highest feasible nominal rate can reduce useful throughput when candidate modes need the same symbol count, but a one-symbol saving can justify the more aggressive mode.When symbol counts match, extra computational budget could instead support stronger coding, more reliable detection, or additional decoder capacity.Source: §6 · p. 9
  • O-RAN adaptation can use processor load and measured latency alongside channel state, provided platform-specific transmit and receive timings are measured.Equation (7) supplies a compact objective for these cross-layer decisions.Source: §6 · p. 9
  • The reported values are throughput for the modeled PHY processing unit, not complete application throughput; protocol overheads and retransmissions are excluded.The study also uses small analytical opportunities rather than complete Wi-Fi frames and selected PHY block costs rather than every modern-transceiver operation.Source: §6 · p. 9
  • The internal comparison uses a shared platform, symbol duration, processing architecture, and block set, but external generalization is limited.The proposed modern validation includes complete 5G-NR O-RAN paths, repeated timing samples, processor contention, memory-transfer effects, energy, and reliability.Source: §6 · p. 9

7 Conclusion

The conclusion characterizes a computation-limited throughput anomaly in software-based PHYs and identifies short, high-density bursts as a practical concern for O-RAN systems.

7 Conclusion

  • A higher nominal-rate PHY configuration may deliver lower effective throughput than a slower one when processing latency is accounted for.This can occur when a single symbol carries the offered load, preventing intersymbol pipelining and making processing latency a substantial share of delivery time.Source: §7 · p. 9
  • Higher-rate configurations can increase signal dimensions and computational cost, with some PHY algorithms scaling superlinearly in those dimensions.The anomaly is most pronounced when the entire offered load fits in one symbol, so modulation, transmission, and demodulation cannot be pipelined across symbols.Source: §7 · p. 9
  • The anomaly is a practical manifestation of the computation-limited regime formalized by the SC framework in.In that regime, computational resources constrain asymptotic communication performance even as conventional channel resources become arbitrarily abundant.Source: §7 · p. 10
  • The authors extended the SC framework by parameterizing the number of symbols per transmission opportunity to characterize bursts of different lengths.They identify short bursts of a few high-density symbols as a practical concern for emerging very-high-throughput software-based PHYs.Source: §7 · p. 10
  • The authors plan to develop link-adaptation algorithms that account for symbol-processing latency when selecting configurations to maximize effective throughput.Source: §7 · p. 10

Author Biographies

The biographies describe six authors’ academic appointments, education, professional experience, and research interests.

Author Biographies

  • One author is pursuing a B.S. in computer science at UTFPR and works as a software developer, with research interests including software-defined radio and O-RAN.Source: Gabriel Alessi Posonski · p. 11
  • One author is an associate professor at UTFPR whose current research interests include networking and signal processing for wireless communications.The biography also notes a Ph.D. from the University of Coimbra and contributions to open-source networking projects.Source: Saulo Queiroz · p. 11
  • One author is an associate professor at the University of Porto and center coordinator at INESC TEC, with research interests in security and privacy of networked and intelligent systems.Source: Saulo Queiroz · p. 11
  • One author is an associate professor at Macao Polytechnic University whose research interests include wireless communications and signal processing, especially MIMO, NOMA, and machine learning.Source: Benjamin Koon Kei Ng · p. 12
  • One author is an associate professor at Macao Polytechnic University whose research interests include mobile wireless communications, machine learning in communications, and computer vision for smart cities.Source: Chan-Tong Lam · p. 12
  • One author is a full professor at the University of Coimbra with more than 30 years of research experience and more than 200 publications.The biography also notes nine co-authored international patents and work in computer communications, wireless networks, quality of service, management, and security.Source: Edmundo Monteiro · p. 12

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