Source-linked AI summary
GPU-Accelerated Hypergraph Partitioning and Placement to Map SNNs on Neuromorphic Hardware
Marco Ronzani, Cristina Silvano
TL;DR
Mapping SNNs to neuromorphic hardware is challenging as networks grow, and mapping quality affects performance. The paper presents a GPU-accelerated partitioning and placement pipeline tailored to this hardware, reporting lower analytical energy and latency costs and faster mapping construction than existing tools.
Problem
Mapping SNN neurons to cores becomes more complex as networks grow, yet solution quality affects runtime performance.
Source: §1 · p. 1Method
The paper develops a GPU-accelerated SNN mapping pipeline with hardware-specialized hypergraph partitioning and placement initialized by recursive bisection.
Source: §1 · p. 1, Initial Placement · p. 4Results
The mappings achieve 0.58× energy consumption and 0.84× average spike delivery latency compared to the best SoTA tools, while mapping construction is 18–280× faster on a per-tool average.
Source: §1 · p. 1Takeaways & Limitations
The evaluated pipeline achieves the highest mapping quality among the evaluated SoTA baselines while reducing time-to-solution, with scalability positioned toward ever-growing networks.
Source: §6 · p. 6The multicast cost model uses a router-agnostic lower bound based on minimum Steiner trees, so concrete routers may incur higher costs.
Source: Placement Definition · p. 3
Abstract
from arXiv · showhide
SNNs running on neuromorphic hardware use spikes to achieve sparse and energy-efficient communication over a mesh of cores. In turn, system performance heavily depends on the assignment of neurons to cores: the mapping. Since hardware features inter-core multicast and intra-core replication of spikes, we model SNNs as hypergraphs to exploit both opportunities for reducing communication traffic. Mapping thus comprises two NP-hard problems: hypergraph partitioning and placement on the lattice of cores. High-quality solutions to both are critical, yet increasingly difficult as networks scale to millions of neurons. Therefore, we propose a GPU-accelerated pipeline for SNN mapping: a multi-level partitioning scheme is devised around hardware constraints, while placement is initialized through recursive bisection, followed by refinement pulling together strongly connected cores through repeated swaps. Model-based experiments show upwards of 16% lower latency and 42% lower energy for spike movements over existing sequential tools, while our parallel mapper is on average 18-280x faster.
1 Introduction
Mapping SNNs onto neuromorphic hardware becomes harder as networks grow, and mapping quality affects runtime performance. The paper proposes a GPU-accelerated pipeline that combines specialized hypergraph partitioning with placement and reports lower analytical communication costs and faster construction than existing tools.
1 Introduction
- SNN mapping assigns neurons to cores to reduce spike traffic; it separates into core-compliant hypergraph partitioning and placement of groups on cores.Partitioning minimizes the volume of spikes crossing groups, while placement minimizes the distance traveled.Source: §1 · p. 1
- Prior general-purpose tools do not support NMH costs and constraints, while specialized SNN mappers use faster, greedier heuristics and remain sequential CPU implementations.Scaling these tools to networks with millions of neurons could require days of execution time.Source: §1 · p. 1
- GPU algorithms handle partitioning at scale and explore many placements in parallel, enabling mappings of networks with hundreds of millions of synapses in minutes without sacrificing solution quality.Source: §1 · p. 1
- The authors describe the work as the first GPU-accelerated pipeline for mapping SNNs on neuromorphic hardware.Source: §1 · p. 1
- The pipeline introduces multi-level hypergraph partitioning tailored to NMH constraints and a multi-start placement routine initialized through recursive bisection.Source: §1 · p. 1
- 0.58× energy consumption and 0.84× average spike delivery latency versus the best SoTA tools, with mapping construction 18–280× faster on a per-tool average.Evaluations covered 12 SNNs ranging from 0.8M to 577M synapses.Source: §1 · p. 1
2 Preliminaries
SNNs communicate through spikes, and their network topology varies by how they are derived or trained. The paper models them as weighted directed hypergraphs and describes NMH as a core mesh with constraints and communication mechanisms relevant to mapping.
Spiking Neural Networks
- SNN neurons integrate incoming spikes and emit a spike along their axon after crossing a threshold; information is encoded by spike timing or rate.The network is asynchronous but simulated in discrete spike-propagation steps.Source: §2 · p. 1
- SNNs may be ANN-derived feedforward networks or natively trained networks with small-world structure, cycles, and dense neighborhoods.Source: §2 · pp. 1–2
Neuromorphic Hardware
- NMH uses a mesh of cores, with spikes communicated through inter-core multicast and replicated inside a core for multiple local destinations.Core arrangements may be a 2D lattice or toroid; the model also specifies per-core limits on neurons, incoming axons, and synapses.Source: Neuromorphic Hardware · p. 2, SNN and Hardware Models · p. 2
SNN and Hardware Models
- A SNN is represented as a weighted directed hypergraph: neurons are nodes, axons are hyperedges, and each hyperedge’s weight represents its spike frequency.Each hyperedge has one source, and each node has at most one outbound hyperedge.Source: SNN and Hardware Models · p. 2
3 The Mapping Problem
Mapping assigns SNN neurons to hardware cores to reduce spike traffic. It separates this task into partitioning neurons under core constraints and placing the resulting groups to reduce communication distance.
3 The Mapping Problem
- Partitioning forms disjoint neuron groups, minimizes weighted cut connectivity, and must respect per-partition hardware constraints.The model includes limits on partition size and distinct inbound h-edges.Source: Partitioning Definition · p. 2
- Placement injectively maps partitions onto hardware cores; its local costs include hop count and per-core transit probability.On a 2D lattice, distance is Manhattan distance.Source: Placement Definition · p. 2
- Analytical metrics abstract platform-specific execution: total energy captures spike traffic, average latency frequency-weights delivery completion time, and maximum congestion tracks peak routing pressure.Neuron-update energy is unaffected by mapping.Source: Placement Definition · p. 3
- A router-agnostic minimum Steiner-tree cost models multicast as a lower bound; exact Steiner costs are computed after mapping, while heuristics use hop and transit-probability proxies.Concrete routers may incur higher costs.Source: Placement Definition · p. 3
- Counting each h-edge cut once exposes intra-core spike replication, while placement costs encourage localized inter-core multicast.These hypergraph objectives capture communication behavior that graph-based SNN models underexploit.Source: Placement Definition · p. 3
4 GPU-based Mapping Pipeline
The GPU pipeline maps SNN hypergraphs through constraint-aware multilevel partitioning and placement on the core lattice. It uses recursive bisection for initial placement, then refines the layout through swaps between adjacent cores.
4 GPU-based Mapping Pipeline
- GPU traversal assigns outer node or hyperedge work to blocks and warps, while bounded inner traversals run cooperatively within warps.The approach confines sequential work to small neighborhoods, extracting most parallelism from the hypergraph’s outer dimensions.Source: §4 · p. 3
4.1 Partitioning
- The multilevel partitioner extends prior work to enforce all constraints Ω, Δ, and Φ through neighbor-counting and an event-based pipeline.It coarsens strongly connected nodes into super-nodes, then uncoarsens level by level while moving nodes to reduce cut hyperedges.Source: §4.1 · p. 3
- Coarsening forms disjoint pairs through a high-weight matching over a functional candidate graph, whose score structure yields a pseudoforest rooted at two-cycles.Threads walk to root two-cycles, acquire candidates with conflicts resolved by score, then retrace paths to match nodes whose acquisitions persist.Source: Coarsening · pp. 3–4
- Figure 3 distinguishes coarsening in green from uncoarsening and refinement in red, highlighting steps in the partitioning phases.The multilevel process merges strongly connected nodes before uncoarsening moves nodes between partitions.Source: §4.1 · p. 3, Figure 3 · p. 4
- During uncoarsening, nodes propose feasible moves based on the cut cost spared by leaving a partition minus the cost of entering another.Moves are ordered by gain; sparse events track constraint violations, and the algorithm applies the best improving prefix that remains valid.Source: Uncoarsening and Refinement · p. 4
4.2 Placement
- Initial placement projects the core lattice onto a Hilbert-curve sequence, then uses recursive bisection and tree-based orientation to order strongly connected nodes.Bisections use label propagation to reduce cut hyperedge weight; folding the tree orients sibling sections so strongly connected sides face each other.Source: Initial Placement · p. 4
- Placement refinement derives adjacent-core swap forces from both source-destination distances and destination locality within hyperedges.These terms target lower connection distance and encourage pin locality, supporting multicast and serving as a proxy for reducing hops.Source: Swap Proposals · pp. 4–5
- Symmetric tension combines the opposing forces on two adjacent cores; positive tension signifies that swapping them would reduce the distance covered by affected connections.The refinement matches proposed swaps, updates tensions in sequence to account for interference, and applies the best improving prefix until no swaps occur.Source: Swap Proposals · p. 5, Placement Refinement · p. 5
5 Experimental Evaluation
The evaluation compares GPU mapping against sequential tools on twelve SNNs, assessing partitioning, placement, and end-to-end mapping quality, runtime, and scalability.
Evaluation setup
- The study evaluates twelve public SNNs under size-matched hardware settings and a shared analytical communication model, with end-to-end wall-clock timings averaged over five runs.Benchmarks include acyclic feedforward and cyclic small-world networks; each placement method receives the same lowest-connectivity partition available.Source: §5 · pp. 5–6
Partitioning
- Compared with SNN mapping tools, our partitioning yields 1.3–15.9× lower connectivity; hMETIS and Mt-KaHyPar have 1.6× and 1.9× higher mean connectivity, respectively.Mt-KaHyPar does better on three occasions but produces tens of invalid partitions.Source: Figure 5 · p. 5, §5 · p. 6
Scalability
- Mapping time scales near-linearly with pin count; the 577M-pin MobileNet mapping takes a few minutes and peaks at 28GB of GPU memory.The scalability comparison is shown in Figure 6.Source: Figure 6 · p. 6, Results Discussion · p. 6
Placement
- With Π = 64, existing tools incur 1.02–1.75× energy, 1.02–1.76× average latency, and 1.04–2.96× maximum congestion versus our placement.Mt-KaHyPar sometimes achieves metrics up to 10% lower, but at prohibitively high execution times and with a limit of 64 lattice nodes.Source: Figure 7 · p. 6, §5 · p. 6, Results Discussion · p. 6
End-to-end mapping
- Across twelve SNNs, competing tools incur mean 1.72× energy, 1.18× average latency, and 1.98× maximum congestion versus our end-to-end mappings.For each SNN and metric, the comparison uses the best competing result normalized to ours.Source: Figure 8 · p. 6, Results Discussion · p. 6
Runtime
- Our approach is 25–2k× faster than sequential hMETIS and 3–15× faster than 16-thread Mt-KaHyPar.It is also 5× or faster than mapping tools that iterate over pins, and at most 6× slower than SNNcut’s single node iteration.Source: §5 · p. 6
6 Conclusion
The paper presents a GPU-accelerated SNN mapping pipeline that achieves the highest mapping quality among evaluated baselines while reducing time-to-solution.
Conclusion
- The work presents the first GPU-accelerated pipeline for mapping spiking neural networks on neuromorphic hardware.The authors report the claim as, to their knowledge, a first.Source: §6 · p. 6
- The pipeline achieves the highest mapping quality among evaluated state-of-the-art baselines while greatly reducing time-to-solution.Its scalability positions it to handle growing networks, with brain-scale systems as a long-term target.Source: §6 · p. 6
- The reported evaluation uses an analytical framework; evaluation on hardware platforms remains in progress pending integration with their software stacks.The tools are available as open-source.Source: §6 · p. 6