Source-linked AI summary

A 28nm 27,648-Spin Multichip Digital Ising Accelerator with Pegasus Connectivity

Tong Wu, Atharva Raut, Ian Khor, Ziyad Alswaidan, Ting-Yu Lee, Hongchang Kuang, Navid Anjum Aadit, Anand Raju, Dhruv Chinmay, Siddharth Das, Ken Mai, Kerem Camsari, Tathagata Srimani

arXiv:2609.07907v2cs.ARcs.ET

TL;DR

Scaling Ising hardware is constrained by coefficient storage and interconnect, while cross-chip state exchange can stall dependent updates. This 28 nm four-chip accelerator uses a 27,648-spin Pegasus graph with banked coefficient SRAM and overlapped boundary-state transfers. It reaches 30.24G peak updates/s at 140 MHz and 1.2 pJ/spin-update including I/O power, with 11.5× the throughput of a recent 28 nm multichip design.

  • Problem

    Scaling Ising accelerators is limited by coefficient storage and interconnect, while multichip state exchange can stall dependent updates and lower-connectivity graphs increase embedding overhead.

    Source: p. 1
  • Method

    A 28 nm four-chip accelerator combines a 27,648-spin Pegasus graph, banked coefficient SRAM, and boundary-state streaming that overlaps interchip transfers with independent updates.

    Source: pp. 1–2
  • Results

    The four-chip system reaches 30.24G peak updates/s at 140 MHz and 1.2 pJ/spin-update including I/O power, with 11.5× the throughput of a recent 28 nm multichip design.

    Source: p. 3
  • Takeaways & Limitations

    The same programmable datapath demonstrates MaxCut, spin glass, frustrated loops, factorization, and 3SAT.

    Source: p. 3

Abstract

from arXiv · show

We report a 28 nm four-chip Ising accelerator with 27,648 spins, degree-15 Pegasus connectivity, and 10b coefficients. Boundary-state streaming overlaps interchip transfers with spin updates, achieving 98.03% simulated weak-scaling efficiency. At 140 MHz, the four-chip system delivers 30.24G peak updates/s at 1.2 pJ/update including I/O power, with 11.5$\times$ the throughput and approximately one-quarter the logic-plus-SRAM area per spin of a prior 28 nm multichip design. We demonstrate MaxCut, spin glass, frustrated loops, factorization, and 3SAT.

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