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FlexSpIM: An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Hybrid Stationarity

Nicolas Chauvaux, Adrian Kneip, Charlotte Frenkel

arXiv:2609.08446v1cs.AR

TL;DR

CIM accelerators for SNNs lack flexibility across diverse workloads, motivating FlexSpIM’s reconfigurable operands and layer-wise hybrid stationarity. On the IBM DVS gesture dataset, it achieves 95.8% accuracy and enables energy and latency reductions of up to 45% and 52%.

  • Problem

    Existing CIM-based SNN accelerators have limited reconfigurability for diverse layer specifications, while membrane-potential storage adds to SCNN memory needs.

    Source: §I · p. 2

  • Method

    FlexSpIM uses reconfigurable weight and membrane-potential resolutions and shapes, unified storage, and layer-wise hybrid weight/output stationarity.

    Source: §I · p. 2, B. CIM Operation · p. 4

  • Results

    FlexSpIM reaches 95.8% accuracy on IBM DVS gesture while hybrid stationarity cuts energy up to 45% and latency up to 52% at 32 macros.

    Source: B. Results · p. 12, §VI · p. 13

  • Takeaways & Limitations

    System-level optimizations such as hybrid dataflow matter more than further CIM-macro optimization in the evaluated setting.

    Source: B. Results · p. 12

Abstract

from arXiv · show

Compute-in-memory (CIM) accelerators for spiking neural networks (SNNs) offer a promising solution for achieving $\mu$s-level inference latency and ultra-low energy in edge vision applications. However, their limited flexibility at both circuit and system levels restricts their deployment across diverse workloads. This work introduces FlexSpIM, a digital CIM architecture supporting arbitrary operand resolution and shape within a unified storage for weights and neuron states (i.e., membrane potentials). These circuit-level capabilities enable a layer-level hybrid weight- and output-stationary dataflow, maximizing operand reuse and reducing costly on- and off-chip data movement during SNN execution. Measurement results from a fabricated FlexSpIM prototype in 40-nm CMOS demonstrate competitive 1-bit-normalized energy efficiency and higher throughput compared with prior fixed-precision digital CIM-based SNN accelerators, while providing bitwise resolution reconfiguration. Evaluated on the IBM DVS gesture dataset, FlexSpIM achieves 95.8% accuracy while enabling up to 45% energy and 52% latency reductions in large-scale systems compared with fixed stationarity approaches.

I. INTRODUCTION

SCNNs suit sparse, latency-critical event vision, but persistent membrane potentials increase memory needs and existing CIM designs lack flexibility for diverse layers. FlexSpIM combines reconfigurable operands with layer-wise hybrid stationarity to reduce data movement.

I. INTRODUCTION

  • Although sparsity can reduce memory needs and bypass zero operations, exploiting sparsity above 90% at iso-accuracy remains an open challenge.The cited work reports up to 70% input sparsity and 80% weight sparsity without accuracy degradation on ImageNet.Source: §I · p. 1
  • DVS cameras generate events only when temporal contrast crosses a threshold, with active-pixel ratios typically below 1% to around 10% in the cited driving scenarios.The passage also reports sub-100-µs end-to-end event-generation latency.Source: §I · pp. 1–2
  • Membrane-potential storage can add 25–67% to the memory footprint of an equivalent CNN, making data movement a central SCNN challenge.The estimate assumes 8-bit weights and 16-bit membrane potentials; keeping all weights and states on-chip is impractical for large SCNNs.Source: §I · p. 2
  • FlexSpIM combines reconfigurable weight and membrane-potential resolution and shape with layer-wise weight/output stationarity to reduce operand movement.A unified weight/membrane-potential memory supports selecting the stationarity strategy per layer.Source: §I · p. 2
  • Prior CIM accelerators for SNNs have limited reconfigurability, constraining their fit to diverse layer specifications and potentially causing mapping penalties or application-specific hardware needs.FlexSpIM supports non-proportional weight and membrane-potential resolutions and operand shapes.Source: §I · p. 2

A. Spiking Neural Networks (SNNs)

The paper describes spiking neurons as stateful units that accumulate weighted input spikes in membrane potentials and emit spikes when those potentials reach a threshold.

A. Spiking Neural Networks (SNNs)

  • An integrate-and-fire neuron maintains a membrane potential over time, incremented by synaptic weights when input spikes arrive.The model relies on additions and comparisons rather than multiply-accumulate operations.Source: 1) Spiking neurons · p. 2
  • The membrane-potential update sums synaptic weights for spikes from the presynaptic neurons connected to neuron j.N is the number of presynaptic neurons, and O_i(t) denotes neuron i's spike train.Source: 1) Spiking neurons · p. 2
  • When a neuron's potential reaches its firing threshold, it emits an output spike and resets its potential; this work adopts reset by threshold subtraction.The passage states that threshold-subtraction reset was shown to increase accuracy.Source: 1) Spiking neurons · p. 2

2) SNN execution:

The section contrasts timestep-first and layer-first SNN execution, then explains why in-column CIM suits sparse SCNN workloads while in-array CIM suits dense CNN operations.

2) SNN execution:

  • Layer-first execution processes all layers for one timestep before advancing, lowering latency at the cost of higher memory traffic than timestep-first execution.Timestep-first execution can maximize weight and membrane-potential reuse when layers do not fit on-chip.Source: 2) SNN execution · p. 3

1) In-array vs. in-column CIM:

  • For dense CNN MVMs, in-array CIM is more efficient, while high sparsity can underutilize it and leave efficiency capped by ADC contribution.The passage notes that analog impairments or digital approximation can limit in-array computing accuracy.Source: 1) In-array vs. in-column CIM · p. 3
  • In-column CIM uses simultaneous wordline activation for operations between same-bitline operands, making it suitable for sparse event-based SCNN processing.In 6T SRAM, the array supports bitwise AND/OR operations, while peripheral circuits extend functionality to additions and multiplications.Source: 1) In-array vs. in-column CIM · p. 3

2) State-of-the-art CIM for SNNs:

Prior digital in-column CIM accelerators constrain operand resolutions and dataflow through fixed memory organizations. FlexSpIM uses a unified organization to support arbitrary operand resolutions, multiple dataflows, and full membrane-potential precision.

2) State-of-the-art CIM for SNNs:

  • IMPULSE supports a single set of weight and potential resolutions and weight-stationary execution; SpiDR supports only three precision modes and retains separate hardwired memory regions.IMPULSE interleaves potentials and sacrifices one potential bit for weight-sign extraction.Source: 2) State-of-the-art CIM for SNNs · pp. 3–4

III. PROPOSED DIGITAL CIM MACRO

  • FlexSpIM reshapes membrane potentials into a 6 × 2 bitcell structure for bidirectional carry propagation, eliminating interleaving while supporting arbitrary operand resolutions and multiple dataflows.Its unified organization is agnostic to whether weights or potentials are stored.Source: §III · p. 4
  • The top-level architecture comprises a 16 kB digital CIM-SRAM macro, a 4.25 kB spike input buffer, and a reshaped 16-bank weight/potential buffer.The weight/potential buffer has 2 kB per bank.Source: §III · p. 4

A. CIM-SRAM Overview

  • The macro uses a 512 × 256 6T-SRAM array with per-column peripheral circuits that extend in-column bitwise logic into precision-flexible operations.Three additional bitcells per column store 2-bit PC configuration and 1-bit emulated PC control; a dual address decoder supports full- and half-span wordline controls.Source: A. CIM-SRAM Overview · p. 4

B. CIM Operation

FlexSpIM supports weight-stationary and output-stationary execution using the same CIM macro and peripheral resources. Each layer configures its operands and dataflow, then reuses the loaded non-stationary operand during accumulation.

B. CIM Operation

  • Both weight-stationary and output-stationary execution keep one operand stationary while the other updates, using weights or membrane potentials as the stationary operand, respectively.The shared CIM macro stores only weights and membrane potentials because input spikes directly activate wordlines.Source: B. CIM Operation · p. 4
  • After initialization, accumulation repeats with non-stationary operand updates as needed until the current layer and timestep’s events are processed.Membrane potentials are thresholded and reset after all events in OS, but after each neuron’s last accumulation event in WS.Source: B. CIM Operation · p. 4
  • Operations share six phases controlled by an FSM clocked up to 1.2 GHz, with programmable phase durations and fine-grained read timing.At least four cycles are required across the phases; read/CIM duration can also be adjusted for operand resolution.Source: B. CIM Operation · pp. 4–5

1) Configuration setup:

  • For each layer, FlexSpIM configures PC control bitcells for the operands and dataflow before initializing the stationary operand.Configuration data arrive through the macro I/O interconnect and use only the write phases.Source: 1) Configuration setup · p. 5

2) Operands initialization:

  • Stationary operands occupy the full address range, while non-stationary operands are stored at the memory bottom and updated between layers or timesteps as needed.Stationary operands are written once and reused across layers and timesteps.Source: 2) Operands initialization · p. 5

3) Synaptic weight accumulation:

FlexSpIM supports bit-serial and bit-parallel accumulation, with configurable operand reshaping and carry propagation across peripheral circuits. Its configuration permits arbitrary operand block dimensions and operand resolutions.

3) Synaptic weight accumulation:

  • Latch-based sense amplifiers with separate bitline and bitline-bar reference voltages support reliable Boolean readout despite the limited voltage swing imposed by disturbance risk.At 0.8 V, the reported reference-level margin is 135 mV; the analysis uses post-layout Monte Carlo read-stability simulations.Source: 3) Synaptic weight accumulation · p. 6, Figure 7 · p. 6
  • In bit-serial weight-stationary accumulation, one operand bit is processed per cycle from the LSB, and each sum bit overwrites the processed output bit.A dedicated PC register stores the generated carry for use as the next cycle’s carry-in; output-stationary execution swaps operand positions.Source: 3) Synaptic weight accumulation · p. 6
  • In the 12-bit example, reshaping operands into 4 × 3 blocks processes one SRAM row per cycle, reducing addition latency from 12 to 3 cycles.Carries propagate between neighboring PCs, left-to-right on even rows and right-to-left on odd rows.Source: 3) Synaptic weight accumulation · p. 6
  • The sign-bit extension mechanism propagates the weight sign bit, overflow and underflow indicators, and spike value to current and neighboring PCs.SOUS carries these signals; CMDLR selects its left or right source, while CMDSS selects between SIGN and REGV.Source: Figure 10 · p. 7
  • Configurable carry direction, initial carry-in, and bit-serial operation enable arbitrary operand block width and height, and therefore arbitrary operand resolution.This differs from prior works with fixed-width operands and static mapping patterns, [31].Source: 3) Synaptic weight accumulation · p. 7

4) Sign-bit extension:

FlexSpIM handles sign extension differently for output- and weight-stationary execution to avoid an extra sign-bit read. It also provides near-memory overflow/underflow detection and correction, with reported memory and accuracy comparisons on IBM Gesture.

4) Sign-bit extension:

  • For output-stationary execution, the weight sign bit is stored in a PC register; for weight-stationary execution, it is recovered from signals when the last weight row is processed.The extracted sign bit is latched, then propagated across block PCs during sign-extension cycles.Source: 4) Sign-bit extension · p. 7
  • Reading the sign bit before every accumulation could add up to 50% energy and latency in the block-height-two configuration.FlexSpIM’s mechanism avoids that extra memory access.Source: 4) Sign-bit extension · p. 7

5) Overflow/Underflow protection mechanism:

  • Up to 30% less convolutional-layer memory without accuracy loss is reported against analog CIM SNN accelerators; FlexSpIM also achieves higher accuracy than IMPULSE at a given network size, or the same accuracy with 24% less memory.The comparisons concern the IBM Gesture SCNN and configurable operand resolutions.Source: 5) Overflow/Underflow protection… · p. 7, Figure 11 · p. 8
  • FlexSpIM adds a near-memory shared overflow/underflow detector and fine-grained correction to address quantization-related potential corruption and accuracy loss.After accumulation, the detector checks for overflow or underflow; if detected, execution stalls and inserts correction steps for each condition.Source: 5) Overflow/Underflow protection… · pp. 7–8

6) Membrane-potential comparison and spike generation:

FlexSpIM compares membrane potentials with their thresholds after each timestep and supports threshold broadcasting as an alternative to storing thresholds in the CIM macro. Spike generation and reset update only the relevant neurons.

6) Membrane-potential comparison and spike generation:

  • After all timestep spikes are processed, membrane potentials can be reset to 0, reduced by the threshold, or overwritten with another configured value.Figure 13 contrasts conventional in-memory threshold storage with shared horizontal interconnections and depicts the cycle-level comparison.Source: 6) Membrane-potential comparison and… · p. 9, Figure 13 · p. 9
  • Threshold broadcasting uses horizontal interconnects and extension bits to emulate threshold bits, saving 3kb bit (3%) of CIM storage for a fully bit-serial 16-bit potential/threshold configuration.Broadcast supports 1-, 2-, 4-, 8-, and 16-way modes; other operand shapes require threshold storage in memory or additional interconnect resources.Source: 6) Membrane-potential comparison and… · p. 9
  • When a neuron spikes, an underflow in the comparison signals spike generation; the SPIKE signal is stored in REGV and forwarded to the controller.During reset, only PCs associated with SPIKE = 1 update their membrane potential.Source: 6) Membrane-potential comparison and… · p. 9

C. Comparison to the State of the Art

FlexSpIM trades some standalone macro energy efficiency for flexibility, with the authors arguing that this penalty becomes negligible at system level. Its layer-wise hybrid stationarity and mapping stack target system-level data movement and diverse macro budgets.

C. Comparison to the State of the Art

  • FlexSpIM's increased flexibility incurs energy and latency overheads versus rigid architectures, but the authors report that the energy-efficiency penalty becomes negligible at system level.They identify flexibility as a more important driver of system-level efficiency than macro-level energy metrics.Source: C. Comparison to the State of the Art · p. 9

IV. SYSTEM-LEVEL DESIGN SPACE EXPLORATION AND SOFTWARE STACK

  • FlexSpIM's key system-level advantage is reducing data movement, which can outweigh standalone macro efficiency: prior work reported a 10× system-level energy-efficiency loss from transfers and an additional 2× penalty when weights did not fit on chip.For layer-first SCNN execution, sparse activations further increase transfer overhead as weight reuse falls.Source: §IV · p. 9

A. Hybrid-Stationary Dataflow

  • Hybrid stationarity selects weight or output stationarity per layer: the six-layer SCNN needs five macros to store all weights, while min-memory hybrid stationarity keeps one operand per layer stationary with two macros.With enough macros, max-memory hybrid stationarity keeps the largest-footprint operand stationary for each layer.Source: A. Hybrid-Stationary Dataflow · p. 9
  • The software stack searches mappings and execution configurations for each layer, then jointly optimizes the resulting mappings across CIM macros for estimated energy and latency.Its inputs include hardware capacity, bandwidth, access energy, and macro count.Source: A. Hybrid-Stationary Dataflow · p. 10

B. Single-Layer Performance Exploration

The exploration separates spatial physical mappings from temporal intra-layer schedules, using analytical ZigZag for rapid schedule search and unrolled ZigZag for cycle-accurate evaluation of selected mappings.

B. Single-Layer Performance Exploration

  • Physical mappings vary dataflow, parallelization, and operand shape; wider bit-parallel mappings raise bandwidth pressure, while more vertical bit-serial mappings can raise latency.The objective is workload-level co-location, so diverse mappings matter even when a mapping is not optimal for an individual layer.Source: B. Single-Layer Performance Exploration · p. 10
  • Intra-layer scheduling sets temporal execution order within a fixed spatial mapping, such as processing all inputs for one neuron before moving to the next.The section evaluates schedules with analytical and cycle-accurate simulators.Source: B. Single-Layer Performance Exploration · pp. 10–11

1) Analytical ZigZag:

  • Analytical ZigZag extends the model with timesteps, persistent membrane potentials, and input sparsity, but its homogeneous-spike assumption can reduce energy and latency estimate accuracy.For 93.75% input sparsity, localized spikes activate 11% of output neurons, while uniform spikes activate all; the homogeneous assumption upper-bounds membrane-potential fetches.Source: 1) Analytical ZigZag · p. 11

2) Unrolled (cycle-accurate) ZigZag:

  • Unrolled ZigZag executes real input data cycle by cycle for more accurate estimates, but its runtime makes exhaustive evaluation impractical.Analytical ZigZag selects the best schedule per physical mapping, reducing the search from billions of configurations to a few hundred mapping evaluations.Source: 2) Unrolled (cycle-accurate) ZigZag · p. 11

C. Multi-Layer Mapping Optimizer

The multi-layer optimizer packs layer mappings into the available CIM macros, and the system evaluation finds that hybrid stationarity yields the strongest trade-off across macro budgets. In the tested SCNN, it reduces energy and latency at scale while transfers remain a major energy cost.

C. Multi-Layer Mapping Optimizer

  • The optimizer formulates macro placement as rectangle packing and uses MaxRects Bottom-Left; with two macros, hybrid stationarity keeps all six SCNN layers fully stationary, unlike OS-only and WS-only.It searches feasible combinations of one physical mapping per layer.Source: C. Multi-Layer Mapping Optimizer · p. 11

A. Experimental Setup

  • The system combines DRAM, input and non-stationary operand buffers, and a configurable CIM array; the non-stationary buffer holds membrane potentials for WS or weights for OS.Its adaptive buffer bandwidth ranges from 32 to 256 bits and connects to the array through a 256-bit single-cycle bus.Source: A. Experimental Setup · pp. 11–12

B. Results

  • At 32 macros, HS achieves up to 52% latency and 45% energy reduction, reaching 105µs and 6.4µJ per timestep versus 291µs and 15.8µJ with one macro, across SCNN layers on DVS128.The measurements are for a single 10 ms timestep at 157 MHz on the IBM DVS gesture dataset; HS offers the best trade-off across macro budgets.Source: Figure 16 · p. 11, B. Results · p. 12
  • At 39 macros, energy use remains 4× higher than the CIM macro itself, showing system-level optimizations such as hybrid dataflow matter more than further CIM macro optimization.Source: B. Results · p. 12

C. Discussion

FlexSpIM reports model-size and system-level gains in its conclusion. The discussion evaluates whether analytical ZigZag preserves schedule choices and rankings under cycle-accurate evaluation, while identifying limits to that validation.

C. Discussion

  • Analytical and unrolled estimates diverge more under WS because OS keeps membrane potentials in CIM macros and is less sensitive to spike distribution; validity requires preserving the cycle-accurate optimal schedule.Source: C. Discussion · p. 12
  • Across sampled physical mappings, most analytical-selected schedules were near-optimal; six had latency deviations up to 36%, while the NS buffer limited costly DRAM-access errors.The validation sampled 100 schedules per mapping; repeating that comparison for every layer was computationally prohibitive.Source: C. Discussion · p. 12
  • After excluding performance differences below 1%, Kendall’s τb correlation improves, confirming analytical ZigZag preserves candidate-schedule ordering despite the homogeneous spike-distribution assumption.Source: C. Discussion · p. 12
  • Across the workload, physical-mapping rankings correlate above 88%, supporting two-stage exploration without repeating 100-schedule checks for every layer.Source: C. Discussion · p. 12

VI. CONCLUSION

  • FlexSpIM reduces model size by 30% versus state-of-the-art CIM approaches while maintaining 95.8% accuracy on IBM DVS gesture, and improves system energy and latency by up to 45% and 52% versus rigid stationarity approaches.Source: §VI · p. 13

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