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SCALE-X: A Systematic Complexity-Aware Low-Precision Approach for Digital Predistortion
Anees Rehman, Mohd Tasleem Khan, George Goussetis, Yuan Ding, João F. C. Mota, Jaiyu Hou
TL;DR
Power-amplifier DPD must meet demanding linearization targets while fitting finite FPGA resources, and the impact of constrained coefficient fitting on fixed-point DPD remains underexplored. SCALE-X combines complexity-aware coefficient pruning with optimized fixed-point modeling; its FPGA implementation uses 4× fewer DSPs than at comparable throughput.
Problem
DPD must provide high-fidelity linearization within finite FPGA resources, while the impact of constrained least-squares fitting on fixed-point DPD remains largely unstudied.
Source: §I · p. 1Method
SCALE-X prunes low-impact anti-diagonal memory-polynomial coefficients and jointly optimizes pruning with signed fixed-point wordlength to balance complexity and linearization performance.
Source: §I · p. 1, §II · pp. 2–3Results
At r*=5, the Zynq implementation uses 25 DSPs and achieves the lowest ENS/TP (10.8) among compared designs; DSP usage is 4× lower than at comparable throughput.
Source: B. Performance Comparison · p. 4Takeaways & Limitations
Joint configuration of model order, memory depth, and coefficient bitwidth reduces computational complexity while preserving linearization performance, with FPGA results confirming resource reductions and practical trade-offs.
Source: §IV · p. 5
Abstract
from arXiv · showhide
This letter presents SCALE-X, a systematic, complexity-aware, low-precision, model-based digital predistortion (DPD) technique for power amplifiers with enhanced capabilities. The proposed approach employs a novel complexity-aware coefficient pruning method, which, when combined with optimized fixed-point modeling, enables more accurate capture of quantization effects and supports better informed decisions for implementation. Targeted configuration of model order, memory depth, and coefficient bitwidth delivers dramatic cuts in computational overhead without much sacrificing accuracy. Field-programmable gate array implementation demonstrates practical trade-offs with improved overall efficiency.
I. INTRODUCTION
The introduction frames high-fidelity DPD on resource-constrained platforms as a growing challenge as communication requirements tighten. SCALE-X addresses the lack of a unified fixed-point quantization and coefficient-pruning approach with joint complexity-aware modeling and FPGA implementation.
I. INTRODUCTION
- Finite FPGA resources make it challenging to maintain high-fidelity DPD as communication systems face tighter linearization targets.The introduction cites 3GPP 5G NR targets of ≥45 dBc ACLR and 3.5–8% EVM.Source: §I · p. 1
- Higher polynomial order or memory depth enlarges model coefficient sets and computational cost, while the impact of constrained least-squares fitting on fixed-point DPD remains largely unstudied.Memory polynomial DPD is described as a favorable trade-off between linearization performance and implementation complexity.Source: §I · p. 1
- SCALE-X addresses the absent unified treatment of fixed-point quantization and coefficient pruning by combining complexity-aware pruning, quantization-aware modeling, and FPGA realization.The introduction presents this combination as delivering a superior accuracy–complexity trade-off for resource-constrained DPD.Source: §I · p. 1
- Anti-diagonal pruning removes low-impact, high-order, long-memory terms, while joint pruning and wordlength optimization targets efficient accuracy–complexity trade-offs.The proposed approach is implemented on a Zynq UltraScale+ RFSoC and reports reduced logic utilization and improved overall efficiency.Source: §I · p. 1
II. PROPOSED SCALE-X FRAMEWORK
SCALE-X reduces the MP-DPD coefficient set through progressive anti-diagonal pruning, re-estimating the surviving coefficients at each stage. It jointly selects a feasible pruning stage and fixed-point format for implementation.
II. PROPOSED SCALE-X FRAMEWORK
- Equation (2) requires MK multiplications, compared with M(2K−1) for the alternative formulation, while both retain MK coefficients and identical NMSE, ACLR, and EVM performance.The systematic representation uses Horner’s rule to reduce multiplications.Source: §II · p. 2
- Anti-diagonal pruning progressively removes coefficients toward the bottom-right of C, where larger memory indices and nonlinear orders contribute least to linearisation.At stage r, the pruned anti-diagonal is defined by m + k = M + K − 1 − r.Source: §II · p. 2
- At each pruning stage, constrained LS re-estimates the active coefficients; pruning stops when NMSE, EVM, or ACLR violates its limit, selecting the previous feasible stage.The active regression matrix includes only coefficients not in the cumulative pruned set.Source: §II · p. 2
- The framework applies signed QI.F fixed-point quantization to intermediate products and jointly optimizes integer and fractional bits with the pruning stage.Wordlength is W = I + F bits, with I integer bits including sign and F fractional bits.Source: §II · p. 3
- The FPGA architecture maps delayed input samples to rows and nonlinear orders to basis functions, then multiplies, quantizes, and accumulates terms before summing across memory taps.Red coefficients mark the pruned anti-diagonals.Source: Figure 2 · p. 2, §II · p. 3
A. Performance Evaluation
The evaluation identifies a joint pruning and fixed-point operating region that preserves near-floating-point linearization, while showing that anti-diagonal pruning retains performance better than matrix-size reduction. FPGA measurements also show reduced resource use and power without a throughput penalty.
A. Performance Evaluation
- M = 3 and K = 7 sustains near-floating-point ACPR (−59.63 dBc), EVM (0.088%), and NMSE (−57.63 dB) down to roughly 12–14 coefficients.All three metrics degrade sharply beyond that coefficient count.Source: A. Performance Evaluation · p. 3
- At roughly 12–14 coefficients and 12–13 bits, pruning and fixed-point quantization combine with negligible compounding loss.Below roughly 12–13 bits, quantization noise increasingly drives divergence from the floating-point baseline.Source: A. Performance Evaluation · pp. 3–4
- At matched coefficient counts, anti-diagonal pruning achieves lower out-of-band PSD than direct matrix-size reduction across all four operating points.The gap is largest at higher coefficient counts and narrows as coefficients are reduced.Source: A. Performance Evaluation · p. 4
- At r = 5, ENS falls from 7856 to 4042 (48.6% reduction), dynamic power drops from 218 to 177 mW, and throughput remains 375 Msps.DSP usage falls from 50 to 25; the FPGA resource comparison is reported in Table I.Source: A. Performance Evaluation · p. 4, Table I · p. 4
B. Performance Comparison
The FPGA comparison reports the pruned SCALE-X design's resource and throughput-normalized efficiency against existing implementations. The proposed design has the lowest reported ENS/TP, though comparisons with a full multi-stage system have a scope difference.
B. Performance Comparison
- At 12-bit Q1.11 precision, r∗ = 5 uses 25 DSPs and 0 BRAMs, draws 177 mW at 375 Msps, and has the lowest ENS/TP (10.8) among compared designs.The result is reported for the Zynq UltraScale+ RFSoC ZU48DR.Source: B. Performance Comparison · p. 4
- At 12-bit (Q1.11) precision, the proposed design on the Zynq UltraScale+ RFSoC ZU48DR uses 25 DSPs at 375 Msps and, relative to, achieves a 4× reduction in DSP usage at comparable throughput.Against, the DPD-only implementation occupies a small fraction of the resources required by its full multi-stage system; does not separately report DPD-only resource usage.Source: B. Performance Comparison · p. 4
- The authors characterize SCALE-X as the most favorable balance across model complexity and hardware efficiency, supporting resource-constrained DPD deployment.Source: B. Performance Comparison · p. 4
IV. CONCLUSION
SCALE-X combines coefficient pruning with optimized fixed-point modeling and jointly configures model order, memory depth, and coefficient bitwidth. The conclusion reports reduced complexity with preserved linearization performance and identifies broader model support as future work.
IV. CONCLUSION
- SCALE-X combines coefficient pruning with optimized fixed-point modeling to capture quantization effects and guide efficient design.Source: §IV · pp. 4–5
- Jointly optimizing model order, memory depth, and coefficient bitwidth reduces computational complexity while preserving linearization performance.Source: §IV · p. 5
- FPGA results confirm reduced hardware resource usage with practical trade-offs; extending the approach beyond MP-based DPD models is future work.Source: §IV · p. 5