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OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology
Yang Chen, Daniele Storelli, Xinyi Zhao, Ankit Bende, Paul-Philipp Manea, Oliver Artner, Arun Ashok, Kay Winterberg, Godwin Paul, Siyuan Jia, Christian Roth, Sabitha Kusuma, Michael Schiek, Vikas Rana, Dirk Wouters, Stephan Menzel, Andre Zambanini, Christian Grewing, Stefan Wiefels, Susanne Hoffmann-Eifert, John Paul Strachan, Stefan van Waasen, Regina Dittmann
TL;DR
RRAM-based computing needs fine current control during SET without sacrificing reliable RESET, requirements that can conflict in a single access transistor. OTTER introduces a 28 nm CMOS platform with a parallel HD–LD 2T1R cell and evaluates its switching and programming. The reported characterization shows complementary SET and RESET roles, with sizing guidelines and finer SET programming using the LD transistor.
Problem
A single access transistor must limit current for SET yet provide enough drive for RESET, creating conflicting design demands for reliable multilevel RRAM programming.
Source: §1 · p. 2Method
OTTER co-integrates TaOx RRAM with 28 nm CMOS and characterizes a parallel, independently addressed HD–LD 2T1R cell using experiments and JART VCM Rth simulations.
Source: §1 · p. 2Results
The HD transistor provides reliable RESET across tested bias conditions, while the LD transistor enables finer SET programming; combined measurements and simulations yield RESET-transistor sizing guidelines.
Source: §7 · p. 18Takeaways & Limitations
The 2T1R platform provides independent SET and RESET current paths and is used to investigate device- and array-level CAM and CIM operation.
Source: §7 · p. 18The sizing simulations provide indicative trends, their absolute values warrant caution, and direct experimental verification of the proposed transistor-level mechanisms remains ongoing.
Source: §6.2 · p. 12
Abstract
from arXiv · showhide
This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.
1 Introduction
RRAM supports analog programming for both content-addressable and compute-in-memory operations, but its transistor must balance SET current control against RESET drive. OTTER explores a parallel HD–LD transistor pair to decouple these requirements and characterizes the resulting platform and operation.
1 Introduction
- Filamentary VCM RRAM changes conductance through donor relocation; SET raises conductance and RESET lowers it.SET requires precise current control, and arrays need a selective element to suppress sneak currents.Source: §1 · p. 2
- A series access transistor can impede RESET through voltage division, while broad multilevel programming calls for fine SET current control.The proposed 2T1R cell places independently addressable HD and LD transistors in parallel with the RRAM to separate these demands.Source: §1 · p. 2
- OTTER is a 28 nm CMOS platform co-integrated with TaOx RRAM, with 2T1R test structures and CAM and CIM arrays.The paper reports systematic 2T1R characterization spanning DC sweeps, pulse-based multilevel programming, and array-level CIM, with sizing guidelines supported by JART VCM Rth simulations.Source: §1 · p. 2
2 Design
OTTER combines a parallel-transistor 2T1R cell with CAM and CIM arrays to investigate memory and computing configurations. Its cell and array designs trade programming control and selectivity against analog computation functionality.
2.1 2T1R structures
- The 2T1R cell pairs a W/L = 10 HD transistor with a W/L = 2 LD transistor in parallel, each independently addressed through its own word line.The HD transistor supports RESET drive, while the LD transistor supports finer SET current control.Source: §2.1 · p. 2
2.2 CAM arrays
- An aCAM cell matches inputs within a stored conductance-defined interval, while a shared NOR match line marks the word as mismatched if any cell mismatches.The chip-level design includes both comparator orientations and evaluates their aCAM-specific trade-offs through simulation.Source: Figure 2 · p. 3, §2.2 · p. 4
- The aCAM comparator encodes an analog decision boundary in memristor conductance, with top- and bottom-connected orientations exposing different body-effect trade-offs.The two 8 × 8 arrays use distinct comparator orientations; the chip also varies cell architectures by row and implements NOR- and NAND-type match lines.Source: §2.2 · p. 4
2.3 CIM arrays
- The pseudo-crossbar CIM array supports analog VMM through current summation on shared lines, but reduced selectivity complicates programming.The conventional array provides precise cell selection and controlled programming, and both arrays span 15 × 15 2T1R structures.Source: §2.3 · pp. 4–5
3 TaOx based VCM device integration on 28 nm CMOS chip
The OTTER chip integrates TaOx RRAM devices with 28 nm CMOS using a CMOS-compatible back-end process. The passage describes the device dimensions, layer stack, and fabrication sequence.
3 TaOx based VCM device integration on 28 nm CMOS chip
- The 200 nm × 200 nm Pt/7 nm TaOx/13 nm Ta/Pt RRAM devices were integrated on a 28 nm TSMC CMOS chip (36 mm2) using approximately thirty BEOL-compatible steps below 300 °C.The NMOS transistors have W/L = 2 (LD) and W/L = 10 (HD).Source: §3 · p. 5
- The RRAM stack comprises a 25 nm Pt active electrode, 7 nm TaOx switching layer, 13 nm Ta ohmic electrode, and 25 nm Pt capping layer.The switching region is defined by a reduced-TaOy conductive plug and the disc area; oxygen exchange with the Ta electrode changes the local average Ta valence.Source: Figure 4 · p. 5
- Fabrication patterns the contact pads and bottom electrode before depositing and patterning the TaOx, Ta, and Pt top-electrode stack.Connector bars are then formed to connect the RRAM electrodes to their contact pads.Source: §3 · p. 6
4 Experimental
The experimental protocol compares transistor pairings for 2T1R switching and uses pulse training to assess multilevel programming. It defines readout conditions and the SET/RESET bias sequences used in those measurements.
4.1 2T1R Characterization
- Read current is measured using the HD transistor and calculated from the central 60% of each read pulse, excluding its leading and trailing edges.The measurement setup uses five probe contacts, including separately addressed HD and LD word lines and a bulk terminal.Source: §4.1 · pp. 6–7
- Three configurations separate or combine SET and RESET drive: HD–HD, LD–LD, and LD–HD, with triangular sweeps applied to the bit line during SET and source line during RESET.Each configuration uses a 0.2 V bit-line, 3.3 V HD-word-line, 10 µs read pulse after SET and RESET; the transistor bulk is grounded during measurements.Source: §4.1 · pp. 6–7
- Pulse training compares HD and LD SET protocols under IGVVA, with the HD transistor exclusively driving RESET in both cases.SET pulses last 1 µs and are followed by 10 µs read pulses; the sequences use 29 HD SET pulses or 65 LD SET pulses, then reset the device to its high-resistance initial state.Source: §4.1 · pp. 7–8, Figure 6 · p. 7
- The experimental section identifies Table 1 as the reference parameter set for the JART VCM Rth compact model.The model parameters are used in circuit-level switching simulations.Source: Table 1 · p. 8
5 Compact Model
The compact model extends JART VCM with state-dependent thermal resistance and couples vacancy evolution to Joule heating. Its calibration accommodates device and cycle variability across switching conditions.
5 Compact Model
- JART VCM Rth extends predecessor JART VCM v1b with a state-dependent effective thermal resistance.Source: §5 · p. 8
- Oxygen-vacancy evolution is modeled as thermally activated ionic transport, while Joule heating determines local filament temperature.The temperature relation uses voltage drops across the disc, plug, and Schottky barrier, total current, effective thermal resistance, and ambient temperature.Source: §5 · p. 8
- The model couples vacancy concentration, effective thermal resistance, and filament temperature to describe gradual multilevel switching.During SET, Rth,eff decreases as Ndisc rises, moderating thermal runaway; during RESET, Rth,eff increases, producing gradual current reduction consistent with experiments.Source: §5 · p. 8
- The access transistor uses a calibrated PDK compact model, with ldisc, ∆WA, and Nmin adjusted to represent device-to-device initial-state variation.Other physical parameters remain fixed at reference values.Source: §5 · p. 8
- Rth coefficients are calibrated separately for each switching configuration and gate-bias condition, with reference values and ranges reported in Table 2.Source: §5 · p. 9, Table 2 · p. 9
- Nmin, Rfil, and lnew follow bounded multiplicative random walks between switching cycles to reproduce statistical resistance-state variation.The bounds are specific to each switching configuration and gate-bias condition.Source: §5 · p. 9
6 Results
The results characterize OTTER’s 2T1R switching, sizing, and pulse-programming behavior and evaluate a simulated aCAM and crossbar MAC operations. They also report measured-current binary-dot-product MAC performance across 5,000 operations, including accuracy and linearity across transistor configurations.
6.1 2T1R Switching Characterization
- LD–HD switching achieves complete RESET and on/off ratios above 5 across SET biases, while LD–LD RESET degrades and fails at higher compliance because of access-transistor voltage drop.In LD–LD, about 50% of cycles fail to return to HRS at 2.2 V SET WL (Icc ≈175 µA), and RESET fails in most cycles at 2.4 V (Icc ≈200 µA); LD–HD remains reliable under those conditions. HD–HD also provides consistent binary switching with on/off ratios above 5.Source: §6.1 · pp. 9–11, Figure 7 · p. 10
6.2 Design Guidelines for Transistor Sizing
- Simulations indicate that deeper programmed LRS states require larger RESET-transistor W/L, while increased maximum source-line voltage helps at intermediate states but has limited benefit for deep states.The reported sizing trends are indicative, and absolute values warrant caution; the proposed explanation is that transistor saturation limits RESET drive, with body effect potentially worsening the limitation at smaller W/L.Source: §6.2 · pp. 11–12
6.3 Pulse-Based Multilevel Programming
- 65 distinguishable LD-SET levels span approximately 10 µA to 85 µA, versus 29 HD-SET levels over a comparable range; LD-SET also yields narrower, better-separated target distributions.Across six target levels from 30 µA to 80 µA, LD-SET distributions show no measurable overlap between adjacent levels, while the three lowest HD-SET levels visibly overlap. The two protocols have comparable variability across the full programming range, but LD-SET has lower variability at each of the six target levels.Source: §6.3 · pp. 13–14, Figure 11 · p. 15
6.4 Content Addressable Memory (CAM)
- 1.240 V versus 0.965 V dynamic range and 2.2% versus 13.9% mean normalized supply-induced error favor the simulated top-connected aCAM configuration.The comparison is top-connected versus bottom-connected, respectively, under nominal 0.60 V supply with ±10% variation; experimental chip measurements are underway.Source: §6.4 · pp. 15–16, Figure 13 · p. 16
6.5 Compute-in-Memory MAC Operation
- The hardware MAC study uses a fabricated 15 × 15 2T1R crossbar and evaluates four SET-programming/MAC-read transistor configurations with five binary weight patterns.Each pattern is tested with 1,000 randomly generated binary input vectors; RESET uses the HD transistor, and the supplied passages describe the evaluation setup rather than MAC accuracy results.Source: §6.5 · pp. 16–17
- LD–LD achieves the lowest RMSE (2.27 µA) and highest R2 (0.9996), while HD–HD has the highest RMSE (7.37 µA) and lowest R2 (0.9982).Figure 14 compares measured MAC current with ideal digital output across the transistor configurations; Table 3 summarizes the accuracy metrics.Source: Figure 14 · p. 17, §6.5 · p. 17, Table 3 · p. 18
- LD–LD’s improved programming accuracy and comparable LD on-resistance and programmed RRAM LRS reduce read-current variability, supporting accurate MAC operations.The paper identifies the LD transistor as beneficial for both precise conductance programming and accurate CIM MAC operations.Source: §6.5 · pp. 17–18
- LD–LD has a lower MAC gain, with a slope of 43.16 µA/bit, but readout-circuit calibration can compensate for the reduction.Source: §6.5 · p. 17
- Measured MAC current was compared with ideal digital output across 5,000 operations, using MAE, RMSE, R2, and fitted slope to assess accuracy, linearity, and gain.Each MAC corresponds to the binary dot product between the input and weight vectors.Source: §6.5 · p. 17
7 Conclusion
OTTER integrates TaOx RRAM with 28 nm CMOS to investigate 2T1R cells and CAM/CIM arrays. The conclusion highlights independent SET/RESET control, finer LD-based programming, transistor-sizing guidance, and array-level MAC results.
7 Conclusion
- OTTER co-integrates TaOx RRAM with 28 nm CMOS and includes dedicated 2T1R test structures plus CAM and CIM arrays.The platform supports evaluation of switching behavior and application-level functionality.Source: §7 · p. 18
- The LD–HD pairing separates SET and RESET paths: HD provides reliable RESET, while LD enables finer SET programming.The HD transistor supports RESET across bias conditions; LD SET produces tighter target-level distributions and reduced inter-level overlap than HD SET, despite comparable intrinsic cycle-to-cycle variability.Source: §7 · p. 18
- Sizing guidelines establish the minimum RESET-transistor W/L needed for complete RESET as a function of SET current compliance.The guidelines draw on DC sweep measurements and compact-model simulations.Source: §7 · p. 18
- Among four MAC transistor combinations, using LD for both SET and readout achieves the lowest RMSE and highest linearity.Exemplary MAC operations were demonstrated through the CIM1 pseudo-crossbar array.Source: §7 · p. 18
- The aCAM analysis evaluates trade-offs between top- and bottom-connected RRAM comparator configurations on the same platform.Source: §7 · p. 18