Source-linked AI summary
AccelMPC: High-Rate, Low-Power FPGA-Accelerated Model Predictive Control for Tiny Drones
Andrea Grillo, Brian Plancher
TL;DR
Tiny aerial robots require fast constrained control, but existing cached MPC solvers cannot reliably sustain high rates on resource-constrained platforms. AccelMPC co-designs an FPGA-accelerated ADMM solver with numerical representation, hardware mapping, and a custom PCB, achieving 1 kHz onboard constrained MPC with improved speed and energy-delay performance.
Problem
Resource-constrained tiny robots need high-rate constrained MPC, while prior cached solvers are forced to operate at reduced control rates when constraints require more iterations.
Method
AccelMPC uses end-to-end co-design of an FPGA-accelerated ADMM MPC solver, numerical representation, hardware mapping, and a custom 6 g PCB.
Results
1 kHz onboard constrained MPC was demonstrated, with up to 15.6× faster solve time and 195.4× improved energy-delay product over embedded solvers.
Takeaways & Limitations
The system enables constrained trajectory tracking on a tiny quadrotor and scales to problems with over 20,000 optimization variables.
Abstract
from arXiv · showhide
Unlocking the potential of tiny aerial robots requires order of magnitude improvements in the performance of embedded edge control. In particular, although recent cached model predictive control (MPC) solvers can handle the fast system dynamics and complex constraints required for agile drone flight, their computational demands remain prohibitive for resource-constrained robots, forcing prior implementations to operate at reduced control rates. AccelMPC overcomes this challenge through an end-to-end co-design approach that jointly optimizes the solver algorithm, numerical representation, hardware mapping, and physical integration. AccelMPC pairs a co-designed FPGA-accelerated alternating direction method of multipliers (ADMM)-based MPC solver with a custom 6g PCB, providing high-bandwidth communication for deployment on a 35g Crazyflie. Hardware experiments demonstrate 1 kHz onboard constrained MPC with dynamic obstacles, up to 15.6x faster solve times and 195.4x improvement in energy-delay product over state-of-the-art embedded microcontroller-based solvers, all while scaling to optimization problems with over 20,000 optimization variables and a comparable number of constraints. We release our PCB design files, firmware, and FPGA solver code open source.
I. INTRODUCTION
Tiny aerial robots need near-kilohertz feedback, but resource constraints limit onboard computation and prevent cached MPC solvers from reliably converging under active constraints. AccelMPC addresses this gap through FPGA-accelerated ADMM MPC and end-to-end hardware-algorithm co-design.
- Tiny aerial robots face severe size, weight, and power constraints despite fast, unstable dynamics that demand feedback rates approaching kilohertz frequencies.
- Cached MPC solvers can run onboard tiny drones, but limited ADMM iterations under active constraints force reduced control rates.
- AccelMPC jointly optimizes solver structure, numerical representation, hardware mapping, and physical integration using an FPGA-accelerated ADMM solver and custom 6 g PCB.
- 1 kHz fully onboard constrained MPC with runtime-updated bounds was demonstrated for dynamic obstacle avoidance on a 35 g Crazyflie.
- 15.6× faster solve time and 195.4× improvement in energy-delay product were achieved over state-of-the-art embedded solvers while supporting more than 20,000 optimization variables.
- The project releases PCB design files, firmware, and FPGA solver code open source.
B. ADMM for Solving the Linear MPC QP
The paper applies ADMM to a constrained linear MPC quadratic program by splitting the optimization with an auxiliary variable and alternating structured updates.
- Introducing an auxiliary variable converts the constrained quadratic program into an equivalent problem with a box-indicator constraint.
- The augmented Lagrangian adds a quadratic penalty and dual-variable term for enforcing the equality Mw − y = 0.
- ADMM solves the formulation through three alternating updates involving the primal variable, projected auxiliary variable, and dual variable.
- The w-update is a structured linear-system solve, while the y-update projects onto the box [l, u].
- Using the scaled dual variable s = λ/ρ maintains b = ρMᵀ(y − s), making the linear-system right-hand side b − c.
A. Embedded and Edge MPC Solvers
Embedded and edge MPC solvers trade generality, structure exploitation, and computational efficiency, but tiny quadrotor MCUs remain unable to sustain reliable constrained optimization at high rates.
- Embedded MPC approaches include tailored code-generation tools, general-purpose operator-splitting solvers, and structured frameworks that exploit problem structure.
- Tiny quadrotors cannot support power-hungry CPUs or GPUs and instead rely on resource-constrained microcontrollers.
- Cached MPC uses ADMM and offline Riccati factorizations to enable efficient QP solves within tiny platforms’ memory and timing constraints.
- As constraints activate and convergence slows, cached MCU-based approaches cannot scale and therefore require reduced control rates.
B. FPGA-Based Linear MPC
This section develops an FPGA-oriented MPC solver by exploiting structured linear algebra, fixed-point arithmetic, and deterministic streaming execution. The design targets online constrained control on tiny aerial robots while preserving scalability and numerical fidelity.
- No prior work combines FPGA-accelerated online MPC, onboard deployment, and closed-loop flight validation on a tiny aerial robot.
- AccelMPC jointly designs the optimization algorithm, numerical representation, hardware mapping, and physical integration, producing two FPGA solver mappings and a custom PCB.The project also releases the solver, firmware, and PCB design openly.
- Structured linear solve: The banded coefficient matrix enables streamed forward and backward substitution with cost O(Nvar) in the number of optimization variables.The bandwidth is determined by local stage coupling and is nearly independent of prediction horizon.
- Numerical representation: 32-bit fixed-point arithmetic reduces FPGA power and latency relative to floating point while introducing approximately 10^-6 m or less position-RMSE difference.Maximum constraint-violation and control-RMSE differences were approximately 10^-7.
- Deterministic execution: Fixed ADMM iteration counts provide deterministic latency, while runtime state, reference, and bound inputs preserve online MPC operation.
B. FPGA Datapath and Complementary Mappings
The FPGA datapath maps each ADMM operation to streaming hardware and offers complementary sparse and staged operator representations. These mappings share the solver and numerical format but trade energy, latency, and scalability differently.
- Streaming datapath: Every ADMM step maps to streaming hardware using local storage, pipelined substitution, and independent compare-saturate projection.
- Online solve: The solver caches compiled matrices, a banded Cholesky factor, penalty data, reference terms, and nominal bounds, then accepts runtime state and bound updates.
- Trade-offs: No single mapping is optimal across all robotic MPC problem sizes or applications because the alternatives trade energy and latency differently.
- Full sparse mapping: The full sparse mapping stores expanded operators directly, minimizing energy per solve but increasing BRAM demand and eventually spilling into distributed LUT memory.
- Staged mapping: The staged mapping reconstructs operator products during execution, yielding slightly lower short-horizon latency and substantially slower memory growth with problem size.Its improved scalability allows larger horizons on the same FPGA.
C. Custom PCB Design and Integration
AccelMPC uses a custom FPGA expansion board to overcome the resource and communication limitations of existing Crazyflie integration options. Firmware and high-speed links connect the solver to onboard state estimation and actuation.
- Board motivation: Existing Crazyflie FPGA solutions lacked sufficient resources or relied on low-bandwidth interfaces, motivating a custom four-layer expansion PCB.
- Hardware design: The board integrates an AMD Artix-7 100T FPGA, dedicated power management, high-speed SPI, a 100 MHz oscillator, and configuration flash.
- Firmware integration: Modified Crazyflie firmware transmits runtime solver data, triggers optimization, retrieves the first control input, and updates constraint bounds through the same interface.Changing bounds between control cycles supports dynamic obstacle avoidance.
V. EXPERIMENTAL EVALUATION
Experiments compare TinyMPC on the Crazyflie MCU with two FPGA mappings across prediction horizons and evaluate speed, energy, EDP, and feasible iteration budgets. The FPGA implementations sustain the requirements for kilohertz-rate constrained MPC.
- Solve time: FPGA implementations are up to 15.6× faster than TinyMPC across the evaluated prediction horizons.All three implementations scale approximately linearly with horizon.
- Physical integration: The fabricated 4×3 cm FPGA board mounts directly on the Crazyflie through its standard expansion interface.
- Energy-delay product: FPGA implementations achieve 79.1-195.4× lower energy-delay product than TinyMPC.Full sparse uses less power but scales less well than staged.
- Iteration budget: Within a 1 kHz control period, TinyMPC cannot sustain a sufficient constrained-MPC iteration budget, whereas both FPGA implementations preserve multiple iterations across the evaluated horizons.The budget includes MCU-FPGA communication overhead.
C. FPGA Architecture Tradeoffs and Scalability
The staged and full sparse FPGA mappings offer different energy, latency, and memory-scaling tradeoffs rather than a universally dominant design. Staged scales to much larger horizons, while full sparse is more energy efficient where its expanded operators fit on-chip.
- Neither FPGA mapping dominates across all design objectives; both provide high-performance, low-power control.
- Staged provides slightly lower latency over the shared operating range, while full sparse achieves lower power and energy per solve when its expanded operators fit efficiently in on-chip memory.
- Staged’s compact memory footprint avoids the LUTRAM spillover that limits full sparse near H = 90 and scales to H = 1350.
- 195.4× lower energy-delay product is achieved by FPGA implementations than TinyMPC at 10 ADMM iterations across evaluated horizons.
D. Onboard Flight Experiments
Onboard flight experiments show that the FPGA controller preserves nominal tracking while enabling larger online optimization budgets and enforcing constraints during 1 kHz flight.
- 1) Unconstrained Figure-Eight Tracking:: Comparable closed-loop tracking performance is achieved by TinyMPC and the FPGA controller on an unconstrained figure-eight trajectory.TinyMPC uses H=15 and k=2 at 500 Hz, whereas the FPGA controller uses H=20 and k=28 at the same control rate.
- 1) Unconstrained Figure-Eight Tracking:: A substantially larger online optimization budget is provided by the FPGA implementation while preserving the embedded baseline’s nominal tracking behavior.
- 2) Static constrained trajectory tracking:: At 1 kHz, the FPGA controller enforces box constraints onboard with H=27 and k=9, keeping the measured trajectory inside the admissible region.The reference intentionally violates the x- and y-coordinate bounds.
3) Dynamic obstacle avoidance:
The controller adapts online to moving obstacles by updating runtime constraint bounds while keeping the constraint matrix and FPGA configuration fixed. Flight demonstrations show obstacle avoidance alongside 1 kHz constrained control and scaling beyond 20,000 optimization variables.
- 3) Dynamic obstacle avoidance:: Dynamic obstacle motion changes only the corresponding entries of l and u, leaving the constraint matrix, Cholesky factorization, and FPGA bitstream fixed.
- 3) Dynamic obstacle avoidance:: The quadrotor deviates from its nominal figure-eight path to avoid moving boxes and returns to the nominal trajectory once the path clears.
- 1 kHz constrained trajectory tracking is enabled on a tiny quadrotor, while the same solver architecture scales to over 20,000 optimization variables.
- Future work targets richer collision-avoidance formulations and more aggressive flight regimes, including cluttered three-dimensional environments and online replanning around moving obstacles.