AccelMPC: High-Rate, Low-Power FPGA-Accelerated Model Predictive Control for Tiny Drones

• Tiny aerial robots face severe size, weight, and power constraints despite fast, unstable dynamics that demand feedback rates approaching kilohertz frequencies.Source: §I · p. 1
• Cached MPC solvers can run onboard tiny drones, but limited ADMM iterations under active constraints force reduced control rates.Source: §I · p. 1
• AccelMPC jointly optimizes solver structure, numerical representation, hardware mapping, and physical integration using an FPGA-accelerated ADMM solver and custom 6 g PCB.Source: §I · p. 1
• 1 kHz fully onboard constrained MPC with runtime-updated bounds was demonstrated for dynamic obstacle avoidance on a 35 g Crazyflie.Source: §I · p. 1
• 15.6× faster solve time and 195.4× improvement in energy-delay product were achieved over state-of-the-art embedded solvers while supporting more than 20,000 optimization variables.Source: §I · p. 1
• The project releases PCB design files, firmware, and FPGA solver code open source.Source: §I · p. 1

• Introducing an auxiliary variable converts the constrained quadratic program into an equivalent problem with a box-indicator constraint.Source: B. ADMM for Solving the Linear MPC QP · p. 2
• The augmented Lagrangian adds a quadratic penalty and dual-variable term for enforcing the equality Mw − y = 0.Source: B. ADMM for Solving the Linear MPC QP · p. 2
• ADMM solves the formulation through three alternating updates involving the primal variable, projected auxiliary variable, and dual variable.Source: B. ADMM for Solving the Linear MPC QP · p. 2
• The w-update is a structured linear-system solve, while the y-update projects onto the box [l, u].Source: B. ADMM for Solving the Linear MPC QP · p. 2
• Using the scaled dual variable s = λ/ρ maintains b = ρMᵀ(y − s), making the linear-system right-hand side b − c.Source: B. ADMM for Solving the Linear MPC QP · p. 2

• Embedded MPC approaches include tailored code-generation tools, general-purpose operator-splitting solvers, and structured frameworks that exploit problem structure.Source: A. Embedded and Edge MPC Solvers · p. 2
• Tiny quadrotors cannot support power-hungry CPUs or GPUs and instead rely on resource-constrained microcontrollers.Source: A. Embedded and Edge MPC Solvers · p. 2
• Cached MPC uses ADMM and offline Riccati factorizations to enable efficient QP solves within tiny platforms’ memory and timing constraints.Source: A. Embedded and Edge MPC Solvers · p. 2
• As constraints activate and convergence slows, cached MCU-based approaches cannot scale and therefore require reduced control rates.Source: A. Embedded and Edge MPC Solvers · p. 3

• No prior work combines FPGA-accelerated online MPC, onboard deployment, and closed-loop flight validation on a tiny aerial robot.Source: §IV · p. 3
• AccelMPC jointly designs the optimization algorithm, numerical representation, hardware mapping, and physical integration, producing two FPGA solver mappings and a custom PCB.The project also releases the solver, firmware, and PCB design openly.Source: §IV · p. 3

Structured linear solve

• The banded coefficient matrix enables streamed forward and backward substitution with cost O(Nvar) in the number of optimization variables.The bandwidth is determined by local stage coupling and is nearly independent of prediction horizon.Source: Figure 2 · p. 3, A. Algorithm and Numerical Co-Design · p. 4

Numerical representation

• 32-bit fixed-point arithmetic reduces FPGA power and latency relative to floating point while introducing approximately 10^-6 m or less position-RMSE difference.Maximum constraint-violation and control-RMSE differences were approximately 10^-7.Source: A. Algorithm and Numerical Co-Design · p. 4

Deterministic execution

• Fixed ADMM iteration counts provide deterministic latency, while runtime state, reference, and bound inputs preserve online MPC operation.Source: A. Algorithm and Numerical Co-Design · pp. 3–4

Streaming datapath

• Every ADMM step maps to streaming hardware using local storage, pipelined substitution, and independent compare-saturate projection.Source: B. FPGA Datapath and Complementary… · p. 4

Online solve

• The solver caches compiled matrices, a banded Cholesky factor, penalty data, reference terms, and nominal bounds, then accepts runtime state and bound updates.Source: B. FPGA Datapath and Complementary… · p. 4

Trade-offs

• No single mapping is optimal across all robotic MPC problem sizes or applications because the alternatives trade energy and latency differently.Source: B. FPGA Datapath and Complementary… · p. 4

Full sparse mapping

• The full sparse mapping stores expanded operators directly, minimizing energy per solve but increasing BRAM demand and eventually spilling into distributed LUT memory.Source: B. FPGA Datapath and Complementary… · p. 4

Staged mapping

• The staged mapping reconstructs operator products during execution, yielding slightly lower short-horizon latency and substantially slower memory growth with problem size.Its improved scalability allows larger horizons on the same FPGA.Source: B. FPGA Datapath and Complementary… · p. 4

Board motivation

• Existing Crazyflie FPGA solutions lacked sufficient resources or relied on low-bandwidth interfaces, motivating a custom four-layer expansion PCB.Source: C. Custom PCB Design and Integration · p. 4

Hardware design

• The board integrates an AMD Artix-7 100T FPGA, dedicated power management, high-speed SPI, a 100 MHz oscillator, and configuration flash.Source: C. Custom PCB Design and Integration · p. 5

Firmware integration

• Modified Crazyflie firmware transmits runtime solver data, triggers optimization, retrieves the first control input, and updates constraint bounds through the same interface.Changing bounds between control cycles supports dynamic obstacle avoidance.Source: C. Custom PCB Design and Integration · p. 5

Solve time

• FPGA implementations are up to 15.6× faster than TinyMPC across the evaluated prediction horizons.All three implementations scale approximately linearly with horizon.Source: B. Solver Benchmarks · p. 5

Physical integration

• The fabricated 4×3 cm FPGA board mounts directly on the Crazyflie through its standard expansion interface.Source: Figure 3 · p. 5

Energy-delay product

• FPGA implementations achieve 79.1-195.4× lower energy-delay product than TinyMPC.Full sparse uses less power but scales less well than staged.Source: B. Solver Benchmarks · p. 5

Iteration budget

• Within a 1 kHz control period, TinyMPC cannot sustain a sufficient constrained-MPC iteration budget, whereas both FPGA implementations preserve multiple iterations across the evaluated horizons.The budget includes MCU-FPGA communication overhead.Source: B. Solver Benchmarks · p. 5

• Neither FPGA mapping dominates across all design objectives; both provide high-performance, low-power control.Source: C. FPGA Architecture Tradeoffs and… · p. 5
• Staged provides slightly lower latency over the shared operating range, while full sparse achieves lower power and energy per solve when its expanded operators fit efficiently in on-chip memory.Source: C. FPGA Architecture Tradeoffs and… · p. 5
• Staged’s compact memory footprint avoids the LUTRAM spillover that limits full sparse near H = 90 and scales to H = 1350.Source: C. FPGA Architecture Tradeoffs and… · pp. 5–6
• 195.4× lower energy-delay product is achieved by FPGA implementations than TinyMPC at 10 ADMM iterations across evaluated horizons.Source: Figure 5 · p. 6

1) Unconstrained Figure-Eight Tracking:

• Comparable closed-loop tracking performance is achieved by TinyMPC and the FPGA controller on an unconstrained figure-eight trajectory.TinyMPC uses H=15 and k=2 at 500 Hz, whereas the FPGA controller uses H=20 and k=28 at the same control rate.Source: 1) Unconstrained Figure-Eight Tracking · p. 6, Figure 7 · p. 7
• A substantially larger online optimization budget is provided by the FPGA implementation while preserving the embedded baseline’s nominal tracking behavior.Source: 1) Unconstrained Figure-Eight Tracking · p. 6

2) Static constrained trajectory tracking:

• At 1 kHz, the FPGA controller enforces box constraints onboard with H=27 and k=9, keeping the measured trajectory inside the admissible region.The reference intentionally violates the x- and y-coordinate bounds.Source: 2) Static constrained trajectory… · pp. 6–7

3) Dynamic obstacle avoidance:

• Dynamic obstacle motion changes only the corresponding entries of l and u, leaving the constraint matrix, Cholesky factorization, and FPGA bitstream fixed.Source: 3) Dynamic obstacle avoidance · p. 7
• The quadrotor deviates from its nominal figure-eight path to avoid moving boxes and returns to the nominal trajectory once the path clears.Source: 3) Dynamic obstacle avoidance · p. 7

• 1 kHz constrained trajectory tracking is enabled on a tiny quadrotor, while the same solver architecture scales to over 20,000 optimization variables.Source: §VI · p. 7, Figure 8 · p. 7
• Future work targets richer collision-avoidance formulations and more aggressive flight regimes, including cluttered three-dimensional environments and online replanning around moving obstacles.Source: §VI · p. 7