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Fidelity-Aware Scheduling of Quantum Circuits on Multi-QPU Systems

Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto, Patrick Hopf, Deborah Volpe, Helmut Seidl, Giovanna Turvani, Robert Wille, Christian B. Mendl, Martin Schulz

arXiv:2609.09980v1quant-phcs.AIcs.ET

TL;DR

Heterogeneous multi-QPU systems make circuit placement difficult because device-specific compilation changes expected fidelity, while fidelity-first placement can reduce parallel utilization. The paper uses a GNN to predict per-QPU fidelity before compilation and a tunable scheduler to balance fidelity against parallelism. The framework closely approaches exhaustive fidelity-based assignment while avoiding compilation on every device.

  • Problem

    Heterogeneous QPUs can yield different compiled circuits and fidelities for the same circuit, making placement a trade-off between execution quality and parallelism.

  • Method

    A GNN predicts each circuit’s expected fidelity on each QPU before compilation, and a tunable scheduler uses those estimates to assign circuits.

  • Results

    The GNN reaches mean fidelity 0.3737 at w = 1 versus the Oracle’s 0.3759, while tracking the ground-truth policy within 0.0034 at every weight.

  • Takeaways & Limitations

    The scheduler captures most of the available fidelity gain at moderate weights while retaining multi-QPU use, exposing a practical fidelity–load-balance trade-off.

Abstract

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High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.

I. INTRODUCTION

Heterogeneous multi-QPU systems create circuit-dependent device-selection challenges because compilation and hardware characteristics determine execution fidelity. The paper proposes predicting fidelity before compilation and using those predictions to schedule circuits while balancing fidelity, parallelism, and compilation overhead.

  • Different QPUs can produce different compiled implementations and expected fidelities for the same high-level circuit.
  • The framework uses a GNN to predict each circuit’s expected post-compilation fidelity on every available QPU before device-specific compilation.
  • A tunable scheduler uses fidelity predictions to control the trade-off between execution quality and parallel device utilization.
  • Compiling each circuit only for its selected QPU reduces the overhead of exhaustive multi-device compilation.
  • The fidelity estimate accumulates calibrated operation success probabilities but omits idle-time decoherence, crosstalk, calibration drift, and shot noise.

B. Cost of Exhaustive Device Selection

Fidelity-first assignment can overload one QPU, whereas round-robin improves utilization while ignoring device-dependent fidelity. The proposed weight w exposes a continuous trade-off between these competing objectives.

  • Strict fidelity-first assignment can concentrate a batch on one QPU and leave other devices underutilized.
  • Round-robin improves distribution across QPUs but may assign circuits to devices with substantially lower expected fidelity.
  • Fidelity and parallelism are competing objectives, so improving one may reduce the other.
  • The fidelity weight w ∈[0, 1] ranges from workload distribution at w = 0 to highest-predicted-fidelity assignment at w = 1.
  • Intermediate weights allow limited fidelity loss in exchange for better workload distribution across devices.

III. RELATED WORKS

Prior work addresses device selection, fidelity prediction, resource management, and parallel execution separately. This paper combines pre-compilation fidelity prediction with tunable scheduling of circuit batches across heterogeneous QPUs.

  • Existing work does not provide a complete workflow for pre-compilation fidelity-based batch assignment that avoids multi-device compilation overhead.
  • Automatic device-selection studies avoid brute-force compilation but mainly classify the best target for an individual circuit.
  • Earlier GNN-based fidelity prediction estimates ESP across QPUs but does not address dispatching circuits among devices.
  • Other machine-learning approaches estimate circuit reliability from graph or sequence representations, while this work uses prediction to drive resource scheduling.
  • The paper contributes an end-to-end pre-compilation estimation and allocation framework, a tunable policy spanning round-robin and fidelity maximization, and evaluation on an IQM-derived emulated multi-QPU environment.

IV. METHODOLOGY

The methodology converts quantum circuits into numerical DAGs, predicts device-specific fidelity with a GNN, and assigns circuits using the resulting predictions. Its graph model uses directional message passing options and pooled graph representations.

  • The pipeline preprocesses circuits, estimates their fidelity on available QPUs with a GNN, and schedules them according to a selected policy.
  • Circuit preprocessing represents gates as DAG nodes and operation dependencies as directed edges.
  • The GNN graph encoder aggregates neighboring-node information, and an MLP predicts fidelity for the target devices.
  • Bidirectional message passing optionally processes both the original and reversed DAG to capture upstream operations and downstream consequences.
  • Mean-max-sum pooling concatenates average, maximum, and sum aggregations of node embeddings into one graph-level representation.
  • The optimal model is selected by tuning the hyperparameters listed in the search space.

C. Scheduling

The scheduler assigns circuits sequentially to QPUs using GNN-predicted fidelities and a load-balancing penalty. Its fidelity weight w controls the trade-off between execution fidelity and workload distribution, reaching pure fidelity maximization at w = 1.

  • Scheduling: The scheduler sequentially assigns circuits from a unified queue to available QPUs using per-device fidelity estimates and current workload information.Each device is evaluated during the dispatch round, with load tracked as assigned circuits relative to total dispatched circuits.
  • Scheduling: The composite assignment score balances predicted fidelity against device load through a tunable fidelity weight w ∈ [0, 1].Raw fidelities and load shares use a common scale, preserving the magnitude of each circuit’s device preference.
  • Scheduling: The end-to-end framework converts circuits into DAGs, predicts a k × D fidelity matrix, schedules circuits to QPUs, and then transpiles them for their selected devices.DAG nodes represent gates and measurements, while edges encode data dependencies.
  • Scheduling: Increasing load makes further assignments progressively more expensive until the marginal load-share gap offsets the fidelity advantage.This mechanism uses actual share imbalance rather than normalized device ranks.
  • Scheduling: The ratio w/(1 − w) acts as an exchange rate between fidelity advantage and load share, so circuits switch devices at different weights according to their preferences.The allocation changes gradually across w ∈ (0, 1), while stronger device preferences trigger reassignment at lower weights.
  • Scheduling: At w = 1, the load term disappears and each circuit is assigned by pure fidelity maximization.This endpoint follows directly from omitting the load component of the score.

2) Dispatcher integration:

The Quantum Meta-Scheduler integrates fidelity-aware assignment into a continuous dispatch loop. It snapshots pending circuits and backend state, creates a device-to-circuit mapping, and executes each selected circuit through device-specific transpilation, submission, and result polling.

  • Dispatcher integration: The Quantum Meta-Scheduler runs a continuous dispatch loop over a unified queue shared by all available backends.The loop orchestrates the circuit lifecycle within an HPC allocation.
  • Dispatcher integration: Each dispatch tick snapshots pending circuits in arrival order and runtime backend state, including active-circuit counts and calibration data.The snapshot is immutable before scheduling begins.
  • Dispatcher integration: The scheduling policy returns a device-to-circuit mapping in which each circuit appears in at most one device list.In the fidelity-aware policy, pending circuits are processed sequentially using GNN-provided per-device estimates.
  • Dispatcher integration: After assignment, each circuit is transpiled for its target device, submitted for execution, and asynchronously polled for results.Device-specific transpilation avoids compiling every circuit for all available QPUs.
  • Dispatcher integration: The architecture separates scheduling policy from execution infrastructure, allowing alternative policies to be compared under identical dispatch and execution conditions.Any policy conforming to the multi-device interface can replace the fidelity-aware policy.

V. EXPERIMENTAL SETTINGS

The evaluation uses an emulated three-QPU environment derived from two IQM superconducting devices, with circuit-level fidelity labels generated through device-specific compilation. The experiments assess both GNN prediction accuracy and scheduling performance.

  • Experimental design: The study evaluates model fidelity prediction and its integration into scheduling across available QPUs.The evaluation has two complementary dimensions: prediction accuracy and device assignment.
  • Target devices: The environment uses EQE1, a 53-qubit device, and QExa20, a 20-qubit device, characterized by per-gate and per-qubit fidelity values.These IQM superconducting devices are used to emulate realistic multi-QPU conditions.
  • Target devices: Partitioning EQE1 into independent 26- and 27-qubit sub-devices creates a three-QPU configuration for studying parallelization and differing noise characteristics.Seven cross-boundary edges are severed, and the sub-devices inherit the parent device’s calibration data.
  • Dataset and labeling: The dataset contains 17056 MQT Bench circuits augmented with alternative state-preparation routines, ansatz topologies, and oracle targets.Each circuit is compiled for every target device with Qiskit optimization level 2 to generate circuit-device fidelity labels.
  • Model training: Bayesian optimization over 50 trials selects model hyperparameters, with training capped at 1000 epochs and early stopping after 50 stagnant epochs.The optimization objective is the minimum validation MSE reached during a trial.

VI. RESULTS

The results section evaluates the framework through fidelity-prediction accuracy and circuit dispatch across multiple QPUs. The publicly available implementation supports these evaluations.

  • Evaluation scope: The framework is evaluated along model fidelity-prediction accuracy and scheduler dispatch capability.These dimensions assess both predictive effectiveness and practical circuit assignment.
  • Reproducibility: The implementation is publicly available at https://github.com/1nnocenzo/pred-distr-tool.git.The repository provides access to the code used for the framework.

A. Fidelity Estimation Model

The GNN predicts circuit fidelity across target devices with low test-set error and little systematic bias. Its accuracy remains strong across fidelity ranges and is particularly high for QExa20.

  • Overall accuracy: 1.04% MAE and 2.00% RMSE are achieved on the test split for fidelity prediction.The reported metrics summarize the optimal model’s overall test-set performance.
  • Error by fidelity: RMSE remains below 4% across target-fidelity groups, with maximum errors occurring for fidelities in the range [0.1, 0.4].The grouped analysis characterizes where prediction errors are largest.
  • Device-specific accuracy: QExa20 achieves a fidelity-prediction RMSE about 27.5% lower than the overall RMSE.The device-specific result indicates particularly strong prediction performance for QExa20.
  • Prediction behavior: Predictions cluster around the perfect-agreement diagonal across the full fidelity range for all three target devices.The predicted-versus-ground-truth comparison shows little systematic bias in device-specific estimates.

B. Scheduling

The scheduling evaluation compares oracle, ground-truth-weighted, GNN, and round-robin policies across a fidelity-weight sweep. Increasing fidelity emphasis gradually shifts assignments toward preferred devices, while moderate GNN weights preserve more balanced utilization than the oracle.

  • Policy comparison: Four policies are compared: Oracle, GT-Weighted, GNN, and Round-Robin, with GNN and GT-Weighted swept over w ∈ {0.0, 0.1, ..., 1.0}.The evaluation uses ground-truth fidelities for oracle-based references and predicted fidelities for the GNN policy.
  • Parallelism evaluation: 55.6% of circuits prefer EQE1 Bottom, 35.1% prefer QExa20, and 9.3% prefer EQE1 Top under the Oracle assignment.The resulting load-balance coefficient of variation is CV = 0.697, revealing strong dataset preference for EQE1 Bottom.
  • Parallelism evaluation: At w = 0, GNN and GT-Weighted produce an almost uniform distribution with CV = 0.0003 across the three backends.The GNN policy exactly matches the Round-Robin reference at this weight.
  • Parallelism evaluation: The GNN distribution reaches CV = 0.033 at w = 0.3, 0.069 at w = 0.5, and 0.149 at w = 0.7 as fidelity emphasis increases.The share-equilibrium mechanism makes migration toward preferred devices gradual rather than abrupt.
  • Parallelism evaluation: The Oracle assigns 2846 of 5117 circuits to one device and only 474 to EQE1 Top, whereas moderate-weight GNN scheduling distributes work more evenly while approaching oracle-level fidelity.This trade-off provides a practical operating point for throughput-sensitive HPCQC workloads.

2) Fidelity results:

Prediction-aware scheduling improves fidelity as the fidelity weight increases, closely tracking ground-truth assignment while trading load balance for execution quality. Most of the available fidelity gain arrives at moderate weights, whereas further gains require substantial imbalance.

  • Fidelity versus weight: Mean fidelity increases monotonically with w: GT-Weighted reaches 0.3759 and GNN 0.3737 at w = 1, with the GNN within 0.0034 throughout.Both policies start at the round-robin endpoint when w = 0; GT-Weighted matches the Oracle at w = 1.
  • Reference policies: Round-robin has CV = 0.0003 and mean fidelity 0.3436, whereas the Oracle reaches 0.3759, defining the available fidelity-load trade-off band.The Oracle and round-robin provide weight-independent lower and upper reference points for the policy curves.
  • Fidelity-load trade-off: At w = 0.5, fidelity reaches 0.3675 (+7.0% over round-robin) with CV = 0.069, while w = 0.7 reaches 0.3703 (+7.8%) with CV = 0.149.These settings capture most of the fidelity advantage while retaining balanced use of the devices.
  • Fidelity-load trade-off: The final 0.9% fidelity gain, reaching 0.3737 at w = 1.0, requires CV to increase to 0.884.Marginal fidelity returns diminish sharply beyond the moderate-weight regime.
  • Prediction fidelity: GNN assignments converge toward GT-Weighted assignments as w increases, with agreement rising from 68.8% at w = 0.3 to 80.1% at w = 1.Mean regret decreases from 0.0031 to 0.0021, has median exactly zero, and only 1.15% of circuits exceed regret 0.05.

3) Scheduling overhead:

Prediction-based device selection reduces per-circuit compilation cost for sufficiently complex circuits by replacing exhaustive multi-device compilation with encoding and inference. The advantage is workload-dependent, and its one-off training-label cost must be amortized over enough dispatched circuits.

  • Per-circuit overhead: The prediction-based path is faster in both median and mean over the full test split, with encoding and inference costing 11.57 ms in the median.These costs are comparable to the two compilations avoided at D = 3.
  • Crossover behavior: The paths cross at about 35 two-qubit gates; in the densest bin, exhaustive selection costs 110 ms versus 64 ms for prediction, a 1.72× saving.The same trend reaches 1.73× at 20 qubits and 1.65× in the deepest depth quartile.
  • Workload dependence: Below the crossover, exhaustive compilation is cheaper, and 47% of circuits are individually faster to compile exhaustively than to predict.The prediction-based advantage grows with circuit size and the number of devices because exhaustive cost is linear in D while prediction cost is not.
  • Amortization: The 904.5 s training-label cost is amortized after approximately 9.1 × 10^4 dispatched circuits at D = 3, after which the framework yields net savings.The break-even point falls as the number of devices grows.
  • Caveats: Speedup estimates use batch-size-one CPU inference and a pure-Python DAG traversal, so the measured overheads are implementation-specific and conservative.The authors identify these as implementation rather than algorithmic costs.
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