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PHAT: PHotonic Accelerator for TFHE

Guowei Yang, Farbin Fayza, Beren Aydoğan, Carlos A. Ríos Ocampo, Ayse K. Coskun, Ajay Joshi

arXiv:2609.11613v1cs.CRcs.ARcs.ET

TL;DR

TFHE enables computation on encrypted data but remains costly because bootstrapping relies heavily on FFT operations and electronic accelerators face throughput and memory bottlenecks. PHAT uses OPCM-based FFT units with twiddle-stationary dataflow and optimized scheduling to address these constraints, achieving 2.14×–5.10× speedup across four TFHE-based ML workloads versus the best-performing ASIC accelerator.

  • Problem

    TFHE supports arbitrary encrypted computation, but its high computational and communication overhead, particularly in FFT-heavy bootstrapping, limits practical deployment.

  • Method

    PHAT is an OPCM-based photonic TFHE accelerator combining OPCM FFT units, a twiddle-stationary dataflow, and scheduling that addresses precision and programming overhead.

  • Results

    2.14×–5.10× speedup is achieved across four TFHE-based ML workloads against the best-performing ASIC accelerator.

  • Takeaways & Limitations

    PHAT demonstrates the potential of OPCM-based photonic acceleration for compute- and memory-intensive TFHE applications.

Abstract

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Fully Homomorphic Encryption (FHE) enables secure computation on encrypted data, making it a promising solution for privacy-preserving applications in the cloud. Among various FHE schemes, FHE over the Torus (TFHE) stands out due to its support for arbitrary operations. However, its high computation and communication overhead, particularly in the Fast Fourier Transform (FFT) operations required during bootstrapping, limits its practicality for real-world applications. Conventional electronic accelerators struggle to achieve sufficient throughput due to the limitations of technology scaling and the memory-wall problem. To address these challenges, we propose PHAT, a PHotonic Accelerator for TFHE leveraging Optically-addressed Phase-Change Memory (OPCM). OPCM-based processing-in-memory systems offer high computation and communication throughput, making them well-suited for accelerating FFT operations in TFHE. However, directly mapping FFT to OPCM presents challenges such as high-precision analog computation and the high latency and energy cost of programming OPCM cells. To overcome these challenges, we introduce a novel electro-photonic accelerator architecture optimized for TFHE, featuring OPCM-based FFT units, a twiddle-stationary dataflow tailored for OPCM, and a scheduling mechanism to maximize the utilization of the FFT units. PHAT delivers $2.14\times$--$5.10\times$ speedup across four real-world TFHE workloads against the state-of-the-art ASIC accelerator. Our approach significantly enhances the performance of TFHE applications, paving the way for practical and efficient homomorphic encryption in cloud computing.

I. INTRODUCTION

Cloud computation exposes sensitive data during processing, motivating FHE; TFHE supports broad encrypted computation but remains costly, especially in FFT-heavy bootstrapping. PHAT addresses these bottlenecks with an OPCM-based photonic accelerator and reports substantial speedups over electronic accelerators.

  • I. INTRODUCTION: TFHE protects data during computation and supports linear, Boolean, and lookup-table operations, making it suitable for general-purpose and ML workloads.
  • I. INTRODUCTION: TFHE remains impractical because computation and data-movement overhead are high, with bootstrapping dominated by FFT and IFFT operations.FFT and IFFT consume about 90% of TFHE bootstrapping time in the authors’ experiments.
  • I. INTRODUCTION: OPCM offers high-throughput processing-in-memory, but TFHE acceleration requires addressing double-precision arithmetic and costly OPCM-cell programming.OPCM programming requires nanojoules of energy and hundreds of nanoseconds per cell.
  • I. INTRODUCTION: PHAT combines OPCM-based FFT units, a multi-word photonic multiplier, and a twiddle-stationary dataflow tailored to TFHE.The design assigns twiddle factors to fixed hardware units and schedules butterfly operations accordingly.

II. BACKGROUND

The background introduces OPCM’s non-volatile, multilevel optical storage and processing capabilities, then describes TFHE’s ciphertext structures and programmable bootstrapping operations. These properties and workloads motivate the accelerator design.

  • A. OPCM Background: OPCM stores multibit values non-volatilly and supports analog in-memory multiplication through GST-controlled optical transmittance.Demonstrated GST cells provide up to 64 deterministic states, or 6 bits per cell.
  • A. OPCM Background: OPCM programming changes GST phase using heat, with electrical switching requiring 5.55–860.71 nJ in prior studies.Optical switching can use less energy but faces scalability challenges from optical routing and device footprint.
  • A. OPCM Background: Phase-change memories provide non-volatile amplitude modulation, long-term retention, and substantial refractive-index modulation for processing-in-memory.
  • B. TFHE Background: TFHE uses LWE and GLWE ciphertexts together with bootstrapping and key-switching keys to support encrypted operations.LWE ciphertexts hold encrypted data, while GLWE ciphertexts store univariate functions used during programmable bootstrapping.

2) TFHE operations:

TFHE operations include programmable bootstrapping, key switching, and linear leveled ciphertext operations. PBS combines modulus switching, blind rotation, and sample extraction, with blind rotation dominating runtime.

  • Blind rotation consumes approximately 96% of total PBS runtime, making it the computationally intensive PBS step.
  • PBS performs modulus switching, blind rotation, and sample extraction to produce a new LWE ciphertext.Modulus switching changes the ciphertext modulus, while sample extraction selects a polynomial coefficient without computation.
  • The PBS procedure iteratively performs polynomial rotation, subtraction, decomposition, and external-product operations.
  • Key switching converts the post-PBS LWE ciphertext back to its original size under the original key.
  • Linear leveled operations include ciphertext-ciphertext addition, ciphertext-cleartext addition, and ciphertext-cleartext multiplication.

C. Fast Fourier Transform (FFT)

The FFT accelerates the discrete Fourier transform by decomposing it into radix-2 butterfly stages. Each butterfly combines two complex inputs with a twiddle factor to produce two complex outputs.

  • FFT reduces DFT complexity from O(N^2) to O(N log N) using the Cooley-Tukey radix-2 algorithm.The algorithm divides a size-N FFT into log N stages, each containing N/2 butterfly operations.
  • Each butterfly consumes complex inputs a and b plus twiddle factor ω, producing two complex outputs.

2) Accelerating polynomial multiplication using FFT:

FFT and IFFT reduce polynomial-multiplication complexity and are central to TFHE acceleration. PHAT maps these operations onto OPCM-based butterfly units with programmed twiddle factors.

  • FFT-based polynomial multiplication reduces complexity from O(N^2) to O(N log N).
  • Negacyclic FFT for degree-N polynomials can use a size-N FFT through input preprocessing with powers of ω_2N.
  • Conjugate symmetry reduces the required FFT size from N to N/2 for real polynomial signals.The method folds paired coefficients into complex numbers containing the real signal components.
  • PHAT uses OPCM chiplets containing photonic butterfly units, with twiddle factors programmed during initialization and retained without refresh.

B. Microarchitecture

PHAT’s microarchitecture assigns FFT butterfly multiplications to OPCM photonic multipliers while retaining additions and subtractions in electronic hardware. Its multi-word design addresses the precision gap between OPCM cells and TFHE bootstrapping requirements.

  • 1) BFU Microarchitecture: Each butterfly uses four unique constant multiplications in OPCM and performs the remaining additions and subtractions electronically.
  • PHAT evaluates numerical accuracy across digital and analog domains to ensure optical and conversion errors do not affect FHE correctness.
  • 2) OPCM PMult Microarchitecture: At least 42 bits of FFT precision are required for successful PBS, exceeding the 6-bit precision of a single OPCM cell.
  • 2) OPCM PMult Microarchitecture: PHAT’s multi-word multiplier combines low-precision OPCM operations to support the high-precision FFT multiplications required by PBS.
  • 2) OPCM PMult Microarchitecture: A modified 3×3 OPCM array stores two triangular matrices, computes partial products, and combines them digitally into high-precision multiplication results.The design uses extra optical-electrical converters and shift-and-add logic to assemble the partial products.
  • 2) OPCM PMult Microarchitecture: Signed PMult combines two unsigned PMult units because optical intensity and GST transmittance support only nonnegative values.

1) Twiddle-stationary Dataflow:

PHAT keeps twiddle factors programmed in OPCM BFUs across FFTs, then addresses access imbalance and utilization through replicated BFUs and eager scheduling.

  • Twiddle-stationary Dataflow: PHAT programs each BFU with a fixed twiddle factor because OPCM reprogramming costs 5.55–860.71 nJ and 400 ns per cell.The assignment remains fixed after TFHE parameters are chosen.
  • Twiddle-stationary Dataflow: Twiddle-stationary dataflow minimizes twiddle-factor reprogramming across multiple FFTs.The design keeps twiddle factors stationary to address OPCM programming cost.
  • Access-aware BFU Allocation: Twiddle-factor access imbalance can reduce BFU utilization to 0.8% in a size-1024 FFT.Repeated accesses serialize butterfly operations on the BFU holding the required factor.
  • Access-aware BFU Allocation: 13.38× FFT speedup is achieved with access-aware BFU allocation and 37.5% area overhead.The strategy assigns more BFUs to frequently accessed twiddle factors to mitigate access bottlenecks.
  • Eager Scheduling: Eager scheduling combines operations from multiple FFTs and improves FFT throughput by over 70× when paired with access-aware BFU allocation.Operations execute as soon as their required BFUs are available, while FFT units run alongside electrical-chiplet units.

3) Difference from Prior Batching Strategies:

PHAT’s batching strategy targets OPCM’s data-dependent BFU utilization by scheduling butterfly operations out of order rather than using fixed-step pipelining.

  • Difference from Prior Batching Strategies: Eager scheduling executes butterfly operations as soon as required BFUs are available, enabling out-of-order execution.The strategy differs from lock-step pipelining and is designed to improve resource efficiency on OPCM hardware.
  • Evaluation Methodology: PHAT’s evaluation combines accuracy experiments, component-level simulation, and PPA estimation across TFHE PBS workloads and prior solutions.The methodology uses TFHE-rs and Concrete-ML traces together with dedicated simulators.
  • PPA Evaluation: The OPCM design is conservatively modeled at 5 GHz despite current OPCM implementations reaching up to 18 GHz.This frequency assumption is based on a level considered achievable using CMOS technology.
  • PPA Evaluation: PHAT consumes 528 W on average across four real-world TFHE workloads.The power estimate is reported as part of the accelerator’s PPA analysis.

B. Evaluation Workload

PHAT is evaluated on representative TFHE PBS parameter sets and four inference workloads, with accuracy and access-aware BFU allocation assessed alongside performance and area.

  • B. Evaluation Workload: The workload evaluation uses four representative TFHE PBS parameter sets and four inference tasks: XGBoost, NN-20, NN-50, and NN-100.The neural-network tasks are convolutional networks with 20, 50, and 100 layers.
  • C. Accuracy of the OPCM FFT Unit: Increasing PMult word count or bit width reduces FFT error relative to a double-precision baseline.Accuracy is quantified using Mean Squared Error against a 53-bit-mantissa reference.
  • C. Accuracy of the OPCM FFT Unit: A 7-word PMult with 6 bits per word achieves full PBS success, providing 43 bits of precision including the sign bit.This is the smallest evaluated configuration reaching 100% success for the tested 128-bit-security parameter set.
  • D. Access-aware BFU Allocation: Access-aware BFU allocation assigns additional BFUs to twiddle factors whose access counts exceed a configurable threshold.Allocation is proportional to access frequency for selected factors, while other factors receive one BFU.
  • D. Access-aware BFU Allocation: For thresholds at least 15, access-aware allocation delivers 1.21–13.38× speedup with 0.2%–37.5% area overhead.The comparison is against a baseline without access-aware allocation for one size-1024 FFT.

E. Scheduling Optimization

PHAT combines scheduling and access-aware allocation to improve FFT-unit utilization and TFHE performance, while remaining a proof-of-concept with substantial area and power costs.

  • E. Scheduling Optimization: Eager scheduling addresses low BFU utilization by executing multiple FFTs in parallel, whose different stages are more likely to use different twiddle factors.This reduces BFU contention under the twiddle-stationary dataflow.
  • E. Scheduling Optimization: 13.38× speedup from access-aware BFU allocation shows that twiddle-factor access imbalance, rather than insufficient scheduling opportunities, is the primary scheduling bottleneck.Increasing the number of FFTs in the schedule queue improves throughput by at most 20%, whereas AA substantially alleviates the bottleneck.
  • 1.68×, 1.79×, 1.80×, and 1.41× higher PBS throughput than Morphling across parameter sets I–IV demonstrate PHAT’s overall performance advantage.The improvement is attributed to OPCM’s high computational throughput and in-memory processing, which reduce computation latency and data movement overhead.
  • 2.14×, 4.10×, 4.72×, and 5.10× speedups over Morphling across XGBoost, NN-20, NN-50, and NN-100 show stronger gains on complete workloads.Parallel GEMM and vector units overlap with BFU execution, helping hide BFU latency and reduce overall execution time.
  • PHAT consumes 8.1× more area and 10× higher power than Morphling, reflecting the maturity gap between integrated photonics and optimized electrical ASIC technology.The authors frame PHAT as a proof-of-concept whose area and power are not yet competitive with ASICs.

V. RELATED WORK

Prior TFHE accelerators span electronic platforms and photonic or processing-in-memory designs, but PHAT targets TFHE’s precision and throughput requirements with OPCM-based acceleration.

  • Electronic TFHE accelerators reduce baseline cost but remain constrained by high computational overhead, technology-scaling limits, and memory bottlenecks.The related work covers CPUs, GPUs, FPGAs, ASICs, and electronic processing-in-memory systems.
  • PHAT’s reported PBS and application evaluations are summarized in Table III and Table IV, respectively.
  • Photonic accelerators commonly use 8–12-bit arithmetic for ML, whereas TFHE requires at least 42 bits of precision.PHAT uses photonic multi-word multipliers to improve precision without RNS conversion.
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