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A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs
Elia Mateu-Barriendos, Álvaro Gómez-Pau, Josep Rius, Daniel Arumí, Rosa Rodríguez-Montañés, Salvador Manich
TL;DR
Current-mode readout circuits can add area and power overhead to memristive SNN crossbars. This paper converts the column-voltage VMM output into a time-domain signal for neuron current injection. A 10×1 prototype and a trained 64×10 SNN application demonstrate the approach, with reported area reduction and comparable energy efficiency versus a representative current-sensing implementation.
Problem
Current-mode readout and scaling circuitry can impose substantial area and power overhead in memristive SNN crossbars.
Source: §I · p. 1Method
The proposed fully analog readout converts the column-voltage VMM output into a variable-width pulse that controls neuron current injection.
Source: §I · p. 1, §II · pp. 1–2Results
The 10×1 prototype achieved ∼20× area reduction over a representative current-sensing implementation with comparable energy efficiency, and a trained 64×10 SNN demonstrated inference feasibility with quantized memristive weights.
Source: §IV · p. 4Takeaways & Limitations
Column-voltage sensing avoids current-mode circuitry that becomes challenging at high column currents.
Source: §IV · p. 4
Abstract
from arXiv · showhide
Artificial neural networks rely on vector-matrix multiplications (VMMs), whose implementation in von Neumann architectures is dominated by costly data movement between memory and processing units. Spiking neural networks (SNNs) mitigate this bottleneck by performing in-memory, analog VMMs using memristive crossbar arrays. However, conventional current-mode readout circuits incur significant area and power overhead. This work proposes a fully analog readout architecture based on voltage-to-time conversion of the VMM output. By sensing the column voltage, the proposed approach avoids current-mode summing and scaling circuitry, improving area and energy efficiency. Post-layout simulations of a 10x1 SNN implemented in a 130 nm CMOS technology validate the proposed architecture, while application to a trained 64x10 SNN for digit classification further demonstrates its feasibility for SNN inference.
I. INTRODUCTION
Memristive crossbars perform in-memory VMMs for SNNs, but readout and neuron design can limit area and energy efficiency. The paper proposes voltage-to-time readout to avoid current-mode sensing and explicit scaling circuitry.
I. INTRODUCTION
- Analog neurons integrate column current efficiently, but large read currents limit scalability and can require large capacitors, extra circuitry, or binary weights.The cited memristive devices typically operate in the tens to hundreds of kΩ, producing µA−mA column currents in large arrays [7].Source: §I · p. 1
- Conventional readout can dominate area and power: digital schemes use per-column amplifiers and ADCs, while current-mode circuits may require complex scaling.Large scaling factors over wide dynamic ranges can require multi-stage designs.Source: §I · p. 1
- Voltage sensing and time-based encoding had been used in other systems, but the cited approaches were not directly suited to analog SNNs.Crossbars store synaptic weights as non-volatile conductances and inherently perform VMMs through Ohm’s and Kirchhoff’s laws.Source: §I · p. 1
- The proposed readout converts the VMM output from a sensed column voltage into time, avoiding current-mode readout and explicit scaling circuitry.The authors state that this enables compact neuron design, multilevel weights, and improved area and energy efficiency.Source: §I · p. 1
II. VOLTAGE-TO-TIME READOUT ARCHITECTURE
The architecture senses the VMM output as a column voltage and converts it into a pulse duration that controls neuron current injection. This time encoding makes neuron current settable by design rather than scaled to the column output.
II. VOLTAGE-TO-TIME READOUT ARCHITECTURE
- The 1T1R synaptic weights are conductances, and the VMM output is the sum of active-input conductances sensed as column voltage VREAD,j.A reference current is injected into each column and selected to keep VREAD,j below the SET voltage; the access transistor’s ON-resistance is neglected.Source: §II · pp. 1–2
- The V2T circuit converts VREAD,j into an active-low CTRL pulse whose duration ∆tj is set by the capacitor discharge time.During SPK EN, CCAP discharges through NMOS M1; afterward, PMOS M0 restores VCAP.Source: §II · p. 2
- The discharge-time conversion is monotonic but nonlinear, following a power-law dependence on the column conductance.Circuit tuning can produce a locally approximately linear region.Source: §II · p. 2
- The CTRL pulse switches neuron current IPOS, making injected charge proportional to pulse duration; IPOS can therefore be set by neuron design constraints.Unlike current sensing, the VMM result is encoded in time rather than current amplitude that scales with the column output.Source: §II · p. 2
III. RESULTS AND DISCUSSION
The authors implemented a 10×1 SNN prototype in 130 nm CMOS and report its design parameters. The V2T circuit targets specified input-spike timing, and its timing robustness was evaluated under process and mismatch variations.
III. RESULTS AND DISCUSSION
- A 10×1 SNN prototype based on the proposed architecture was implemented in 130 nm CMOS and submitted for fabrication.Table I summarizes the prototype’s design parameters.Source: §III · p. 2, Table I · p. 2
- The V2T circuit targets 2.5 µs input spikes at rates up to 200 kHz, with a scaling and offset network designed to draw negligible current compared with active memristors.The network is intended not to disturb the read operation.Source: §III · p. 2
- At maximum conductance, combined process and mismatch variations produced a timing spread of σ/µ = 13.7% in PVT-corner and Monte Carlo robustness checks.The IF neuron operates on the input-spike timescale.Source: §III · p. 2
A. Post-layout simulation results
Post-layout simulations confirm monotonic conductance-to-time conversion across the operating range, with reduced sensitivity at high conductance. Representative waveforms show distinct firing rates for one and ten active inputs.
A. Post-layout simulation results
- Post-layout simulations use a Verilog-A memristive-device model from the PDK.The reported conversion results are based on a representative subset of active inputs and conductance combinations.Source: A. Post-layout simulation results · p. 2
- The conductance-to-time conversion is monotonic over the operating range, with an approximately linear region and reduced sensitivity at high conductance.At high column conductance, additional simultaneously active inputs reduce sensitivity rather than preventing operation.Source: A. Post-layout simulation results · p. 2, Figure 5 · p. 3
- 11.8 kHz and 66.8 kHz firing rates result for one and ten simultaneously active inputs, respectively.The representative waveforms use 200 kHz inputs and 0.2 mS synaptic weights.Source: A. Post-layout simulation results · pp. 2–3
B. Area and Energy
The prototype’s reported energy per synaptic operation is 129 pJ. Its area and idle power scale approximately linearly with output-neuron count, while decoupling capacitors account for much of the V2T circuit area.
B. Area and Energy
- Table II reports the implemented prototype’s layout area, excluding access circuitry.The table expresses area in equivalent minimum-size inverters, with 7.56 µm² per inverter.Source: B. Area and Energy · p. 3, Table II · p. 3
- 129 pJ is the total energy per synaptic operation, including synaptic readout and voltage-to-time conversion.The synaptic circuit uses 128.5 pJ per read; the V2T circuit uses 0.58 pJ per operation.Source: B. Area and Energy · p. 3
- Area and idle power scale approximately linearly with output-neuron count, with one reference-current generator and one V2T circuit required per output.About 70% of the V2T circuit area is occupied by decoupling capacitors, which can be shared in larger systems.Source: B. Area and Energy · p. 3
C. Comparison with a current-sensing scheme
The proposed V2T circuit is reported to occupy over 20× less per-column readout area than a representative current-sensing design. The energy comparison is similar in magnitude, but the cited current-sensing design covers a narrower conductance range.
C. Comparison with a current-sensing scheme
- Over 20× smaller per-column readout area is reported for the proposed V2T circuit than for the representative current-sensing implementation.The current-sensing design’s estimated 130 nm CMOS readout area is 11,000 µm² (≈1455 INV).Source: C. Comparison with a current-sensing… · p. 3
- 120 pJ per read operation is reported for over the 2.5 µs comparison window, an energy of the same order of magnitude as the proposed approach.The cited 10 µA–200 µA current range corresponds to 0.04 mS–0.8 mS, less than 10% of the 0.1 mS–10 mS range targeted here.Source: C. Comparison with a current-sensing… · p. 3
- 25 µA–2.5 mA column currents in the proposed 10×1 SNN would require 10³–10⁵ attenuation to reach the nA range, plus circuitry to enforce fixed read voltage.The added circuitry is estimated to increase the 120 pJ energy by several orders.Source: C. Comparison with a current-sensing… · p. 3
D. Application to Digit Recognition
The trained 64×10 SNN produced matching digit-classification outcomes in software and circuit implementations on representative rate-encoded samples. This provides preliminary validation of the architecture for inference with quantized memristive weights.
D. Application to Digit Recognition
- The evaluated network was a trained 64×10 SNN with nonnegative weights quantized to ten conductance levels spanning 1 kΩ to 10 kΩ.The weights were mapped to a schematic-level implementation.Source: D. Application to Digit Recognition · p. 3
- Representative 8×8 digit samples produced the same classification outcome in software and circuit implementations, providing preliminary validation for inference.The samples were rate-encoded over 100 µs.Source: D. Application to Digit Recognition · pp. 3–4, Figure 7 · p. 4
- Membrane traces in the application figure are shown only when multiple neurons are active.Source: Figure 7 · p. 4
IV. CONCLUSION
The proposed fully analog memristive-SNN readout converts column voltage into a time-domain signal that controls neuron current injection. The 10×1 prototype achieved about 20× lower area than a representative current-sensing implementation with comparable energy efficiency, and a trained 64×10 SNN demonstrated inference feasibility.
IV. CONCLUSION
- The readout converts the VMM output, sensed as column voltage, into a time-domain signal controlling neuron current injection.Avoiding current-mode readout eliminates complex, area-intensive circuitry that becomes challenging at high column currents.Source: §IV · p. 4
- The 10×1 prototype achieved ∼20× area reduction over a representative current-sensing implementation with comparable energy efficiency.It was implemented in 130 nm CMOS, with post-layout results confirming conductance-to-time conversion.Source: §IV · p. 4
- Application to a trained 64×10 SNN demonstrated feasibility for inference with quantized memristive weights.Source: §IV · p. 4