PaperlayerView exact revision on arXiv

Source-linked AI summary

Benchmarking the computational power of quantum computers

Timothy Proctor, Oliver Hart, Oliver Widzowski Maupin, Matthew Girling, Daniel Hothem, Daniel Mills, Jordan Hines, Karl Mayer, Jacob S. Nelson, Tyler LeBlond, Zohim Chandani, Diego Forlivesi, Piper C. Wysocki, Boldizsár Poór, Joan M. Dreiling, Annie Park, Adam P. Reed, Brian Estey, Cameron Foltz, Akhil Isanaka, M. S. Allman, Michael Mills, Maxwell D. Urmey, Peter E. Siegfried, Audrey Faricy, Jin-Sung Kim, Cristina Cîrstoiu, Andrew D. Baczewski, Charles H. Baldwin, Robin Blume-Kohout

arXiv:2609.12146v1quant-phcs.ETcs.PF

TL;DR

Scientific-utility progress is difficult to compare because existing benchmarks do not directly measure large-circuit performance against utility-scale resource estimates. QUOPS benchmarks processors using computationally relevant circuits and estimates the largest successful sizes and execution rates; current processors have or nearly have the required rates, but their scores remain roughly five orders of magnitude short.

  • Problem

    Existing benchmarks do not directly compare integrated large-circuit performance with evolving scientific-utility resource estimates across diverse hardware.

    Source: p. 1

  • Method

    QUOPS uses randomized circuits built from alternating RP(θ) and CNOT layers, with mirror circuits estimating the largest successful sizes in an admissible width–size range.

    Source: p. 3, METHODS · p. 7

  • Results

    Current physical processors have or nearly have the QUOPS rates estimated for RSA-2048 and FeMoco, but their scores remain roughly five orders of magnitude short; the simple fault-tolerant architecture is outperformed by physical-qubit processors.

    Source: pp. 5–6

  • Takeaways & Limitations

    The first fault-tolerant architecture to set a QUOPS record above every physical-qubit architecture would mark a major milestone and a realization of Gottesman’s criterion for demonstrating fault tolerance.

    Source: p. 6

    The demonstrated Steane-code experiment does not saturate Helios-1’s fault-tolerant capability.

    Source: p. 5

Abstract

from arXiv · show

Quantum computing hardware is advancing rapidly toward utility-scale machines that will enable scientific breakthroughs. Many teams are pursuing distinct and difficult-to-compare routes to this goal, using different qubit technologies and logical architectures. Tracking progress toward quantum utility therefore requires rigorous benchmarks that measure computational capability relative to utility-scale challenge problems and enable fair comparison across disparate platforms. Here we demonstrate direct, cross-platform measurement of quantum computational capability using a new benchmark that quantifies the size of the largest computationally relevant quantum circuits that a machine can execute successfully and the speed at which it can execute them. We apply this quantum universal operation performance system (QUOPS) experimentally to leading processors from Quantinuum, Google, and IBM, computing directly on physical qubits. Translating state-of-the-art resource requirements for recognized challenge problems that represent useful quantum computation into effective QUOPS circuit sizes shows that computational capability must grow by 5 orders of magnitude, motivating fault-tolerant approaches. We use the same benchmark to assess the performance of a simple fault-tolerant logical-qubit processor implemented on up to eight [[7,1,3]]-encoded logical qubits using Quantinuum Helios-1, and project the growth of capability across successive generations of fault-tolerant quantum computers to show how QUOPS can track progress toward quantum scientific utility.

METHODS

QUOPS tests circuits by width and size, then uses mirror-circuit measurements to estimate which shapes a processor executes successfully. Its capability region and score summarize successful shapes, while QUOPS rates and error-mitigated estimates add throughput and mitigation views.

METHODS

  • Circuit width counts qubits, while size counts single-qubit RP(θ) gates plus twice the number of CNOT gates.The tested shapes (w, s) can be chosen to map the edge of a system’s capability region and locate its highest QUOPS score.Source: METHODS · p. 7
  • For each selected shape, random QUOPS circuits are compiled into architecture-specific gates, potentially using routing, synthesis, serialization, or ancillas.Compilation may approximate the target unitary.Source: METHODS · p. 7
  • A shape passes when its mean process polarization meets the threshold, assessed with mirror circuits and a one-sided confidence bound.Noise and imperfect approximate compilation both reduce polarization; the standard threshold is 1/√e, except for error-mitigated capability estimates.Source: METHODS · p. 7
  • The QUOPS score is the largest successful circuit size in the admissible cone, with score and capability-region estimates subject to stated confidence criteria.The score uses at least 95% confidence unless stated otherwise; the capability region uses at least 90% confidence and assumes success does not increase with width or size.Source: METHODS · p. 7
  • Error-mitigated capability estimates may be extrapolated from mean-polarization data, but can include circuit sizes not executed and might not be achievable in practice.Reported error-mitigated scores should include the polarization threshold, corresponding sampling overhead, and QUOPS rate at the score’s circuit shape.Source: METHODS · p. 7
  • QUOPS rate adjusts raw circuit size per execution time for estimated error-mitigation overhead, with the operational rate accounting for mirror-circuit and execution overheads.Rates should be reported alongside the score at the same circuit shape, although the shape maximizing rate may differ from the one maximizing score.Source: METHODS · pp. 7–8

SUPPLEMENTARY INFORMATION

This supplementary section formalizes QUOPS circuits, their compilation, and the measures used to define circuit success, capability regions, and benchmark scores across architectures. It specifies how the scalar score Q and rate Ω characterize successful circuit sizes and the time needed to obtain useful data.

A. Quantum circuits

  • Circuit definitions distinguish width, layer-count depth, and gate-weighted size; the supplementary notation also treats random circuits and their expectation values as random variables.The primary size assigns a k-qubit gate weight k, while a gate-specific count can be defined separately.Source: A. Quantum circuits · p. 12, C. Random circuits · p. 12

B. Process fidelity and polarization

  • Process polarization rescales process fidelity and is useful for deep circuits because it approaches zero as fidelity approaches 1/4^n; for depolarizing noise, polarization equals the depolarizing parameter.Process fidelity is closely related to average gate fidelity, with a difference of O(1/4^n).Source: B. Process fidelity and polarization · p. 12

A. QUOPS gate set

  • QUOPS circuits use an architecture-independent gate set of all-to-all CNOTs and Pauli-axis rotations, with intentional compilation overhead that approximates costs of compiling algorithm-like operations.Restricted connectivity can require SWAP chains or CNOT ladders; reporting compiled circuit properties is encouraged for architecture-specific comparisons.Source: A. QUOPS gate set · pp. 12–13

B. QUOPS circuits

  • A QUOPS circuit has width w, even depth d, and random paired layers of CNOTs and single-qubit rotations; its final layer may be partially filled, and size counts single-qubit gates plus twice the CNOT count.For fixed width, circuit size has discrete allowed values determined by depth and final-layer filling fraction.Source: B. QUOPS circuits · p. 13

C. QUOPS circuit compilation

  • QUOPS permits approximate compilation, compilation across circuit layers, and ancillas; approximation error reduces the score, while proxy circuits must use exact compilation and generally preserve layer barriers.The foundational definition uses idealized noise assumptions, but the operational procedure is designed to estimate it when those assumptions approximately hold and remains well-motivated otherwise.Source: C. QUOPS circuit compilation · p. 14, §III · p. 14, A. QUOPS circuit success · p. 15

A. QUOPS circuit success

  • Circuit success is quantified by process polarization between the noisy compiled execution and the ideal circuit, including compilation error but excluding initial-state preparation and final readout errors.The foundational noise model excludes leakage and many non-Markovian processes, while the operational definition remains well-motivated when that model does not apply.Source: A. QUOPS circuit success · p. 15

B. QUOPS circuit ensemble success

  • For each circuit shape, QUOPS summarizes the variable process-polarization distribution by its mean, which is simpler to estimate and is expected to be close to the median for realistic distributions.Circuits of the same shape can have different polarization because compilation sizes and interactions with system noise vary.Source: B. QUOPS circuit ensemble success · p. 15

C. QUOPS capability regions

  • The standard capability region separates successful from failed circuit shapes using a threshold on mean process polarization; 1/√e is chosen for its error-rate interpretation and efficient sampling.Under a simple per-location error model, the threshold corresponds to circuit size s ≈ 1/(2ϵ); mirror-circuit success probabilities near the boundary are approximately 1/e.Source: C. QUOPS capability regions · p. 15
  • A QUOPS capability region marks circuit shapes whose mean polarization exceeds threshold α; α = 1/√e defines the standard region, while lower thresholds define error-mitigated regions.The region coarse-grains the shape-dependent probability distribution into success or failure; measurement requires estimating rather than exactly measuring polarization and sampling only some possible shapes.Source: C. QUOPS capability regions · p. 15

D. QUOPS score

  • Q is the largest successful circuit size inside an admissible cone intended to cover circuits expected to provide quantum utility, rather than only quantum-volume square circuits.The cone preserves the square-circuit boundary but excludes deep, narrow and wide, shallow shapes; at width 2, its depth bounds are s = 4 and s = 8, giving a maximum Q = 8.Source: D. QUOPS score · p. 16

E. QUOPS rate

  • QUOPS rate Ω complements Q by quantifying useful-operation rate while accounting for rejected executions and the additional samples required by error mitigation.Its simplified timing model omits practical costs such as circuit loading and recalibration, and proxy-circuit execution time may differ from compiled QUOPS-circuit time; an operational definition for mirror circuits is provided separately.Source: E. QUOPS rate · p. 16

F. Error-mitigated QUOPS regions and scores

The section distinguishes error mitigation from QUOPS’s success metric and describes how QUOPS metrics are estimated using mirror-circuit fidelity estimation (MCFE). MCFE uses reference and SPAM circuits to isolate compiled-circuit error, subject to reliability assumptions.

F. Error-mitigated QUOPS regions and scores

  • Error mitigation is not applied to QUOPS data because it acts on classical outcomes, while QUOPS success measures quantum evolution; its potential benefit is represented by separate error-mitigated regions and scores.Heralded-error techniques such as detection and postselection are permitted, with discarded executions counted in the QUOPS rate.Source: F. Error-mitigated QUOPS regions and… · p. 17
  • The sample overhead approximates the multiplicative increase in circuit executions needed to estimate an observable without noise for QUOPS circuits of the specified size.The bound may be inaccurate if mitigation is biased or if learning a noise model adds costs, which it does not include.Source: F. Error-mitigated QUOPS regions and… · p. 17

IV. AN OPERATIONAL DEFINITION OF QUOPS

  • QUOPS metrics are estimated by first estimating circuit polarization, then using mean polarization estimates to derive capability regions, scores, and rates with stated statistical confidence.The operational definition permits polarization-estimation procedures other than MCFE when their accuracy is justified under applicable system assumptions.Source: §IV · p. 17, A. Estimating QUOPS circuit success:… · p. 17

A. Estimating QUOPS circuit success: MCFE

  • MCFE estimates an individual QUOPS circuit’s process polarization; averaging estimates from sampled circuits gives the shape’s mean, while a later procedure is more sample-efficient.MCFE is reliable under the stated physically relevant circumstances; otherwise, or when using another procedure, its reliability should be justified.Source: A. Estimating QUOPS circuit success:… · p. 17

1. MCFE circuit ensembles

  • M1 contains the compilation being assessed, M2 contains reference compilations, and M3 is a SPAM reference; combining their data isolates the assessed compilation’s error.M3 estimates errors from SPAM and the L and L′ layers; M2 data remove the reference-compilation contribution. If g = gref, M1 and M2 are identically distributed, so M2 need not be run separately.Source: Figure 5 · p. 18, §1 · p. 19

2. MCFE single-circuit data analysis

This section presents MCFE and single-shape QUOPS procedures for estimating circuit polarization, score, capability region, and rate, including reference compilations for physical- and logical-qubit errors. It also describes fixed and adaptive score procedures and uncertainty controls for capability-region estimates and false passes.

2. MCFE single-circuit data analysis

  • MCFE estimates a circuit’s process polarization from the effective polarizations of sampled mirror circuits; its sample complexity does not grow with circuit size or width when mirror polarizations are O(1).QUOPS checks whether mean circuit polarization exceeds 1/√e, corresponding to mirror-circuit effective polarizations of approximately 1/e.Source: §2 · p. 19

B. Estimating QUOPS circuit success: reference compilations

  • Three reference-compilation constructions address MCFE’s stochastic-error requirement: standard randomized compilation for exact physical-qubit circuits, and two synthesis-error methods for FTQC.Weighted synthesis randomization makes synthesis errors stochastic; depolarizing-channel insertion reproduces known infidelity and can bound polarization using one ensemble when logical Pauli gates are essentially error free.Source: B. Estimating QUOPS circuit success:… · p. 19

1. Standard randomized compilation

  • Standard randomized compilation exactly compiles QUOPS circuits, then uses Pauli-frame randomization to yield approximately stochastic errors when at least one stated single-qubit-error condition holds.The conditions are small single-qubit errors relative to two-qubit errors, approximately gate-independent single-qubit errors, or predominantly stochastic single-qubit errors.Source: §1 · p. 20

2. Weighted synthesis randomization

  • Weighted synthesis randomization prevents coherent cancellation of FTQC gate-synthesis errors by sampling weighted approximations that convert them into incoherent error.The method combines two synthesized approximations and their conjugates for each Pauli-axis rotation; it requires approximately stochastic errors on H, T, S, X, Y, and Z gates.Source: §2 · p. 20

3. Depolarizing channel insertion

  • The depolarizing-channel insertion estimator accurately incorporates synthesis-induced polarization loss in noiseless simulations across QUOPS circuit shapes and sizes.The method inserts sampled logical Pauli errors with probability equal to each synthesized rotation’s process infidelity, enabling a lower bound from one circuit ensemble; the plotted comparison uses the 1/√e benchmark threshold.Source: §3 · pp. 20–21, Figure 6 · p. 21

C. Estimating QUOPS circuit ensemble success

  • The QUOPS ensemble-success estimator combines effective-polarization estimates across sampled QUOPS and mirror circuits, with a lower-variance approximation that can slightly overestimate success.The approximation assumes a covariance term that is typically small and negative; uncertainty is quantified by bootstrapping circuits and executions to obtain a standard deviation and one-sided 95% lower confidence bound.Source: C. Estimating QUOPS circuit ensemble… · pp. 21–22

D. Estimating QUOPS capability regions and scores

  • QUOPS requires score estimates to be lower bounds with at least 95% confidence and capability-region estimates to have at least 90% confidence.The procedures use per-shape hypothesis tests, gated or wagering score tests, and multiple comparisons for the remaining shapes; α is 1/√e for standard scores and regions, and lower for error-mitigated ones.Source: D. Estimating QUOPS capability regions… · p. 22

1. The QUOPS test at a single circuit shape

  • At each tested shape, QUOPS estimates mean process polarization and its standard deviation using a bootstrap that accounts for sampled circuits and circuit executions.The shape-specific estimate uses Eq. (53) or Eq. (54), and the bootstrap resamples circuits within each mirror-circuit ensemble.Source: §1 · p. 23
  • At one circuit shape, the QUOPS test rejects the null that the shape lies outside the capability region only when its one-sided p-value is at most δ, controlling false passes for that shape.Because score and capability-region estimates combine outcomes across shapes, the section uses gated testing for the score and family-wise error control for the additional shapes used in the region.Source: §1 · p. 23

2. Estimating the QUOPS score with gated tests

  • The gated score procedure tests a prespecified increasing-size sequence at δ = 0.05, stops at the first failure, and estimates the score from the last shape that passed.It gives 95% confidence without correcting for the number of tests, provided the sequence is fixed independently of test data and each shape uses independent test data. Because the first failure spends the full significance budget, an unexpectedly early failure prevents testing other shapes to raise the estimate.Source: §2 · p. 23

3. Estimating the QUOPS capability region

  • Hochberg’s step-up procedure controls the family-wise error rate at 5% for shapes outside the gated sequence, and the estimated capability region is their successful shapes combined with gated passes and downward closure.The resulting region has 90% confidence if true polarization is non-increasing in width and size; without that assumption, the guarantee applies to declared-successful tested shapes, not their downward closure.Source: §3 · p. 24

4. Significance wagering: a flexible procedure for estimating the QUOPS score

  • Significance wagering permits adaptive choices of circuit shapes and test levels while controlling the probability of any false pass at a total significance budget of 0.05.A failed test adds its wager to the spent budget, while a passed test leaves it unchanged; validity requires fixing each shape and wager before testing and using data not used in earlier tests.Source: §4 · p. 24

E. Estimating QUOPS rate

  • The operational QUOPS rate uses estimated process polarization and mirror-circuit execution time and counts to measure useful operations per second while accounting for execution overheads and proxy circuits.Its execution-count estimate accounts for accepted and rejected shots, and the definition includes a factor of 2 because mirror circuits are approximately twice as deep as the corresponding QUOPS circuits; the rejection adjustment is a heuristic.Source: E. Estimating QUOPS rate · p. 25

V. QUOPS TARGETS FROM CHALLENGE PROBLEMS

The section translates challenge-problem resource estimates into comparable QUOPS score and rate targets, then describes a simplified resource-modeling pipeline for projecting QUOPS on surface-code fault-tolerant devices. The forecasts rely on explicit device, error-budget, and scheduling assumptions, and their explored circuit sizes are bounded by the cultivation data used.

V. QUOPS TARGETS FROM CHALLENGE PROBLEMS

  • Targets match a QUOPS circuit’s non-Clifford resource budget to the algorithm’s, using four T gates per Toffoli and a 1/√e polarization threshold.The model neglects Clifford errors and assumes stochastic, independent errors; the target is reached by optimizing the synthesized-rotation T count.Source: §V · pp. 25–26
  • The QUOPS targets are 2.5 × 10^8 for RSA-2048 and 3.4 × 10^8 for FeMoco, with required rates of 5.7 × 10^3 and 8.0 × 10^2 QUOPS/s, respectively.The target sizes are compared at algorithm widths of 1399 and 1459 logical qubits; the rate targets use a five-day completion budget.Source: §V · p. 26
  • The conversion assumes a specific synthesis cost model and neglects Clifford and idling errors as well as structural differences between algorithm and random circuits.The authors state these approximations do not affect the main-text conclusions because current scores are about five orders of magnitude below targets.Source: §V · p. 27

A. Surface code with 2D-planar-grid connectivity

  • The surface-code projections use a 2D local-qubit device family with fixed cycle time, reaction time, and depolarizing physical noise assumptions.The projected devices use the logical gate set {H, S, S†, T, CNOT}, with lattice-surgery CNOTs and cultivated T states.Source: A. Surface code with 2D-planar-grid… · p. 27

1. Estimating circuit polarizations using FLASQ

  • Simplified FLASQ estimates circuit success from logical operations, device resources, reaction time, and per-gate ancilla volumes, accounting for routing, Clifford work, ancillas, and magic-state preparation.Its coarse-grained outputs include logical timesteps, spacetime volume, and consumed magic states.Source: §1 · pp. 27–28

2. Compilation model and error budget

  • The projections compile QUOPS rotations into Clifford+T and split the allowable error budget evenly among Clifford errors, T-state infidelity, and rotation synthesis error.The equal split is a uniform heuristic; the authors note optimized budgets could yield higher QUOPS.Source: §2 · p. 28

3. Simplifying assumptions

  • The simplified forecasts assume spacetime-limited computations and set the number of data logical qubits equal to benchmark width, replacing detailed active-qubit accounting.These assumptions reduce the estimate to aggregate resource counts rather than a detailed operation schedule.Source: §3 · p. 28

4. Predicted QUOPS

  • To make large-circuit forecasts tractable, the analysis samples QUOPS circuits and rotations, estimates gate counts, then scans code distances for the success threshold.The cultivation data impose an explored-size limit of O(10^6), which the authors say could be removed with distillation or a lower-error cultivation protocol.Source: §4 · pp. 28–29

5. Projected QUOPS for hypothetical fault-tolerant devices

For the modeled surface-code devices, predicted QUOPS rises with physical-qubit budget, while width and size limits reflect device resources and magic-state quality. The fully connected projections use explicit scheduling and a fitted cost model to estimate capability regions across logical architectures.

5. Projected QUOPS for hypothetical fault-tolerant devices

  • Predicted QUOPS rises with device size: 5,000 physical qubits yield about 1,950 at width 13, while 50,000 yield 273,632 at width 68.The intermediate estimates are 9,240 at width 21 for 10,000 qubits and 68,470 at width 41 for 25,000 qubits.Source: §5 · p. 29
  • At high widths, physical-qubit limits constrain capability, while cultivation’s achievable magic-state fidelity ultimately caps circuit sizes and can shift the dominant bottleneck.The modeled bottleneck can move from logical spacetime overhead to non-Clifford resource quality as device scale increases.Source: §5 · p. 29

B. Fully connected FTQC architectures

  • The fully connected projections explicitly compile and schedule QUOPS circuits, then fit execution times and logical errors to an approximate model extrapolated across circuit shapes.They cover surface-code and concatenated symplectic double-code architectures on all-to-all physical connectivity.Source: B. Fully connected FTQC architectures · p. 29

1. Architectural assumptions

  • The all-to-all hardware model compares surface-code and concatenated symplectic double-code implementations with different logical-gate, error-correction, and magic-state protocols.Both architectures assume scalable correlated decoding permits one syndrome-extraction round after logical gadgets.Source: §1 · pp. 29–30

2. Methodology

  • A dynamic scheduler tracks code-block lifetimes, state preparation, failures, corrections, and idling error correction to estimate achievable logical-layer parallelism.The remaining error budget can be flexibly divided between error correction and consumed magic states, with the proportion depending on circuit shape.Source: §2 · p. 30

3. Approximate model

  • The approximate model captures a trade-off between idling error and magic-state injection, with per-layer time set by T injection or available magic-state preparation.Its fitted cost model agrees with observed data and with observed pass/fail brackets for modeled frontiers.Source: §3 · pp. 30–31

4. QUOPS capability regions

  • Capability frontiers combine fitted maximum passing sizes by width with a device-specific maximum width set by available space for code blocks and magic-state preparation.The model distinguishes magic-state-preparation-limited regimes and excludes data-qubit reuse.Source: §4 · p. 31

VII. QUANTINUUM EXPERIMENTS

The Quantinuum experiments span physical-qubit tests on Helios-1 and H2-1 and logical-qubit tests on Helios-1. The logical Steane-code experiments reached 40 QUOPS at width four, using synthesized rotations and runtime randomization.

A. Helios-1

  • Helios-1 offers all-to-all connectivity, real-time classical compute and ion routing, and native Rϕ, Rz, and Rzz gates; its dominant errors arise from two-qubit gates and transport.Typical errors are around 8×10^-4 for two-qubit gates and 5×10^-4 per qubit per dense layer of two-qubit gates.Source: A. Helios-1 · p. 31, §1 · p. 31

2. Real-time engine control, Guppy, and Selene

  • Helios-1’s runtime maps virtual operations to physical operations and makes transport decisions during execution, while Guppy supports dynamic allocation and control flow and Selene emulates Guppy programs.Selene’s stabilizer simulation was validated against state-vector simulation up to 24 qubits.Source: §2 · pp. 32–33

3. Helios-1 compiler options

  • Helios-1 compiler options include leakage repumping, dynamical decoupling, and single-qubit gate squashing; physical experiments enabled gate squashing, with compilation barriers preserving MCFE assumptions.Leakage repumping reduces leaked population exponentially with cycle number, and dynamical decoupling inserts canceling X gates during long idle periods.Source: §3 · p. 33

4. Timing and QUOPS rate

  • Timed QUOPS rates include overheads encountered in normal operation, with experiment times measured from the first shot through the last shot.Untimed data points were submitted through the normal fair-queue system.Source: §4 · p. 33

B. H2-1

  • H2-1 shares all-to-all connectivity and Helios-1’s native gates, but computes ion transport before execution, requiring control flow to be unrolled at compile time.Its leakage-detection gadget flags shots for discard and was used only for circuits with w < 56.Source: B. H2-1 · pp. 33–34

1. Summary

  • The Steane-code experiments reached 40 QUOPS at width 4, with mirrored circuits averaging 20 CNOT gates and 20 T gates.The experiments used up to eight logical qubits.Source: §1 · p. 34

2. Synthesis of RP(θ) rotations

  • Logical circuits used B = 3-bit rotation synthesis, accounting for synthesis error with depolarizing channels; per-shot randomization reduces polarization-estimator variance for a fixed shot count.At (w, s) = (4, 40), B = 3 yields about 77.3% polarization without noise; no compilation beyond synthesis was applied.Source: §2 · p. 34, §1 · p. 34, §3 · p. 35

4. Baseline Steane code implementation (v1)

  • The baseline implementation used repeat-until-success state preparation, teleportation-based T-gate injection, transversal Clifford gates, and flag-based real-time QEC after selected rotations and CNOT layers.QEC followed each synthesized rotation requiring a T or T† gate and every CNOT layer.Source: §4 · p. 35

5. Optimized Steane code implementation (v2)

The optimized Steane implementation improved parallel execution and reduced estimator variance through per-shot circuit randomization. Its reported T-count distribution is for the fully fault-tolerant v3 experiment.

5. Optimized Steane code implementation (v2)

  • The optimized implementation retains the baseline QEC policy, correcting after rotations requiring magic-state injection and after each CNOT.The cited T-count distribution reports T-QUOPS QT = 10 for the v3 experiment, not v2.Source: §5 · p. 35, Figure 10 · p. 36
  • Randomizing the circuit on every shot reduces polarization-estimator variance when random circuits have substantially varying T counts.The T-count distribution caption identifies the size-40, width-4 experiment as the fully fault-tolerant v3 implementation; its mirrored-circuit median is 20.Source: §5 · p. 35, Figure 10 · p. 36
  • Pairing blocks that need QEC lets their gates and measurements run in parallel, reducing circuit execution time and memory error.An unpaired block is processed separately.Source: §5 · p. 35
  • The optimized magic-state protocol prepares |H⟩ by repeat-until-success, rotates it into |T⟩, and uses a limit of three attempts that was never reached in these experiments.The experiments therefore required no postselection from hitting that RUS limit.Source: §5 · p. 35

6. Fully fault tolerant Steane code implementation (v3)

The v3 Steane implementation changes QEC and decoding so fault tolerance holds when gadgets are composed. Its simulated logical error rate scales as p^2, unlike the v2 departure from that scaling at sufficiently small p.

6. Fully fault tolerant Steane code implementation (v3)

  • The v3 QEC policy preserves fault tolerance across composed gadgets, unlike the earlier policy, where a single fault could propagate to a logical error with probability O(p).The revised policy inserts QEC only where needed to retain this property at distance three.Source: §6 · p. 36
  • Frame tracking and correlated error correction keep encoded QUOPS circuits fault tolerant at distance three by correcting frame-dependent errors at critical boundaries.Correlated decoding is required before CNOT use or destructive measurement when a block’s frame permits correctable errors to propagate.Source: §6 · p. 36
  • The correlated-QEC teleportation procedure combines complementary syndrome measurements and decodes them with a frame-specific lookup table.Strictly fault-tolerant resource-state preparation suppresses incompatible mixed-Pauli errors from O(p) to O(p^2).Source: §6 · p. 36
  • For (w, s) = (4, 40), simulated logical error rates for v3 are consistent with p^2 scaling, while v2 departs from p^2 at sufficiently small p.The simulations used Cliffordized gadgets and a uniform depolarizing error model, without stochastic Paulis for synthesis error.Source: Figure 11 · p. 37
  • Parallel state factories prepare resource states for pairs of T gates, while optimized repeat-until-success magic-state preparation reduces overhead while preserving fault tolerance.A successful state can be used while a failed preparation is retried; four initial |0L⟩ states are attempted in parallel.Source: §6 · pp. 36–37

7. Estimating QUOPS and architecture-specific QUOPS

The section estimates QUOPS scores and architecture-specific gate counts, then uses Clifford simulation to map Helios-1’s emulated logical capability region. The emulated region is bounded by synthesis precision and shows a weak size falloff with more Steane blocks.

7. Estimating QUOPS and architecture-specific QUOPS

  • The size-(4, 40) logical experiment has T-QUOPS QT = 10, obtained as the median compiled-circuit T count.For gate-count estimation, Cliffordized S-state injection substitutes for T-state injection while preserving the physical one- and two-qubit gate locations.Source: §7 · p. 37
  • For 105 simulated size-(4, 40) circuits, the fully fault-tolerant implementation had architecture-specific QUOPS Qarch = 4189(3).The estimate uses κ(Rϕ) = 1, κ(Rzz) = 2, and κ(Rz) = 0, with a 68% bootstrap confidence interval for the median.Source: §7 · p. 37

8. Full emulated capability region

  • The emulated capability region uses Clifford simulations with S and S† injection in place of T and T†, with RUS limited to three attempts.The sampled distributions vary with both T-count fluctuations and repeat-until-success state preparation.Source: §8 · pp. 37–38
  • With B = 3-bit precision, the emulated region has a synthesis-limited size near 70 and a weak falloff in maximum size as Steane-block count increases.The falloff is attributed to ion-transport phase errors; width-2 maximum size is finite because circuits are not compiled beyond rotation synthesis.Source: §8 · p. 38

D. Physical experiments

The physical experiments use mirror-circuit fidelity estimation (MCFE) to assess Helios-1 and H2-1, with emulation used to fill out Helios-1’s capability region. The procedures cover circuit construction, sampling, leakage handling, and confidence estimation.

D. Physical experiments

  • Helios-1 physical experiments use MCFE, with randomized circuit ensembles and runtime randomization; each data point uses K = 10 circuits and typically even widths.Widths and sizes were selected to maximize the ratio of two-qubit to one-qubit gates; widths were even except for w = 98.Source: D. Physical experiments · p. 38, §1 · p. 38

1. Helios-1 MCFE circuit class construction

  • B = 3 precision limits the logical Helios-1 simulated circuit sizes to ≲70; v3 matches v2’s score of s = 40 with an improved QUOPS rate.The figure’s heatmap estimates polarization from Clifford simulations of 104 circuits and is interpolated in size.Source: Figure 13 · p. 38

2. H2-1 MCFE circuit class construction

  • H2-1 uses Pauli frame randomization in both mirror halves, reducing sampling needs to the M2 and M3 ensembles.Ten circuits define M2 instances, sampled 200 times each; per-shot randomization uses classical registers.Source: §2 · p. 39

3. Ternary measurements on Helios-1

  • Helios-1’s ternary measurement enables leakage postselection; without postselection, leaked outcomes can be replaced randomly with 0 or 1 under state-independent leakage.The reconstruction relies on leaked-qubit binary outcomes being equally likely after measurement randomization.Source: §3 · p. 39

D. Physical experiments

  • Physical H2-1 results are reported in Table IV, where a result passes only if its 95% confidence interval’s lower endpoint exceeds 1/√e.The table caption also identifies leakage postselection and notes additional SPAM shots for each point.Source: Table IV · p. 40

4. Full emulated Helios-1 capability region

  • Helios-1 capability-region estimates use Clifford substitutions and simulations, with the physical dataset’s heatmap interpolated across width and size.The emulated region uses 10^5 shots per circuit to reduce finite-sampling effects.Source: §4 · p. 40, Figure 14 · p. 40

VIII. GOOGLE EXPERIMENTS

The Willow experiments map its QUOPS capability region while limiting circuit counts. Circuits are routed and compiled for the device’s connectivity before mirror-circuit ensembles are simulated to estimate process fidelity.

A. Circuit construction

  • Circuit shapes were selected iteratively from simulated polarization, with denser size sampling near the success threshold and exponential spacing elsewhere.Sampling returned to exponential spacing after measured polarization fell below threshold, continuing until it approached zero.Source: A. Circuit construction · p. 40
  • Willow’s circuits use optimized layouts and routing for its non-all-to-all connectivity, then undergo randomized compilation for the mirror-circuit ensembles.CNOT gates are compiled to CZ gates and single-qubit gates to PhasedXZ gates; mirroring barriers prevent other compilation.Source: A. Circuit construction · p. 40

B. Experiments

The Willow rate experiment targets the rate at its maximizing circuit shape, while simulations estimate capability and rate using a device noise model. This section also introduces IBM Boston experiments and their circuit construction.

B. Experiments

  • The Willow rate experiment passes the success threshold at its maximizing shape (6, 216), matching the capability-region experiment’s QUOPS while optimizing the rate measurement.It uses 25 circuits with 500,000 shots each, trading runtime for a rate-optimized experiment.Source: B. Experiments · pp. 40–41

C. Simulations

  • Q = 144 at (6, 144) with a simulated Willow QUOPS rate of 7.69 × 10^6 QUOPS/s; error mitigation reaches Q∗ = 512 at (8, 512).The error-mitigated estimate has overhead 80 and rate 8.42 × 10^5 QUOPS/s; simulation is truncated at width 10 because wider circuits are costly to simulate.Source: C. Simulations · p. 41, Figure 15 · p. 42

D. Estimating the QUOPS rate

  • Willow’s rate measurement uses 5 × 10^5 shots to optimize throughput, including unavoidable control and measurement overheads but excluding interleaved user jobs.The simulated-rate estimate uses measured shot, circuit, and batch durations for shape (6, 216), so rates at other shapes may misestimate depth-related time.Source: D. Estimating the QUOPS rate · p. 41

A. Circuit construction

  • IBM Boston experiments use qiskit routing and compilation, with circuits mirrored and recompiled across layer barriers before execution.The 156-qubit Heron R3 experiments used 100 circuits per shape and 200 reference circuits per width.Source: A. Circuit construction · p. 42, §IX · p. 42

B. Experiments

IBM Boston’s physical experiments use 100 circuits per shape, while simulations estimate its capability using IBM’s noise model. Experimental rate estimates approximate batch throughput, and simulated runtimes use gate, reset, delay, and loading assumptions.

B. Experiments

  • Physical IBM Boston experiments use 100 circuits per shape and 200 reference circuits per width.The processor is the 156-qubit ibm boston Heron R3.Source: B. Experiments · p. 42

C. Simulations

  • IBM Boston simulation reaches Q = 204 at (6, 204) with estimated rate 5.72 × 10^5; error mitigation reaches Q∗ = 1344 at (12, 1344), with overhead 3629 and rate 2.08 × 10^3.The simulated capability region is truncated at width 12 because wider circuits were too costly to simulate.Source: C. Simulations · p. 42

D. Estimating the QUOPS rate

  • Experimental IBM rates are approximated from batch QUOPS and wall-clock time, then multiplied by measured polarization; this intermixes circuit shapes.The authors expect loading and resetting overheads to dominate circuit runtime, mitigating the effects of mixing shapes; simulated runtimes assume 250 μs repetition delay, 2.2 μs reset, and 2 seconds to load a 500-circuit batch.Source: D. Estimating the QUOPS rate · p. 43

X. EXTRAPOLATED CAPABILITY REGIONS

The section extrapolates capability regions by fitting polarization decay against circuit size, then uses quantum-volume data to estimate QUOPS scores and relate success thresholds.

X. EXTRAPOLATED CAPABILITY REGIONS

  • α = 0.01 permits sampling overhead up to 10^4, but these regions extend beyond measured circuit sizes and depend on heuristic assumptions.The extrapolated QUOPS-rate estimate also assumes raw-rate variation is small relative to polarization attenuation; it is expected to be accurate to the correct order of magnitude.Source: §X · pp. 43–44
  • At fixed width, polarization is modeled as exponentially decaying with circuit size; a one-sided 95% upper bound on the fitted decay rate defines the extrapolated region.Figure 17 displays the confidence intervals across systems and widths.Source: §X · p. 43

XI. ESTIMATING QUOPS SCORES FROM QUANTUM VOLUME DATA

  • For IBM and Quantinuum, quantum-volume data are converted to approximate QUOPS scores by translating success thresholds and circuit resources using platform-specific procedures.The estimates are intended to establish trends over years, not precise scores.Source: §XI · p. 44

A. Relating success thresholds

  • For large circuits, the quantum-volume pass threshold corresponds to polarization of about 0.48, below QUOPS's 1/√e ≈ 0.61 threshold.The conversion accounts for this difference when relating executable gate counts.Source: A. Relating success thresholds · p. 45

B. Method 1: Matching compiled gate counts

The IBM conversion matches compiled CNOT budgets for quantum-volume and QUOPS circuits, producing a smoothed size relation for historical estimates.

B. Method 1: Matching compiled gate counts

  • For each width, the procedure compiles 20 quantum-volume circuits and candidate QUOPS circuits, then selects the QUOPS size whose CNOT count best matches the threshold-adjusted budget.The candidate-size search uses bisection because compiled CNOT count increases monotonically with size, up to sampling fluctuations.Source: B. Method 1: Matching compiled gate… · p. 45
  • The conversion assumes two-qubit gates dominate errors and share the same per-gate polarization decay across compiled circuit families; routing costs help explain the fitted prefactor.The approximation is used because residual variation is smaller than uncertainty from coupling map, compiler, and other approximations.Source: B. Method 1: Matching compiled gate… · p. 45
  • Converted QUOPS sizes are well described by s⋆(n) ≈ 2.5n^2, with deviations of at most 20%.The plotted trend uses this smooth approximation rather than individual converted values.Source: B. Method 1: Matching compiled gate… · p. 45, Table VII · p. 45

C. Method 2: Inferring two-qubit gate fidelity

The Quantinuum method infers two-qubit gate fidelity from quantum-volume heavy-output data, converts it to QUOPS scores, and fits processor trends over time.

C. Method 2: Inferring two-qubit gate fidelity

  • The conversion adjusts arbitrary-angle gate infidelity to maximally entangling-gate infidelity, then estimates QUOPS size by setting circuit polarization to 1/√e.It assumes a relation between the two gate-error levels and neglects single-qubit gate errors.Source: C. Method 2: Inferring two-qubit gate… · pp. 45–46
  • For 23 quantum-volume experiments, inferred H2-2 (2025) two-qubit infidelity was 1.4 × 10^-3, and H2-1 (2024) infidelity was 2 × 10^-3, close to independently benchmarked errors.The method derives circuit polarization from heavy-output data, removes an assumed per-qubit SPAM contribution, then infers arbitrary-angle gate fidelity.Source: C. Method 2: Inferring two-qubit gate… · pp. 45–46
  • H2-1's April 2025 quantum-volume estimate was 1.1 × 10^3 QUOPS, close to its directly measured 1320 QUOPS in 2026.The comparison is one of the reported consistency checks for the conversion procedure.Source: C. Method 2: Inferring two-qubit gate… · p. 46

D. Trend lines

  • Fitted QUOPS-score doubling times were 2.1 years for IBM and 1.4 years for Quantinuum.The Quantinuum fit combines 23 quantum-volume-derived estimates with direct 2026 measurements on H2-1 and Helios-1.Source: D. Trend lines · p. 46

E. Limitations

The historical conversions rely on simplifying assumptions and are coarse estimates, supporting multi-year trends rather than point-in-time processor comparisons.

E. Limitations

  • The conversions assume global depolarizing noise, two-qubit gates as the sole error source, exponential polarization decay with gate count, and fixed conversion constants.The IBM conversion additionally assumes a square-grid architecture and a specific compiler unlike the processors' heavy-hexagonal connectivity and IBM compilation.Source: E. Limitations · p. 46
  • Quantum-volume estimates are coarse because QV is a binary pass/fail lower bound, whereas Quantinuum heavy-output data resolve how far each test passed.Individual estimates are expected to be accurate to within a factor of about two.Source: E. Limitations · p. 46
  • The estimates are sufficient to identify multi-year trends, but not to compare processors at a single point in time.Direct QUOPS measurements avoid the assumptions used in the historical conversions.Source: E. Limitations · p. 46
Loading 2609.12146v1…