Circuit-MLLM: Topological Logic-Guided Latent-Space Visual Reasoning for Circuit Schematic Understanding

1 Introduction

• Circuit schematics remain challenging for MLLMs because dense component layouts and intricate topological dependencies make schematic parsing difficult for EDA applications.The introduction describes schematic parsing as pivotal for automating circuit analysis and accelerating chip design.Source: §1 · p. 1
• Visual Chain-of-Thought methods use region-centric localization that can fragment long wires, while traditional detector and conversion pipelines risk error propagation and engineering overhead.Circuit schematics’ irregular topology is also difficult to describe precisely in natural language.Source: §1 · p. 2
• Existing latent-space methods capture coarse regions and default to raster-scan order, missing fine-grained connections and misaligning reasoning with circuit topology.The introduction identifies both scarce fine-grained features and missing topology-driven sequence as challenges.Source: §1 · p. 3
• Circuit knowledge mining uses vision experts to produce fine-grained latent circuit representations without increasing inference overhead.The method is intended to improve topology recognition accuracy.Source: §1 · p. 3
• Topology-guided sequencing decouples latent reasoning from raster scanning by aligning inference with circuit structure and tracing from a root component along wires to a target.The framework is presented as latent-space reasoning for complex circuit topology analysis.Source: §1 · p. 3
• 25% higher average score than GPT-5.1 across diverse circuit analysis tasks, with up to 26% higher performance than latent-space visual baselines on topology reasoning tasks.The reported results compare Circuit-MLLM with GPT-5.1 and latent-space visual baselines, respectively.Source: §1 · p. 3

2.1 Automated Circuit Schematic Topology Extraction

• The annotation workflow collected 12,000 schematics, labeled a subset, then used YOLO11, OCR, pixel tracking, and expert review to produce netlist-style descriptions, visual grounding, and pixel-level masks.It also constructed latent-space reasoning QA pairs and Circuit-MLLM-Bench.Source: §2.1 · p. 4

2.2 Related Works

• Prior circuit-understanding methods use detector-guided reasoning or convert schematics to netlists for text LLMs, while latent visual reasoning aligns intermediate image features with latent vectors.The reviewed tool and conversion pipelines can suffer error propagation and engineering overhead; prior latent methods can overlook intrinsic logical chains.Source: §2.2 · pp. 4–5

2.3 Visual Attribution of MLLMs in Circuit Analysis

• In an unguided Qwen-2.5-VL 7B analysis, attention followed a root-to-device path along wires and concurrently tracked branches from a shared node.The passage contrasts parallel branch attention with the typically serial, branch-by-branch human visual process.Source: §2.3 · pp. 5–6
• The framework combines expert-level circuit representation vectors, topology-ordered latent reasoning, and joint latent-feature alignment with explicit text supervision.These are the three elements identified in the framework overview.Source: Figure 4 · p. 6

3.1 Latent-Space Circuit Knowledge Mining Mechanism

• Training-time expert guidance internalizes fine-grained circuit features without inference-time tools, using aligned HAWP, DeepLSD, and DINOv2 priors fused with original visual tokens as alignment targets.The experts provide wireframe and junction detection, fine-grained line segments, and patch-level semantic representations.Source: §3.1 · p. 7

3.2 Topology-Guided Sequencing Strategy

• A pixel-wise Topological Logic Mask assigns priorities from the root across wires and connected devices, then filters and sorts valid patch features into topological order.BFS distance encodes the near-to-far principle, and adaptive max pooling aligns the mask with patch-level features.Source: §3.2 · p. 8
• The ordered expert-enriched sequence is pooled to fixed length k and used as target vectors for sequential cosine-distance alignment of final-layer hidden states.The alignment constrains the model to traverse predefined topological trajectories.Source: §3.2 · p. 8

3.3 Text-Latent Joint Supervision Training

• Training combines topological latent-token alignment with autoregressive cross-entropy on preceding and succeeding text tokens, weighted by λ in the joint objective.The balancing coefficient λ weights the topological alignment loss alongside the text loss.Source: §3.3 · p. 9

4.1 Experimental Settings

• The human-verified Circuit-MLLM-Bench covers Connection Judgment and Connection Identification plus Total Count, Type Count, and Element Class; training uses 5,000 task-distributed instances.Training images are mutually exclusive from the evaluation set; implementation uses Qwen2.5-VL 7B, with latent size 4 and γ = 0.6.Source: §4.1 · pp. 9–10

4.2 Experimental Results

• On Circuit-MLLM-Bench, Circuit-MLLM leads all existing baselines in average performance, improving 57.8% relatively over backbone Qwen-2.5-VL-7B and approximately 22.5% over leading model GPT-4o.Table 1 compares performance across all task categories; “Avg.” denotes the overall average score.Source: §4.2 · p. 10, Table 1 · p. 10
• Approximately 3× the backbone’s EMR on connection identification; across topology tasks, Circuit-MLLM gains approximately 5% average score over Mirage and ILVR and 25% on hard identification EMR over ILVR.It also improves approximately 7% overall over SFT+GRPO, with gains up to 13% on specific tasks.Source: §4.2 · p. 11, Table 2 · p. 11

4.3 Ablation Study

• 72.26 average score, 2.41 above the 69.85 baseline, when sequencing and knowledge mining are combined; either component alone scores 70.61 or 70.64.The combined model also achieves the highest hard Connection Identification EMR, 28.52.Source: §4.3 · pp. 11–12, Table 3 · p. 12
• Latent size 4 yields the best overall score and is reported sufficient to encapsulate reasoning for conventional circuit problems.Latent size is the number of latent vectors generated during inference; the comparison fixes γ at 0.6.Source: §4.3 · p. 12, Table 4 · p. 12
• Using all three visual experts gives the highest average score; DINOv2 performs strongly on counting, while HAWP performs better on connection tasks.DINOv2 struggles with connection-related problems; the experts are DINOv2, HAWP, and DeepLSD.Source: §4.3 · pp. 12–13, Table 5 · p. 13

Latent Space Attention Analysis

• Circuit-MLLM localizes the root component, adjacent wires, and target component more precisely and at finer resolution than Mirage and ILVR.The reported heatmaps also show attention avoiding noise components and blank areas.Source: §5 · p. 14

Latent Space Visual Shift Analysis

• Across six consecutive latent vectors, attention moves from the root device along connecting wires and ultimately concentrates on the target device.Figure 6 shows global and localized heatmaps, including the root device, wire, and target device.Source: §5 · p. 14, Figure 6 · p. 14

6 Conclusion

• Circuit-MLLM embeds topological reasoning in latent space and combines circuit knowledge mining with topology-guided sequencing to improve complex topology analysis.The conclusion reports accurate focus on intended topological regions alongside significant performance improvements.Source: §6 · pp. 14–15

A.1 Chain-of-Thought Paradigms on Topological Tasks

• Visual CoT crops relevant regions before evaluating the original image and patches, whereas Textual CoT locates a root, traces connecting lines, then judges the target.These are the two compared CoT procedures.Source: §A.1 · p. 17, Figure 8 · p. 18
• Latent-Visual outperforms Textual CoT across almost all metrics; Visual CoT slightly improves Connection Identification but degrades Connection Judgment.The authors attribute Visual CoT’s degradation to wire-localization difficulty and cropping that disrupts continuous topology; they attribute Textual CoT’s weakness to error-prone coordinate sequences.Source: §A.1 · p. 17, Table 6 · p. 17

A.2 Sim Weight γ

• With latent size fixed at 4, performance across all tasks peaks at γ = 0.6 for Ltotal = γLtopo + Ltext.The paper states that latent-space alignment and text prediction mutually reinforce each other.Source: §A.2 · p. 18

• The AMSBench comparison includes closed- and open-source general-purpose MLLMs and Masala CHAI as an image-modification baseline.Source: §A.3 · p. 18
• 58% improvement over Qwen-2.5-VL 7B and an approximate 15% increase over GPT-4o on Connection Identification; Circuit-MLLM also leads baselines in Type Counting.Source: §A.3 · pp. 18–19, Table 7 · p. 19
• Circuit-MLLM underperforms GPT-5.1 on AMSBench Total Count, where regions of interest span the whole image and latent-space focusing is less effective.Source: §A.3 · p. 19
• Masala CHAI underperforms the Qwen-2.5-VL 7B backbone across almost all tasks, suggesting limited effectiveness of explicit pixel-level image modification.Source: §A.3 · p. 19

• Unlike AMSBench, Circuit-MLLM-Bench strictly evaluates MLLMs’ visual information extraction on circuit diagrams, using schematics from four non-benchmark datasets.The sources are AMSnet, AnalogGenie, Masala-Chai, and MAPs.Source: B Circuit-MLLM-Bench · p. 20
• After deduplication, automated topology extraction supports five task categories; all but Total Count generate multiple instances, producing over 20 QA pairs per image.The categories are Connection Judge, Connection Identification, Total Count, Type Count, and Element Class.Source: B Circuit-MLLM-Bench · p. 20, Figure 10 · p. 20
• The study evaluates a curated subset of 1,000 schematics with 1,000 QA pairs per task, or 5,000 total, reviewed automatically and manually by domain experts.The pipeline could generate hundreds of thousands of QA pairs across the full schematic corpus.Source: B Circuit-MLLM-Bench · p. 20

• Circuit-MLLM demonstrates superior performance to GPT-5.1 on complex, densely routed circuit connections.Source: C Case Studies on Topology Analysis… · p. 21
• Its latent-visual reasoning accurately identifies all interconnected components in the illustrated topology-analysis cases.Source: C Case Studies on Topology Analysis… · p. 21, Figure 11 · p. 21